[Qemu-devel] [RFC qom-cpu v2 00/28] CPUState QOM realizefn support

[Qemu-devel] [RFC qom-cpu v2 00/28] CPUState QOM realizefn support

[Andreas Färber]

Hello,

This series cleans up cpu_init() by moving code to QOM realizefn and initfn.
As a result, the following target CPUs become fully QOM-instantiatable:
arm, microblaze, openrisc, ppc, s390x and unicore32.
The other targets are still in need of model-specific CPU subclasses.

v2 fixes a bug with gdb arm coprocessor registration spotted by Eduardo and
adjusts m68k as well. It also appends patches to move code to initfn.

In response to conceptual questions raised by Eduardo, I'm letting each
target CPU call its parent's realizefn from the start. This requires knowledge
of what the parent does and how we want to interact with its implementation:
To avoid a local_err variable and dedicated error handling, and in light of
ideas to unify reset handling, the parent realizefn is called last.
NB this is not a general QOM'ism, e.g., CPUClass::reset calls it in the middle.

alpha and unicore32 are lacking a full CPUClass::reset implementation.
ppc, sparc and xtensa do not reset as part of cpu_init() today, still
blocking us from moving cpu_reset() into the base CPUState realizefn,
so that it remains empty (and optional) in this series.

Based on a few cleanups sent out for 1.4, but only cris and microblaze are
affected. Patches are strictly target-specific, so for testing arm just the
two target-arm patches can be picked, not strictly depending on patch 1 even.

I'd like to queue this on my qom-cpu-next branch for v1.5 as base for
further series. Still not fully tested but more so.

Available for testing and cherry-picking from:
git://github.com/afaerber/qemu-cpu.git qom-cpu-realize.v2
https://github.com/afaerber/qemu-cpu/commits/qom-cpu-realize.v2

Regards,
Andreas

v1 -> v2:
* arm: Register cp with gdb from realizefn, spotted by Eduardo.
* m68k: Perform gdb init from realizefn as well.
* Introduce a no-op realizefn at CPU level and call it from each target's realizefn.
* i386: Avoid error handling regression for APIC.
* s390x: Move cpu_reset() from initfn to realizefn.
* Stylistic changes (e.g., white line after NULL-errp object_property_set_bool())
* Appended patches moving TCG initialization from cpu_*_init() to initfn.

Changes from sh4 subclasses series:
* Adopted QOM realizefn signature, dropped error.h inclusion.

Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Richard Henderson <rth@twiddle.net> (alpha, s390)
Cc: Peter Maydell <peter.maydell@linaro.org> (arm)
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> (cris, microblaze)
Cc: Peter C. Crosthwaite <peter.crosthwaite@xilinx.com> (microblaze)
Cc: Michael Walle <michael@walle.cc> (lm32)
Cc: Aurélien Jarno <aurelien@aurel32.net> (mips, sh4)
Cc: Alexander Graf <agraf@suse.de> (ppc, s390)
Cc: qemu-ppc <qemu-ppc@nongnu.org>
Cc: Blue Swirl <blauwirbel@gmail.com> (sparc)
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> (unicore32)
Cc: Max Filippov <jcmvbkbc@gmail.com> (xtensa)
Cc: Jia Liu <proljc@gmail.com> (openrisc)

Andreas Färber (28):
  cpu: Prepare QOM realizefn
  target-alpha: Update AlphaCPU to QOM realizefn
  target-arm: Update ARMCPU to QOM realizefn
  target-i386: Update X86CPU to QOM realizefn
  target-openrisc: Update OpenRISCCPU to QOM realizefn
  target-ppc: Update PowerPCCPU to QOM realizefn
  target-cris: Introduce QOM realizefn for CRISCPU
  target-lm32: Introduce QOM realizefn for LM32CPU
  target-m68k: Introduce QOM realizefn for M68kCPU
  target-microblaze: Introduce QOM realizefn for MicroBlazeCPU
  target-mips: Introduce QOM realizefn for MIPSCPU
  target-s390x: Introduce QOM realizefn for S390CPU
  target-sh4: Introduce QOM realizefn for SuperHCPU
  target-sparc: Introduce QOM realizefn for SPARCCPU
  target-unicore32: Introduce QOM realizefn for UniCore32CPU
  target-xtensa: Introduce QOM realizefn for XtensaCPU
  target-arm: Move TCG initialization to ARMCPU initfn
  target-cris: Move TCG initialization to CRISCPU initfn
  target-lm32: Move TCG initialization to LM32CPU initfn
  target-m68k: Move TCG initialization to M68kCPU initfn
  target-microblaze: Move TCG initialization to MicroBlazeCPU initfn
  target-mips: Move TCG initialization to MIPSCPU initfn
  target-ppc: Move TCG initialization to PowerPCCPU initfn
  target-s390x: Move TCG initialization to S390CPU initfn
  target-sh4: Move TCG initialization to SuperHCPU initfn
  target-sparc: Move TCG initialization to SPARCCPU initfn
  target-unicore32: Move TCG initialization to UniCore32CPU initfn
  target-xtensa: Move TCG initialization to XtensaCPU initfn

 qom/cpu.c                     |    5 +++++
 target-alpha/cpu-qom.h        |    2 ++
 target-alpha/cpu.c            |   21 +++++++++++++++++----
 target-arm/cpu-qom.h          |    3 ++-
 target-arm/cpu.c              |   27 ++++++++++++++++++++-------
 target-arm/cpu.h              |    1 +
 target-arm/helper.c           |   18 +++++++++---------
 target-cris/cpu-qom.h         |    2 ++
 target-cris/cpu.c             |   25 +++++++++++++++++++++++++
 target-cris/cpu.h             |    3 +++
 target-cris/translate.c       |   22 ++++++----------------
 target-cris/translate_v10.c   |    5 +----
 target-i386/cpu-qom.h         |    5 ++---
 target-i386/cpu.c             |   19 +++++++++++++++----
 target-i386/helper.c          |    2 +-
 target-lm32/cpu-qom.h         |    2 ++
 target-lm32/cpu.c             |   22 +++++++++++++++++++++-
 target-lm32/helper.c          |    8 +-------
 target-m68k/cpu-qom.h         |    2 ++
 target-m68k/cpu.c             |   23 +++++++++++++++++++++++
 target-m68k/cpu.h             |    1 +
 target-m68k/helper.c          |   21 ++++++++++-----------
 target-microblaze/cpu-qom.h   |    2 ++
 target-microblaze/cpu.c       |   21 +++++++++++++++++++++
 target-microblaze/cpu.h       |    1 +
 target-microblaze/translate.c |   16 ++++++----------
 target-mips/cpu-qom.h         |    2 ++
 target-mips/cpu.c             |   19 +++++++++++++++++++
 target-mips/cpu.h             |    1 +
 target-mips/translate.c       |    8 ++++----
 target-openrisc/cpu.c         |   13 ++++++++++---
 target-openrisc/cpu.h         |    4 ++--
 target-ppc/cpu-qom.h          |    2 ++
 target-ppc/translate_init.c   |   21 +++++++++++++--------
 target-s390x/cpu-qom.h        |    2 ++
 target-s390x/cpu.c            |   21 ++++++++++++++++++++-
 target-s390x/helper.c         |    9 ++-------
 target-sh4/cpu-qom.h          |    2 ++
 target-sh4/cpu.c              |   19 +++++++++++++++++++
 target-sh4/cpu.h              |    1 +
 target-sh4/translate.c        |    8 ++++----
 target-sparc/cpu-qom.h        |    2 ++
 target-sparc/cpu.c            |   25 ++++++++++++++++++++-----
 target-unicore32/cpu-qom.h    |    3 +++
 target-unicore32/cpu.c        |   26 ++++++++++++++++++++++++++
 target-unicore32/helper.c     |    7 +------
 target-xtensa/cpu-qom.h       |    2 ++
 target-xtensa/cpu.c           |   21 +++++++++++++++++++++
 target-xtensa/cpu.h           |    1 +
 target-xtensa/helper.c        |   16 +++-------------
 50 Dateien geändert, 383 Zeilen hinzugefügt(+), 131 Zeilen entfernt(-)

-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 01/28] cpu: Prepare QOM realizefn

[Andreas Färber]

Overwrite the default implementation with a no-op, no longer
attempting to call DeviceClass::init.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 qom/cpu.c |    5 +++++
 1 Datei geändert, 5 Zeilen hinzugefügt(+)

diff --git a/qom/cpu.c b/qom/cpu.c
index 49e5134..cbc2d01 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -34,12 +34,17 @@ static void cpu_common_reset(CPUState *cpu)
 {
 }
 
+static void cpu_common_realizefn(DeviceState *dev, Error **errp)
+{
+}
+
 static void cpu_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     CPUClass *k = CPU_CLASS(klass);
 
     k->reset = cpu_common_reset;
+    dc->realize = cpu_common_realizefn;
     dc->no_user = 1;
 }
 
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 02/28] target-alpha: Update AlphaCPU to QOM realizefn

[Andreas Färber]

Update the alpha_cpu_realize() signature and hook up to
DeviceClass::realize. Set realized = true in cpu_alpha_init().

qapi/error.h is included through qdev now and no longer needed.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-alpha/cpu-qom.h |    2 ++
 target-alpha/cpu.c     |   21 +++++++++++++++++----
 2 Dateien geändert, 19 Zeilen hinzugefügt(+), 4 Zeilen entfernt(-)

diff --git a/target-alpha/cpu-qom.h b/target-alpha/cpu-qom.h
index 16367d2..c0f6c6d 100644
--- a/target-alpha/cpu-qom.h
+++ b/target-alpha/cpu-qom.h
@@ -34,6 +34,7 @@
 
 /**
  * AlphaCPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * An Alpha CPU model.
@@ -43,6 +44,7 @@ typedef struct AlphaCPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } AlphaCPUClass;
 
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 40e9809..9222731 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -21,14 +21,16 @@
 
 #include "cpu.h"
 #include "qemu-common.h"
-#include "qapi/error.h"
 
 
-static void alpha_cpu_realize(Object *obj, Error **errp)
+static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
 {
-    AlphaCPU *cpu = ALPHA_CPU(obj);
+    AlphaCPU *cpu = ALPHA_CPU(dev);
+    AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
 
     qemu_init_vcpu(&cpu->env);
+
+    acc->parent_realize(dev, errp);
 }
 
 /* Sort alphabetically by type name. */
@@ -130,7 +132,8 @@ AlphaCPU *cpu_alpha_init(const char *cpu_model)
 
     env->cpu_model_str = cpu_model;
 
-    alpha_cpu_realize(OBJECT(cpu), NULL);
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
     return cpu;
 }
 
@@ -244,6 +247,15 @@ static void alpha_cpu_initfn(Object *obj)
     env->fen = 1;
 }
 
+static void alpha_cpu_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc);
+
+    acc->parent_realize = dc->realize;
+    dc->realize = alpha_cpu_realizefn;
+}
+
 static const TypeInfo alpha_cpu_type_info = {
     .name = TYPE_ALPHA_CPU,
     .parent = TYPE_CPU,
@@ -251,6 +263,7 @@ static const TypeInfo alpha_cpu_type_info = {
     .instance_init = alpha_cpu_initfn,
     .abstract = true,
     .class_size = sizeof(AlphaCPUClass),
+    .class_init = alpha_cpu_class_init,
 };
 
 static void alpha_cpu_register_types(void)
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 03/28] target-arm: Update ARMCPU to QOM realizefn

[Andreas Färber]

Turn arm_cpu_realize() into a QOM realize function, no longer called
via cpu.h prototype. To maintain the semantics of cpu_init(), set
realized = true explicitly in cpu_arm_init().

Move GDB coprocessor registration, CPU reset and vCPU initialization
into the realizefn.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-arm/cpu-qom.h |    3 ++-
 target-arm/cpu.c     |   21 ++++++++++++++-------
 target-arm/cpu.h     |    1 +
 target-arm/helper.c  |   14 ++++++++++----
 4 Dateien geändert, 27 Zeilen hinzugefügt(+), 12 Zeilen entfernt(-)

diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 0f455c4..aff7bf3 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -33,6 +33,7 @@
 
 /**
  * ARMCPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * An ARM CPU model.
@@ -42,6 +43,7 @@ typedef struct ARMCPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } ARMCPUClass;
 
@@ -107,7 +109,6 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
 
 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
 
-void arm_cpu_realize(ARMCPU *cpu);
 void register_cp_regs_for_features(ARMCPU *cpu);
 
 #endif
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 07588a1..19d5ae4 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -147,15 +147,12 @@ static void arm_cpu_finalizefn(Object *obj)
     g_hash_table_destroy(cpu->cp_regs);
 }
 
-void arm_cpu_realize(ARMCPU *cpu)
+static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 {
-    /* This function is called by cpu_arm_init() because it
-     * needs to do common actions based on feature bits, etc
-     * that have been set by the subclass init functions.
-     * When we have QOM realize support it should become
-     * a true realize function instead.
-     */
+    ARMCPU *cpu = ARM_CPU(dev);
+    ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
     CPUARMState *env = &cpu->env;
+
     /* Some features automatically imply others: */
     if (arm_feature(env, ARM_FEATURE_V7)) {
         set_feature(env, ARM_FEATURE_VAPA);
@@ -197,6 +194,12 @@ void arm_cpu_realize(ARMCPU *cpu)
     }
 
     register_cp_regs_for_features(cpu);
+    arm_cpu_register_gdb_regs_for_features(cpu);
+
+    cpu_reset(CPU(cpu));
+    qemu_init_vcpu(env);
+
+    acc->parent_realize(dev, errp);
 }
 
 /* CPU models */
@@ -763,6 +766,10 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
 {
     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
     CPUClass *cc = CPU_CLASS(acc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    acc->parent_realize = dc->realize;
+    dc->realize = arm_cpu_realizefn;
 
     acc->parent_reset = cc->reset;
     cc->reset = arm_cpu_reset;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ffddfcb..2902ba5 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -234,6 +234,7 @@ typedef struct CPUARMState {
 
 ARMCPU *cpu_arm_init(const char *cpu_model);
 void arm_translate_init(void);
+void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 int cpu_arm_exec(CPUARMState *s);
 void do_interrupt(CPUARMState *);
 void switch_mode(CPUARMState *, int);
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 37c34a1..f412143 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1270,14 +1270,22 @@ ARMCPU *cpu_arm_init(const char *cpu_model)
     cpu = ARM_CPU(object_new(cpu_model));
     env = &cpu->env;
     env->cpu_model_str = cpu_model;
-    arm_cpu_realize(cpu);
+
+    /* TODO this should be set centrally, once possible */
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 
     if (tcg_enabled() && !inited) {
         inited = 1;
         arm_translate_init();
     }
 
-    cpu_reset(CPU(cpu));
+    return cpu;
+}
+
+void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
+{
+    CPUARMState *env = &cpu->env;
+
     if (arm_feature(env, ARM_FEATURE_NEON)) {
         gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
                                  51, "arm-neon.xml", 0);
@@ -1288,8 +1296,6 @@ ARMCPU *cpu_arm_init(const char *cpu_model)
         gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
                                  19, "arm-vfp.xml", 0);
     }
-    qemu_init_vcpu(env);
-    return cpu;
 }
 
 /* Sort alphabetically by type name, except for "any". */
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 04/28] target-i386: Update X86CPU to QOM realizefn

[Andreas Färber]

Adapt the signature of x86_cpu_realize(), hook up to
DeviceClass::realize and set realized = true in cpu_x86_init().

The QOM realizefn cannot depend on errp being non-NULL as in
cpu_x86_init(), so use a local Error to preserve error handling behavior
on APIC initialization errors.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Eduardo Habkost <ehabkost@redhat.com>
---
 target-i386/cpu-qom.h |    5 ++---
 target-i386/cpu.c     |   19 +++++++++++++++----
 target-i386/helper.c  |    2 +-
 3 Dateien geändert, 18 Zeilen hinzugefügt(+), 8 Zeilen entfernt(-)

diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
index 332916a..48e6b54 100644
--- a/target-i386/cpu-qom.h
+++ b/target-i386/cpu-qom.h
@@ -39,6 +39,7 @@
 
 /**
  * X86CPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * An x86 CPU model or family.
@@ -48,6 +49,7 @@ typedef struct X86CPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } X86CPUClass;
 
@@ -72,8 +74,5 @@ static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
 
 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
 
-/* TODO Drop once ObjectClass::realize is available */
-void x86_cpu_realize(Object *obj, Error **errp);
-
 
 #endif
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 333745b..c988ac5 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2140,10 +2140,14 @@ static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
 }
 #endif
 
-void x86_cpu_realize(Object *obj, Error **errp)
+static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
 {
-    X86CPU *cpu = X86_CPU(obj);
+    X86CPU *cpu = X86_CPU(dev);
+    X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
     CPUX86State *env = &cpu->env;
+#ifndef CONFIG_USER_ONLY
+    Error *local_err = NULL;
+#endif
 
     if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
         env->cpuid_level = 7;
@@ -2185,8 +2189,9 @@ void x86_cpu_realize(Object *obj, Error **errp)
     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
 
     if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
-        x86_cpu_apic_init(cpu, errp);
-        if (error_is_set(errp)) {
+        x86_cpu_apic_init(cpu, &local_err);
+        if (local_err != NULL) {
+            error_propagate(errp, local_err);
             return;
         }
     }
@@ -2195,6 +2200,8 @@ void x86_cpu_realize(Object *obj, Error **errp)
     mce_init(cpu);
     qemu_init_vcpu(&cpu->env);
     cpu_reset(CPU(cpu));
+
+    xcc->parent_realize(dev, errp);
 }
 
 static void x86_cpu_initfn(Object *obj)
@@ -2247,6 +2254,10 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
 {
     X86CPUClass *xcc = X86_CPU_CLASS(oc);
     CPUClass *cc = CPU_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    xcc->parent_realize = dc->realize;
+    dc->realize = x86_cpu_realizefn;
 
     xcc->parent_reset = cc->reset;
     cc->reset = x86_cpu_reset;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 547c25e..bf43d6a 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1280,7 +1280,7 @@ X86CPU *cpu_x86_init(const char *cpu_model)
         return NULL;
     }
 
-    x86_cpu_realize(OBJECT(cpu), &error);
+    object_property_set_bool(OBJECT(cpu), true, "realized", &error);
     if (error) {
         error_free(error);
         object_delete(OBJECT(cpu));
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 05/28] target-openrisc: Update OpenRISCCPU to QOM realizefn

[Andreas Färber]

Update the openrisc_cpu_realize() signature, hook it up to
DeviceClass::realize and set realized = true in cpu_openrisc_init().

qapi/error.h is now included through qdev and no longer needed.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-openrisc/cpu.c |   13 ++++++++++---
 target-openrisc/cpu.h |    4 ++--
 2 Dateien geändert, 12 Zeilen hinzugefügt(+), 5 Zeilen entfernt(-)

diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 7a55112..d0b2fc6 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -62,12 +62,15 @@ static inline void set_feature(OpenRISCCPU *cpu, int feature)
     cpu->env.cpucfgr = cpu->feature;
 }
 
-void openrisc_cpu_realize(Object *obj, Error **errp)
+static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
 {
-    OpenRISCCPU *cpu = OPENRISC_CPU(obj);
+    OpenRISCCPU *cpu = OPENRISC_CPU(dev);
+    OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
 
     qemu_init_vcpu(&cpu->env);
     cpu_reset(CPU(cpu));
+
+    occ->parent_realize(dev, errp);
 }
 
 static void openrisc_cpu_initfn(Object *obj)
@@ -117,6 +120,10 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 {
     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
     CPUClass *cc = CPU_CLASS(occ);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    occ->parent_realize = dc->realize;
+    dc->realize = openrisc_cpu_realizefn;
 
     occ->parent_reset = cc->reset;
     cc->reset = openrisc_cpu_reset;
@@ -165,7 +172,7 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
     cpu = OPENRISC_CPU(object_new(cpu_model));
     cpu->env.cpu_model_str = cpu_model;
 
-    openrisc_cpu_realize(OBJECT(cpu), NULL);
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 
     return cpu;
 }
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 3beab45..419f007 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -33,7 +33,6 @@ struct OpenRISCCPU;
 #include "exec/cpu-defs.h"
 #include "fpu/softfloat.h"
 #include "qom/cpu.h"
-#include "qapi/error.h"
 
 #define TYPE_OPENRISC_CPU "or32-cpu"
 
@@ -46,6 +45,7 @@ struct OpenRISCCPU;
 
 /**
  * OpenRISCCPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * A OpenRISC CPU model.
@@ -55,6 +55,7 @@ typedef struct OpenRISCCPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } OpenRISCCPUClass;
 
@@ -340,7 +341,6 @@ static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
 #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
 
 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
-void openrisc_cpu_realize(Object *obj, Error **errp);
 
 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
 int cpu_openrisc_exec(CPUOpenRISCState *s);
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 06/28] target-ppc: Update PowerPCCPU to QOM realizefn

[Andreas Färber]

Adapt ppc_cpu_realize() signature, hook it up to DeviceClass and set
realized = true in cpu_ppc_init().

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-ppc/cpu-qom.h        |    2 ++
 target-ppc/translate_init.c |   12 +++++++++---
 2 Dateien geändert, 11 Zeilen hinzugefügt(+), 3 Zeilen entfernt(-)

diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index b338f8f..2b82cdb 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -40,6 +40,7 @@
 
 /**
  * PowerPCCPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * A PowerPC CPU model.
@@ -49,6 +50,7 @@ typedef struct PowerPCCPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 
     /* TODO inline fields here */
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 2d78529..63ba4a5 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -10029,9 +10029,9 @@ static int ppc_fixup_cpu(PowerPCCPU *cpu)
     return 0;
 }
 
-static void ppc_cpu_realize(Object *obj, Error **errp)
+static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
 {
-    PowerPCCPU *cpu = POWERPC_CPU(obj);
+    PowerPCCPU *cpu = POWERPC_CPU(dev);
     CPUPPCState *env = &cpu->env;
     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
     ppc_def_t *def = pcc->info;
@@ -10071,6 +10071,8 @@ static void ppc_cpu_realize(Object *obj, Error **errp)
 
     qemu_init_vcpu(env);
 
+    pcc->parent_realize(dev, errp);
+
 #if defined(PPC_DUMP_CPU)
     {
         const char *mmu_model, *excp_model, *bus_model;
@@ -10342,7 +10344,7 @@ PowerPCCPU *cpu_ppc_init(const char *cpu_model)
 
     env->cpu_model_str = cpu_model;
 
-    ppc_cpu_realize(OBJECT(cpu), &err);
+    object_property_set_bool(OBJECT(cpu), true, "realized", &err);
     if (err != NULL) {
         fprintf(stderr, "%s\n", error_get_pretty(err));
         error_free(err);
@@ -10563,6 +10565,10 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
 {
     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
     CPUClass *cc = CPU_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    pcc->parent_realize = dc->realize;
+    dc->realize = ppc_cpu_realizefn;
 
     pcc->parent_reset = cc->reset;
     cc->reset = ppc_cpu_reset;
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 07/28] target-cris: Introduce QOM realizefn for CRISCPU

[Andreas Färber]

Introduce realizefn and set realized = true from cpu_cris_init().

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-cris/cpu-qom.h   |    2 ++
 target-cris/cpu.c       |   15 +++++++++++++++
 target-cris/translate.c |    3 +--
 3 Dateien geändert, 18 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)

diff --git a/target-cris/cpu-qom.h b/target-cris/cpu-qom.h
index 41ab9b2..7ad8398 100644
--- a/target-cris/cpu-qom.h
+++ b/target-cris/cpu-qom.h
@@ -33,6 +33,7 @@
 
 /**
  * CRISCPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * A CRIS CPU model.
@@ -42,6 +43,7 @@ typedef struct CRISCPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } CRISCPUClass;
 
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 3f64a57..34c4f75 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -55,6 +55,17 @@ static void cris_cpu_reset(CPUState *s)
 #endif
 }
 
+static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+    CRISCPU *cpu = CRIS_CPU(dev);
+    CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
+
+    cpu_reset(CPU(cpu));
+    qemu_init_vcpu(&cpu->env);
+
+    ccc->parent_realize(dev, errp);
+}
+
 static void cris_cpu_initfn(Object *obj)
 {
     CRISCPU *cpu = CRIS_CPU(obj);
@@ -65,9 +76,13 @@ static void cris_cpu_initfn(Object *obj)
 
 static void cris_cpu_class_init(ObjectClass *oc, void *data)
 {
+    DeviceClass *dc = DEVICE_CLASS(oc);
     CPUClass *cc = CPU_CLASS(oc);
     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 
+    ccc->parent_realize = dc->realize;
+    dc->realize = cris_cpu_realizefn;
+
     ccc->parent_reset = cc->reset;
     cc->reset = cris_cpu_reset;
 }
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 09e6011..25ff490 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3558,8 +3558,7 @@ CRISCPU *cpu_cris_init(const char *cpu_model)
 
     env->pregs[PR_VR] = vr_by_name(cpu_model);
 
-    cpu_reset(CPU(cpu));
-    qemu_init_vcpu(env);
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 
     if (tcg_initialized) {
         return cpu;
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 08/28] target-lm32: Introduce QOM realizefn for LM32CPU

[Andreas Färber]

Introduce a realizefn and set realized = true in cpu_lm32_init().

Also move cpu_reset() call from initfn to realizefn.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-lm32/cpu-qom.h |    2 ++
 target-lm32/cpu.c     |   18 ++++++++++++++++--
 target-lm32/helper.c  |    4 ++--
 3 Dateien geändert, 20 Zeilen hinzugefügt(+), 4 Zeilen entfernt(-)

diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h
index 400cdbd..d7525b3 100644
--- a/target-lm32/cpu-qom.h
+++ b/target-lm32/cpu-qom.h
@@ -34,6 +34,7 @@
 
 /**
  * LM32CPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * A LatticeMico32 CPU model.
@@ -43,6 +44,7 @@ typedef struct LM32CPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } LM32CPUClass;
 
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index eca2dca..6a84f51 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -42,6 +42,18 @@ static void lm32_cpu_reset(CPUState *s)
     memset(env, 0, offsetof(CPULM32State, breakpoints));
 }
 
+static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+    LM32CPU *cpu = LM32_CPU(dev);
+    LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
+
+    cpu_reset(CPU(cpu));
+
+    qemu_init_vcpu(&cpu->env);
+
+    lcc->parent_realize(dev, errp);
+}
+
 static void lm32_cpu_initfn(Object *obj)
 {
     LM32CPU *cpu = LM32_CPU(obj);
@@ -50,14 +62,16 @@ static void lm32_cpu_initfn(Object *obj)
     cpu_exec_init(env);
 
     env->flags = 0;
-
-    cpu_reset(CPU(cpu));
 }
 
 static void lm32_cpu_class_init(ObjectClass *oc, void *data)
 {
     LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
     CPUClass *cc = CPU_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    lcc->parent_realize = dc->realize;
+    dc->realize = lm32_cpu_realizefn;
 
     lcc->parent_reset = cc->reset;
     cc->reset = lm32_cpu_reset;
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index d76ea3f..a6691ad 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -212,13 +212,13 @@ LM32CPU *cpu_lm32_init(const char *cpu_model)
     env->num_wps = def->num_watchpoints;
     env->cfg = cfg_by_def(def);
 
-    qemu_init_vcpu(env);
-
     if (tcg_enabled() && !tcg_initialized) {
         tcg_initialized = 1;
         lm32_translate_init();
     }
 
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
     return cpu;
 }
 
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 09/28] target-m68k: Introduce QOM realizefn for M68kCPU

[Andreas Färber]

Introduce realizefn and set realized = true in cpu_m68k_init().

Split off GDB registration to a new m68k_cpu_init_gdb() so that it can
be called from the realizefn.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-m68k/cpu-qom.h |    2 ++
 target-m68k/cpu.c     |   17 +++++++++++++++++
 target-m68k/cpu.h     |    1 +
 target-m68k/helper.c  |   14 ++++++++++----
 4 Dateien geändert, 30 Zeilen hinzugefügt(+), 4 Zeilen entfernt(-)

diff --git a/target-m68k/cpu-qom.h b/target-m68k/cpu-qom.h
index 170daa7..20e5684 100644
--- a/target-m68k/cpu-qom.h
+++ b/target-m68k/cpu-qom.h
@@ -33,6 +33,7 @@
 
 /**
  * M68kCPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * A Motorola 68k CPU model.
@@ -42,6 +43,7 @@ typedef struct M68kCPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } M68kCPUClass;
 
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index ce89674..f6720ca 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -119,6 +119,19 @@ static const M68kCPUInfo m68k_cpus[] = {
     { .name = "any",   .instance_init = any_cpu_initfn },
 };
 
+static void m68k_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+    M68kCPU *cpu = M68K_CPU(dev);
+    M68kCPUClass *mcc = M68K_CPU_GET_CLASS(dev);
+
+    m68k_cpu_init_gdb(cpu);
+
+    cpu_reset(CPU(cpu));
+    qemu_init_vcpu(&cpu->env);
+
+    mcc->parent_realize(dev, errp);
+}
+
 static void m68k_cpu_initfn(Object *obj)
 {
     M68kCPU *cpu = M68K_CPU(obj);
@@ -131,6 +144,10 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
 {
     M68kCPUClass *mcc = M68K_CPU_CLASS(c);
     CPUClass *cc = CPU_CLASS(c);
+    DeviceClass *dc = DEVICE_CLASS(c);
+
+    mcc->parent_realize = dc->realize;
+    dc->realize = m68k_cpu_realizefn;
 
     mcc->parent_reset = cc->reset;
     cc->reset = m68k_cpu_reset;
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index adaf56c..94937c4 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -116,6 +116,7 @@ typedef struct CPUM68KState {
 #include "cpu-qom.h"
 
 void m68k_tcg_init(void);
+void m68k_cpu_init_gdb(M68kCPU *cpu);
 CPUM68KState *cpu_m68k_init(const char *cpu_model);
 int cpu_m68k_exec(CPUM68KState *s);
 void do_interrupt(CPUM68KState *env1);
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 097fc78..f2d3059 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -113,15 +113,21 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model)
     env->cpu_model_str = cpu_model;
 
     register_m68k_insns(env);
+
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
+    return env;
+}
+
+void m68k_cpu_init_gdb(M68kCPU *cpu)
+{
+    CPUM68KState *env = &cpu->env;
+
     if (m68k_feature(env, M68K_FEATURE_CF_FPU)) {
         gdb_register_coprocessor(env, fpu_gdb_get_reg, fpu_gdb_set_reg,
                                  11, "cf-fp.xml", 18);
     }
     /* TODO: Add [E]MAC registers.  */
-
-    cpu_reset(ENV_GET_CPU(env));
-    qemu_init_vcpu(env);
-    return env;
 }
 
 void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 10/28] target-microblaze: Introduce QOM realizefn for MicroBlazeCPU

[Andreas Färber]

Introduce realizefn and set realized = true from cpu_mb_init().

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-microblaze/cpu-qom.h   |    2 ++
 target-microblaze/cpu.c       |   15 +++++++++++++++
 target-microblaze/translate.c |    3 +--
 3 Dateien geändert, 18 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)

diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index f75549d..5ea911c 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -33,6 +33,7 @@
 
 /**
  * MicroBlazeCPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * A MicroBlaze CPU model.
@@ -42,6 +43,7 @@ typedef struct MicroBlazeCPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } MicroBlazeCPUClass;
 
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 0f858fd..d4d197d 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -84,6 +84,17 @@ static void mb_cpu_reset(CPUState *s)
 #endif
 }
 
+static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+    MicroBlazeCPU *cpu = MICROBLAZE_CPU(dev);
+    MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
+
+    cpu_reset(CPU(cpu));
+    qemu_init_vcpu(&cpu->env);
+
+    mcc->parent_realize(dev, errp);
+}
+
 static void mb_cpu_initfn(Object *obj)
 {
     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
@@ -96,9 +107,13 @@ static void mb_cpu_initfn(Object *obj)
 
 static void mb_cpu_class_init(ObjectClass *oc, void *data)
 {
+    DeviceClass *dc = DEVICE_CLASS(oc);
     CPUClass *cc = CPU_CLASS(oc);
     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
 
+    mcc->parent_realize = dc->realize;
+    dc->realize = mb_cpu_realizefn;
+
     mcc->parent_reset = cc->reset;
     cc->reset = mb_cpu_reset;
 }
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 58ce712..a84856b 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1970,8 +1970,7 @@ MicroBlazeCPU *cpu_mb_init(const char *cpu_model)
 
     cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
 
-    cpu_reset(CPU(cpu));
-    qemu_init_vcpu(&cpu->env);
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 
     if (tcg_initialized) {
         return cpu;
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 11/28] target-mips: Introduce QOM realizefn for MIPSCPU

[Andreas Färber]

Introduce a realizefn and set realized = true from cpu_mips_init().

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-mips/cpu-qom.h   |    2 ++
 target-mips/cpu.c       |   15 +++++++++++++++
 target-mips/translate.c |    5 +++--
 3 Dateien geändert, 20 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)

diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h
index 2a4b812..55aa692 100644
--- a/target-mips/cpu-qom.h
+++ b/target-mips/cpu-qom.h
@@ -37,6 +37,7 @@
 
 /**
  * MIPSCPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * A MIPS CPU model.
@@ -46,6 +47,7 @@ typedef struct MIPSCPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } MIPSCPUClass;
 
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 10ff46d..18895da 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -42,6 +42,17 @@ static void mips_cpu_reset(CPUState *s)
     cpu_state_reset(env);
 }
 
+static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+    MIPSCPU *cpu = MIPS_CPU(dev);
+    MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
+
+    cpu_reset(CPU(cpu));
+    qemu_init_vcpu(&cpu->env);
+
+    mcc->parent_realize(dev, errp);
+}
+
 static void mips_cpu_initfn(Object *obj)
 {
     MIPSCPU *cpu = MIPS_CPU(obj);
@@ -54,6 +65,10 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
 {
     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
     CPUClass *cc = CPU_CLASS(c);
+    DeviceClass *dc = DEVICE_CLASS(c);
+
+    mcc->parent_realize = dc->realize;
+    dc->realize = mips_cpu_realizefn;
 
     mcc->parent_reset = cc->reset;
     cc->reset = mips_cpu_reset;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 206ba83..9ea9354 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15871,8 +15871,9 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)
     fpu_init(env, def);
     mvp_init(env, def);
     mips_tcg_init();
-    cpu_reset(CPU(cpu));
-    qemu_init_vcpu(env);
+
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
     return cpu;
 }
 
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 12/28] target-s390x: Introduce QOM realizefn for S390CPU

[Andreas Färber]

Introduce realizefn and set realized = true in cpu_s390x_init().

Defer CPU reset from initfn to realizefn.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-s390x/cpu-qom.h |    2 ++
 target-s390x/cpu.c     |   17 +++++++++++++++--
 target-s390x/helper.c  |    4 +++-
 3 Dateien geändert, 20 Zeilen hinzugefügt(+), 3 Zeilen entfernt(-)

diff --git a/target-s390x/cpu-qom.h b/target-s390x/cpu-qom.h
index d54e4a2..237184f 100644
--- a/target-s390x/cpu-qom.h
+++ b/target-s390x/cpu-qom.h
@@ -34,6 +34,7 @@
 
 /**
  * S390CPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * An S/390 CPU model.
@@ -43,6 +44,7 @@ typedef struct S390CPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } S390CPUClass;
 
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 0b68db8..60f71fc 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -97,6 +97,17 @@ static void s390_cpu_machine_reset_cb(void *opaque)
 }
 #endif
 
+static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+    S390CPU *cpu = S390_CPU(dev);
+    S390CPUClass *scc = S390_CPU_GET_CLASS(dev);
+
+    qemu_init_vcpu(&cpu->env);
+    cpu_reset(CPU(cpu));
+
+    scc->parent_realize(dev, errp);
+}
+
 static void s390_cpu_initfn(Object *obj)
 {
     S390CPU *cpu = S390_CPU(obj);
@@ -122,8 +133,6 @@ static void s390_cpu_initfn(Object *obj)
 #endif
     env->cpu_num = cpu_num++;
     env->ext_index = -1;
-
-    cpu_reset(CPU(cpu));
 }
 
 static void s390_cpu_finalize(Object *obj)
@@ -139,6 +148,10 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
 {
     S390CPUClass *scc = S390_CPU_CLASS(oc);
     CPUClass *cc = CPU_CLASS(scc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    scc->parent_realize = dc->realize;
+    dc->realize = s390_cpu_realizefn;
 
     scc->parent_reset = cc->reset;
     cc->reset = s390_cpu_reset;
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 9a132e6..45020b2 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -85,7 +85,9 @@ S390CPU *cpu_s390x_init(const char *cpu_model)
     }
 
     env->cpu_model_str = cpu_model;
-    qemu_init_vcpu(env);
+
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
     return cpu;
 }
 
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 13/28] target-sh4: Introduce QOM realizefn for SuperHCPU

[Andreas Färber]

Introduce a realizefn and set realized = true in cpu_sh4_init().

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-sh4/cpu-qom.h   |    2 ++
 target-sh4/cpu.c       |   15 +++++++++++++++
 target-sh4/translate.c |    5 +++--
 3 Dateien geändert, 20 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)

diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h
index 09573c9..d368db1 100644
--- a/target-sh4/cpu-qom.h
+++ b/target-sh4/cpu-qom.h
@@ -33,6 +33,7 @@
 
 /**
  * SuperHCPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * A SuperH CPU model.
@@ -42,6 +43,7 @@ typedef struct SuperHCPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } SuperHCPUClass;
 
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index e4858a0..839696c 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -53,6 +53,17 @@ static void superh_cpu_reset(CPUState *s)
     set_default_nan_mode(1, &env->fp_status);
 }
 
+static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+    SuperHCPU *cpu = SUPERH_CPU(dev);
+    SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
+
+    cpu_reset(CPU(cpu));
+    qemu_init_vcpu(&cpu->env);
+
+    scc->parent_realize(dev, errp);
+}
+
 static void superh_cpu_initfn(Object *obj)
 {
     SuperHCPU *cpu = SUPERH_CPU(obj);
@@ -65,9 +76,13 @@ static void superh_cpu_initfn(Object *obj)
 
 static void superh_cpu_class_init(ObjectClass *oc, void *data)
 {
+    DeviceClass *dc = DEVICE_CLASS(oc);
     CPUClass *cc = CPU_CLASS(oc);
     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 
+    scc->parent_realize = dc->realize;
+    dc->realize = superh_cpu_realizefn;
+
     scc->parent_reset = cc->reset;
     cc->reset = superh_cpu_reset;
 }
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 260aaab..2409a10 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -253,9 +253,10 @@ SuperHCPU *cpu_sh4_init(const char *cpu_model)
     env->features = def->features;
     sh4_translate_init();
     env->cpu_model_str = cpu_model;
-    cpu_reset(CPU(cpu));
     cpu_register(env, def);
-    qemu_init_vcpu(env);
+
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
     return cpu;
 }
 
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 14/28] target-sparc: Introduce QOM realizefn for SPARCCPU

[Andreas Färber]

Introduce realizefn and set realized = true in cpu_sparc_init().

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-sparc/cpu-qom.h |    2 ++
 target-sparc/cpu.c     |   17 ++++++++++++++++-
 2 Dateien geändert, 18 Zeilen hinzugefügt(+), 1 Zeile entfernt(-)

diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h
index 2a738ae..89cd1cf 100644
--- a/target-sparc/cpu-qom.h
+++ b/target-sparc/cpu-qom.h
@@ -38,6 +38,7 @@
 
 /**
  * SPARCCPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * A SPARC CPU model.
@@ -47,6 +48,7 @@ typedef struct SPARCCPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } SPARCCPUClass;
 
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index f404aa8..a92822d 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -122,7 +122,8 @@ SPARCCPU *cpu_sparc_init(const char *cpu_model)
         object_delete(OBJECT(cpu));
         return NULL;
     }
-    qemu_init_vcpu(env);
+
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 
     return cpu;
 }
@@ -851,6 +852,16 @@ void cpu_dump_state(CPUSPARCState *env, FILE *f, fprintf_function cpu_fprintf,
     cpu_fprintf(f, "\n");
 }
 
+static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+    SPARCCPU *cpu = SPARC_CPU(dev);
+    SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
+
+    qemu_init_vcpu(&cpu->env);
+
+    scc->parent_realize(dev, errp);
+}
+
 static void sparc_cpu_initfn(Object *obj)
 {
     SPARCCPU *cpu = SPARC_CPU(obj);
@@ -871,6 +882,10 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
 {
     SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
     CPUClass *cc = CPU_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    scc->parent_realize = dc->realize;
+    dc->realize = sparc_cpu_realizefn;
 
     scc->parent_reset = cc->reset;
     cc->reset = sparc_cpu_reset;
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 15/28] target-unicore32: Introduce QOM realizefn for UniCore32CPU

[Andreas Färber]

Introduce a realizefn and set realized = true in uc32_cpu_init().

Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
[AF: Invoke the parent's realizefn]
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-unicore32/cpu-qom.h |    3 +++
 target-unicore32/cpu.c     |   20 ++++++++++++++++++++
 target-unicore32/helper.c  |    3 ++-
 3 Dateien geändert, 25 Zeilen hinzugefügt(+), 1 Zeile entfernt(-)

diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h
index fe40b2d..625c614 100644
--- a/target-unicore32/cpu-qom.h
+++ b/target-unicore32/cpu-qom.h
@@ -25,6 +25,7 @@
 
 /**
  * UniCore32CPUClass:
+ * @parent_realize: The parent class' realize handler.
  *
  * A UniCore32 CPU model.
  */
@@ -32,6 +33,8 @@ typedef struct UniCore32CPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
+
+    DeviceRealize parent_realize;
 } UniCore32CPUClass;
 
 /**
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 884c101..bf33326 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -61,6 +61,16 @@ static const UniCore32CPUInfo uc32_cpus[] = {
     { .name = "any",        .instance_init = uc32_any_cpu_initfn },
 };
 
+static void uc32_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+    UniCore32CPU *cpu = UNICORE32_CPU(dev);
+    UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev);
+
+    qemu_init_vcpu(&cpu->env);
+
+    ucc->parent_realize(dev, errp);
+}
+
 static void uc32_cpu_initfn(Object *obj)
 {
     UniCore32CPU *cpu = UNICORE32_CPU(obj);
@@ -80,6 +90,15 @@ static void uc32_cpu_initfn(Object *obj)
     tlb_flush(env, 1);
 }
 
+static void uc32_cpu_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    UniCore32CPUClass *ucc = UNICORE32_CPU_CLASS(oc);
+
+    ucc->parent_realize = dc->realize;
+    dc->realize = uc32_cpu_realizefn;
+}
+
 static void uc32_register_cpu_type(const UniCore32CPUInfo *info)
 {
     TypeInfo type_info = {
@@ -98,6 +117,7 @@ static const TypeInfo uc32_cpu_type_info = {
     .instance_init = uc32_cpu_initfn,
     .abstract = true,
     .class_size = sizeof(UniCore32CPUClass),
+    .class_init = uc32_cpu_class_init,
 };
 
 static void uc32_cpu_register_types(void)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 5359538..173579a 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -42,7 +42,8 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
         uc32_translate_init();
     }
 
-    qemu_init_vcpu(env);
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
     return env;
 }
 
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 16/28] target-xtensa: Introduce QOM realizefn for XtensaCPU

[Andreas Färber]

Introduce realizefn and set realized = true in cpu_xtensa_init().

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-xtensa/cpu-qom.h |    2 ++
 target-xtensa/cpu.c     |   14 ++++++++++++++
 target-xtensa/helper.c  |    4 +++-
 3 Dateien geändert, 19 Zeilen hinzugefügt(+), 1 Zeile entfernt(-)

diff --git a/target-xtensa/cpu-qom.h b/target-xtensa/cpu-qom.h
index e344a9a..270de16 100644
--- a/target-xtensa/cpu-qom.h
+++ b/target-xtensa/cpu-qom.h
@@ -43,6 +43,7 @@
 
 /**
  * XtensaCPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * An Xtensa CPU model.
@@ -52,6 +53,7 @@ typedef struct XtensaCPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } XtensaCPUClass;
 
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index 035b07c..ec99ae9 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -56,6 +56,16 @@ static void xtensa_cpu_reset(CPUState *s)
     reset_mmu(env);
 }
 
+static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+    XtensaCPU *cpu = XTENSA_CPU(dev);
+    XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
+
+    qemu_init_vcpu(&cpu->env);
+
+    xcc->parent_realize(dev, errp);
+}
+
 static void xtensa_cpu_initfn(Object *obj)
 {
     XtensaCPU *cpu = XTENSA_CPU(obj);
@@ -66,9 +76,13 @@ static void xtensa_cpu_initfn(Object *obj)
 
 static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
 {
+    DeviceClass *dc = DEVICE_CLASS(oc);
     CPUClass *cc = CPU_CLASS(oc);
     XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
 
+    xcc->parent_realize = dc->realize;
+    dc->realize = xtensa_cpu_realizefn;
+
     xcc->parent_reset = cc->reset;
     cc->reset = xtensa_cpu_reset;
 }
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index 94c03a1..14bcc7e 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -104,7 +104,9 @@ XtensaCPU *cpu_xtensa_init(const char *cpu_model)
     }
 
     xtensa_irq_init(env);
-    qemu_init_vcpu(env);
+
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
     return cpu;
 }
 
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 17/28] target-arm: Move TCG initialization to ARMCPU initfn

[Andreas Färber]

Ensures that a QOM-created ARMCPU is usable.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-arm/cpu.c    |    6 ++++++
 target-arm/helper.c |    6 ------
 2 Dateien geändert, 6 Zeilen hinzugefügt(+), 6 Zeilen entfernt(-)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 19d5ae4..8615068 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -135,10 +135,16 @@ static inline void set_feature(CPUARMState *env, int feature)
 static void arm_cpu_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
+    static bool inited;
 
     cpu_exec_init(&cpu->env);
     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
                                          g_free, g_free);
+
+    if (tcg_enabled() && !inited) {
+        inited = true;
+        arm_translate_init();
+    }
 }
 
 static void arm_cpu_finalizefn(Object *obj)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f412143..904859b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1262,7 +1262,6 @@ ARMCPU *cpu_arm_init(const char *cpu_model)
 {
     ARMCPU *cpu;
     CPUARMState *env;
-    static int inited = 0;
 
     if (!object_class_by_name(cpu_model)) {
         return NULL;
@@ -1274,11 +1273,6 @@ ARMCPU *cpu_arm_init(const char *cpu_model)
     /* TODO this should be set centrally, once possible */
     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 
-    if (tcg_enabled() && !inited) {
-        inited = 1;
-        arm_translate_init();
-    }
-
     return cpu;
 }
 
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 18/28] target-cris: Move TCG initialization to CRISCPU initfn

[Andreas Färber]

Split out TCG initialization from cpu_cris_init(). Avoid CPUCRISState
dependency for v10-specific initialization and for non-v10 by inlining
the decision into the initfn as well.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-cris/cpu.c           |   10 ++++++++++
 target-cris/cpu.h           |    3 +++
 target-cris/translate.c     |   19 +++++--------------
 target-cris/translate_v10.c |    5 +----
 4 Dateien geändert, 19 Zeilen hinzugefügt(+), 18 Zeilen entfernt(-)

diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 34c4f75..fedf641 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -70,8 +70,18 @@ static void cris_cpu_initfn(Object *obj)
 {
     CRISCPU *cpu = CRIS_CPU(obj);
     CPUCRISState *env = &cpu->env;
+    static bool tcg_initialized;
 
     cpu_exec_init(env);
+
+    if (tcg_enabled() && !tcg_initialized) {
+        tcg_initialized = true;
+        if (env->pregs[PR_VR] < 32) {
+            cris_initialize_crisv10_tcg();
+        } else {
+            cris_initialize_tcg();
+        }
+    }
 }
 
 static void cris_cpu_class_init(ObjectClass *oc, void *data)
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 257cb52..ebf2d40 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -182,6 +182,9 @@ void do_interrupt(CPUCRISState *env);
 int cpu_cris_signal_handler(int host_signum, void *pinfo,
                            void *puc);
 
+void cris_initialize_tcg(void);
+void cris_initialize_crisv10_tcg(void);
+
 enum {
     CC_OP_DYNAMIC, /* Use env->cc_op  */
     CC_OP_FLAGS,
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 25ff490..25a43fa 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3550,8 +3550,6 @@ CRISCPU *cpu_cris_init(const char *cpu_model)
 {
     CRISCPU *cpu;
     CPUCRISState *env;
-    static int tcg_initialized = 0;
-    int i;
 
     cpu = CRIS_CPU(object_new(TYPE_CRIS_CPU));
     env = &cpu->env;
@@ -3560,21 +3558,16 @@ CRISCPU *cpu_cris_init(const char *cpu_model)
 
     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 
-    if (tcg_initialized) {
-        return cpu;
-    }
+    return cpu;
+}
 
-    tcg_initialized = 1;
+void cris_initialize_tcg(void)
+{
+    int i;
 
 #define GEN_HELPER 2
 #include "helper.h"
 
-    if (env->pregs[PR_VR] < 32) {
-        cpu_crisv10_init(env);
-        return cpu;
-    }
-
-
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
     cc_x = tcg_global_mem_new(TCG_AREG0,
                               offsetof(CPUCRISState, cc_x), "cc_x");
@@ -3614,8 +3607,6 @@ CRISCPU *cpu_cris_init(const char *cpu_model)
                                        offsetof(CPUCRISState, pregs[i]),
                                        pregnames[i]);
     }
-
-    return cpu;
 }
 
 void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos)
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index d2cca89..d6ef084 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -1257,7 +1257,7 @@ static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc)
     return insn_len;
 }
 
-static CPUCRISState *cpu_crisv10_init (CPUCRISState *env)
+void cris_initialize_crisv10_tcg(void)
 {
 	int i;
 
@@ -1300,7 +1300,4 @@ static CPUCRISState *cpu_crisv10_init (CPUCRISState *env)
 					       offsetof(CPUCRISState, pregs[i]),
 					       pregnames_v10[i]);
 	}
-
-	return env;
 }
-
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 19/28] target-lm32: Move TCG initialization to LM32CPU initfn

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-lm32/cpu.c    |    6 ++++++
 target-lm32/helper.c |    6 ------
 2 Dateien geändert, 6 Zeilen hinzugefügt(+), 6 Zeilen entfernt(-)

diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index 6a84f51..5f16734 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -58,10 +58,16 @@ static void lm32_cpu_initfn(Object *obj)
 {
     LM32CPU *cpu = LM32_CPU(obj);
     CPULM32State *env = &cpu->env;
+    static bool tcg_initialized;
 
     cpu_exec_init(env);
 
     env->flags = 0;
+
+    if (tcg_enabled() && !tcg_initialized) {
+        tcg_initialized = true;
+        lm32_translate_init();
+    }
 }
 
 static void lm32_cpu_class_init(ObjectClass *oc, void *data)
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index a6691ad..47ae7e7 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -197,7 +197,6 @@ LM32CPU *cpu_lm32_init(const char *cpu_model)
     LM32CPU *cpu;
     CPULM32State *env;
     const LM32Def *def;
-    static int tcg_initialized;
 
     def = cpu_lm32_find_by_name(cpu_model);
     if (!def) {
@@ -212,11 +211,6 @@ LM32CPU *cpu_lm32_init(const char *cpu_model)
     env->num_wps = def->num_watchpoints;
     env->cfg = cfg_by_def(def);
 
-    if (tcg_enabled() && !tcg_initialized) {
-        tcg_initialized = 1;
-        lm32_translate_init();
-    }
-
     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 
     return cpu;
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 20/28] target-m68k: Move TCG initialization to M68kCPU initfn

[Andreas Färber]

Add a tcg_enabled() check to suppress it for qtest.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-m68k/cpu.c    |    6 ++++++
 target-m68k/helper.c |    7 -------
 2 Dateien geändert, 6 Zeilen hinzugefügt(+), 7 Zeilen entfernt(-)

diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index f6720ca..bbeae28 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -136,8 +136,14 @@ static void m68k_cpu_initfn(Object *obj)
 {
     M68kCPU *cpu = M68K_CPU(obj);
     CPUM68KState *env = &cpu->env;
+    static bool inited;
 
     cpu_exec_init(env);
+
+    if (tcg_enabled() && !inited) {
+        inited = true;
+        m68k_tcg_init();
+    }
 }
 
 static void m68k_cpu_class_init(ObjectClass *c, void *data)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index f2d3059..920dfa9 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -97,19 +97,12 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model)
 {
     M68kCPU *cpu;
     CPUM68KState *env;
-    static int inited;
 
     if (object_class_by_name(cpu_model) == NULL) {
         return NULL;
     }
     cpu = M68K_CPU(object_new(cpu_model));
     env = &cpu->env;
-
-    if (!inited) {
-        inited = 1;
-        m68k_tcg_init();
-    }
-
     env->cpu_model_str = cpu_model;
 
     register_m68k_insns(env);
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 21/28] target-microblaze: Move TCG initialization to MicroBlazeCPU initfn

[Andreas Färber]

Split off TCG initialization from cpu_mb_init() into mb_tcg_init() to
call it from the initfn.

Ensures that a QOM-created MicroBlazeCPU is usable.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-microblaze/cpu.c       |    6 ++++++
 target-microblaze/cpu.h       |    1 +
 target-microblaze/translate.c |   13 +++++--------
 3 Dateien geändert, 12 Zeilen hinzugefügt(+), 8 Zeilen entfernt(-)

diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index d4d197d..473bd70 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -99,10 +99,16 @@ static void mb_cpu_initfn(Object *obj)
 {
     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
     CPUMBState *env = &cpu->env;
+    static bool tcg_initialized;
 
     cpu_exec_init(env);
 
     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
+
+    if (tcg_enabled() && !tcg_initialized) {
+        tcg_initialized = true;
+        mb_tcg_init();
+    }
 }
 
 static void mb_cpu_class_init(ObjectClass *oc, void *data)
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 5621068..c66193f 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -272,6 +272,7 @@ struct CPUMBState {
 
 #include "cpu-qom.h"
 
+void mb_tcg_init(void);
 MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
 int cpu_mb_exec(CPUMBState *s);
 void do_interrupt(CPUMBState *env);
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index a84856b..12ea820 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1965,18 +1965,17 @@ void cpu_dump_state (CPUMBState *env, FILE *f, fprintf_function cpu_fprintf,
 MicroBlazeCPU *cpu_mb_init(const char *cpu_model)
 {
     MicroBlazeCPU *cpu;
-    static int tcg_initialized = 0;
-    int i;
 
     cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
 
     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 
-    if (tcg_initialized) {
-        return cpu;
-    }
+    return cpu;
+}
 
-    tcg_initialized = 1;
+void mb_tcg_init(void)
+{
+    int i;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
 
@@ -2007,8 +2006,6 @@ MicroBlazeCPU *cpu_mb_init(const char *cpu_model)
     }
 #define GEN_HELPER 2
 #include "helper.h"
-
-    return cpu;
 }
 
 void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos)
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 22/28] target-mips: Move TCG initialization to MIPSCPU initfn

[Andreas Färber]

Make mips_tcg_init() non-static and add tcg_enabled() check to suppress
it for qtest.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-mips/cpu.c       |    4 ++++
 target-mips/cpu.h       |    1 +
 target-mips/translate.c |    3 +--
 3 Dateien geändert, 6 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)

diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 18895da..09d6172 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -59,6 +59,10 @@ static void mips_cpu_initfn(Object *obj)
     CPUMIPSState *env = &cpu->env;
 
     cpu_exec_init(env);
+
+    if (tcg_enabled()) {
+        mips_tcg_init();
+    }
 }
 
 static void mips_cpu_class_init(ObjectClass *c, void *data)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 5963d62..0e198b1 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -629,6 +629,7 @@ enum {
 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 
 int cpu_mips_exec(CPUMIPSState *s);
+void mips_tcg_init(void);
 MIPSCPU *cpu_mips_init(const char *cpu_model);
 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 9ea9354..373cfa7 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15791,7 +15791,7 @@ void cpu_dump_state (CPUMIPSState *env, FILE *f, fprintf_function cpu_fprintf,
 #endif
 }
 
-static void mips_tcg_init(void)
+void mips_tcg_init(void)
 {
     int i;
     static int inited;
@@ -15870,7 +15870,6 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)
 #endif
     fpu_init(env, def);
     mvp_init(env, def);
-    mips_tcg_init();
 
     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 23/28] target-ppc: Move TCG initialization to PowerPCCPU initfn

[Andreas Färber]

Ensures that a QOM-created PowerPCCPU is usable.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-ppc/translate_init.c |    9 ++++-----
 1 Datei geändert, 4 Zeilen hinzugefügt(+), 5 Zeilen entfernt(-)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 63ba4a5..786d871 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -10337,11 +10337,6 @@ PowerPCCPU *cpu_ppc_init(const char *cpu_model)
 
     cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
     env = &cpu->env;
-
-    if (tcg_enabled()) {
-        ppc_translate_init();
-    }
-
     env->cpu_model_str = cpu_model;
 
     object_property_set_bool(OBJECT(cpu), true, "realized", &err);
@@ -10559,6 +10554,10 @@ static void ppc_cpu_initfn(Object *obj)
         env->sps = defsps;
     }
 #endif /* defined(TARGET_PPC64) */
+
+    if (tcg_enabled()) {
+        ppc_translate_init();
+    }
 }
 
 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 24/28] target-s390x: Move TCG initialization to S390CPU initfn

[Andreas Färber]

Ensures that a QOM-created S390CPU is usable.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-s390x/cpu.c    |    6 ++++++
 target-s390x/helper.c |    7 -------
 2 Dateien geändert, 6 Zeilen hinzugefügt(+), 7 Zeilen entfernt(-)

diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 60f71fc..109777e 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -112,6 +112,7 @@ static void s390_cpu_initfn(Object *obj)
 {
     S390CPU *cpu = S390_CPU(obj);
     CPUS390XState *env = &cpu->env;
+    static bool inited;
     static int cpu_num = 0;
 #if !defined(CONFIG_USER_ONLY)
     struct tm tm;
@@ -133,6 +134,11 @@ static void s390_cpu_initfn(Object *obj)
 #endif
     env->cpu_num = cpu_num++;
     env->ext_index = -1;
+
+    if (tcg_enabled() && !inited) {
+        inited = true;
+        s390x_translate_init();
+    }
 }
 
 static void s390_cpu_finalize(Object *obj)
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 45020b2..bad0683 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -74,16 +74,9 @@ S390CPU *cpu_s390x_init(const char *cpu_model)
 {
     S390CPU *cpu;
     CPUS390XState *env;
-    static int inited;
 
     cpu = S390_CPU(object_new(TYPE_S390_CPU));
     env = &cpu->env;
-
-    if (tcg_enabled() && !inited) {
-        inited = 1;
-        s390x_translate_init();
-    }
-
     env->cpu_model_str = cpu_model;
 
     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 25/28] target-sh4: Move TCG initialization to SuperHCPU initfn

[Andreas Färber]

Add a tcg_enabled() check to suppress it for qtest.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-sh4/cpu.c       |    4 ++++
 target-sh4/cpu.h       |    1 +
 target-sh4/translate.c |    3 +--
 3 Dateien geändert, 6 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)

diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 839696c..223008a 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -72,6 +72,10 @@ static void superh_cpu_initfn(Object *obj)
     cpu_exec_init(env);
 
     env->movcal_backup_tail = &(env->movcal_backup);
+
+    if (tcg_enabled()) {
+        sh4_translate_init();
+    }
 }
 
 static void superh_cpu_class_init(ObjectClass *oc, void *data)
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 34e9b0a..49dcd9e 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -191,6 +191,7 @@ typedef struct CPUSH4State {
 
 #include "cpu-qom.h"
 
+void sh4_translate_init(void);
 SuperHCPU *cpu_sh4_init(const char *cpu_model);
 int cpu_sh4_exec(CPUSH4State * s);
 int cpu_sh4_signal_handler(int host_signum, void *pinfo,
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 2409a10..c58d79a 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -71,7 +71,7 @@ static uint32_t gen_opc_hflags[OPC_BUF_SIZE];
 
 #include "exec/gen-icount.h"
 
-static void sh4_translate_init(void)
+void sh4_translate_init(void)
 {
     int i;
     static int done_init = 0;
@@ -251,7 +251,6 @@ SuperHCPU *cpu_sh4_init(const char *cpu_model)
     cpu = SUPERH_CPU(object_new(TYPE_SUPERH_CPU));
     env = &cpu->env;
     env->features = def->features;
-    sh4_translate_init();
     env->cpu_model_str = cpu_model;
     cpu_register(env, def);
 
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 26/28] target-sparc: Move TCG initialization to SPARCCPU initfn

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-sparc/cpu.c |    8 ++++----
 1 Datei geändert, 4 Zeilen hinzugefügt(+), 4 Zeilen entfernt(-)

diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index a92822d..10dc709 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -114,10 +114,6 @@ SPARCCPU *cpu_sparc_init(const char *cpu_model)
     cpu = SPARC_CPU(object_new(TYPE_SPARC_CPU));
     env = &cpu->env;
 
-    if (tcg_enabled()) {
-        gen_intermediate_code_init(env);
-    }
-
     if (cpu_sparc_register(env, cpu_model) < 0) {
         object_delete(OBJECT(cpu));
         return NULL;
@@ -868,6 +864,10 @@ static void sparc_cpu_initfn(Object *obj)
     CPUSPARCState *env = &cpu->env;
 
     cpu_exec_init(env);
+
+    if (tcg_enabled()) {
+        gen_intermediate_code_init(env);
+    }
 }
 
 static void sparc_cpu_uninitfn(Object *obj)
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 27/28] target-unicore32: Move TCG initialization to UniCore32CPU initfn

[Andreas Färber]

Normalize the "inited" logic and add a tcg_enabled() check to suppress
it for qtest.

Ensures that a QOM-created UniCore32CPU is usable.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-unicore32/cpu.c    |    6 ++++++
 target-unicore32/helper.c |    6 ------
 2 Dateien geändert, 6 Zeilen hinzugefügt(+), 6 Zeilen entfernt(-)

diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index bf33326..7f8dc15 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -75,6 +75,7 @@ static void uc32_cpu_initfn(Object *obj)
 {
     UniCore32CPU *cpu = UNICORE32_CPU(obj);
     CPUUniCore32State *env = &cpu->env;
+    static bool inited;
 
     cpu_exec_init(env);
     env->cpu_model_str = object_get_typename(obj);
@@ -88,6 +89,11 @@ static void uc32_cpu_initfn(Object *obj)
 #endif
 
     tlb_flush(env, 1);
+
+    if (tcg_enabled() && !inited) {
+        inited = true;
+        uc32_translate_init();
+    }
 }
 
 static void uc32_cpu_class_init(ObjectClass *oc, void *data)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 173579a..357cc8b 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -29,7 +29,6 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
 {
     UniCore32CPU *cpu;
     CPUUniCore32State *env;
-    static int inited = 1;
 
     if (object_class_by_name(cpu_model) == NULL) {
         return NULL;
@@ -37,11 +36,6 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
     cpu = UNICORE32_CPU(object_new(cpu_model));
     env = &cpu->env;
 
-    if (inited) {
-        inited = 0;
-        uc32_translate_init();
-    }
-
     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 
     return env;
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu v2 28/28] target-xtensa: Move TCG initialization to XtensaCPU initfn

[Andreas Färber]

Combine this with breakpoint handler registration, guarding both with
tcg_enabled() to suppress also TCG init for qtest. Rename the handler to
xtensa_breakpoint_handler() since it needs to become global.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-xtensa/cpu.c    |    7 +++++++
 target-xtensa/cpu.h    |    1 +
 target-xtensa/helper.c |   14 +-------------
 3 Dateien geändert, 9 Zeilen hinzugefügt(+), 13 Zeilen entfernt(-)

diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index ec99ae9..6dccefb 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -70,8 +70,15 @@ static void xtensa_cpu_initfn(Object *obj)
 {
     XtensaCPU *cpu = XTENSA_CPU(obj);
     CPUXtensaState *env = &cpu->env;
+    static bool tcg_inited;
 
     cpu_exec_init(env);
+
+    if (tcg_enabled() && !tcg_inited) {
+        tcg_inited = true;
+        xtensa_translate_init();
+        cpu_set_debug_excp_handler(xtensa_breakpoint_handler);
+    }
 }
 
 static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 5acf78c..dece224 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -385,6 +385,7 @@ static inline CPUXtensaState *cpu_init(const char *cpu_model)
 }
 
 void xtensa_translate_init(void);
+void xtensa_breakpoint_handler(CPUXtensaState *env);
 int cpu_xtensa_exec(CPUXtensaState *s);
 void xtensa_register_core(XtensaConfigList *node);
 void do_interrupt(CPUXtensaState *s);
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index 14bcc7e..a8a6493 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -54,7 +54,7 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *env)
     return 0;
 }
 
-static void breakpoint_handler(CPUXtensaState *env)
+void xtensa_breakpoint_handler(CPUXtensaState *env)
 {
     if (env->watchpoint_hit) {
         if (env->watchpoint_hit->flags & BP_CPU) {
@@ -72,8 +72,6 @@ static void breakpoint_handler(CPUXtensaState *env)
 
 XtensaCPU *cpu_xtensa_init(const char *cpu_model)
 {
-    static int tcg_inited;
-    static int debug_handler_inited;
     XtensaCPU *cpu;
     CPUXtensaState *env;
     const XtensaConfig *config = NULL;
@@ -93,16 +91,6 @@ XtensaCPU *cpu_xtensa_init(const char *cpu_model)
     env = &cpu->env;
     env->config = config;
 
-    if (!tcg_inited) {
-        tcg_inited = 1;
-        xtensa_translate_init();
-    }
-
-    if (!debug_handler_inited && tcg_enabled()) {
-        debug_handler_inited = 1;
-        cpu_set_debug_excp_handler(breakpoint_handler);
-    }
-
     xtensa_irq_init(env);
 
     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
-- 
1.7.10.4