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From: "Andreas Färber" <afaerber@suse.de>
To: qemu-devel@nongnu.org
Cc: "Igor Mammedov" <imammedo@redhat.com>,
	"Andreas Färber" <afaerber@suse.de>,
	"Eduardo Habkost" <ehabkost@redhat.com>
Subject: [Qemu-devel] [RFC qom-cpu v2 04/28] target-i386: Update X86CPU to QOM realizefn
Date: Sun, 20 Jan 2013 08:22:27 +0100	[thread overview]
Message-ID: <1358666571-1737-5-git-send-email-afaerber@suse.de> (raw)
In-Reply-To: <1358666571-1737-1-git-send-email-afaerber@suse.de>

Adapt the signature of x86_cpu_realize(), hook up to
DeviceClass::realize and set realized = true in cpu_x86_init().

The QOM realizefn cannot depend on errp being non-NULL as in
cpu_x86_init(), so use a local Error to preserve error handling behavior
on APIC initialization errors.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Eduardo Habkost <ehabkost@redhat.com>
---
 target-i386/cpu-qom.h |    5 ++---
 target-i386/cpu.c     |   19 +++++++++++++++----
 target-i386/helper.c  |    2 +-
 3 Dateien geändert, 18 Zeilen hinzugefügt(+), 8 Zeilen entfernt(-)

diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
index 332916a..48e6b54 100644
--- a/target-i386/cpu-qom.h
+++ b/target-i386/cpu-qom.h
@@ -39,6 +39,7 @@
 
 /**
  * X86CPUClass:
+ * @parent_realize: The parent class' realize handler.
  * @parent_reset: The parent class' reset handler.
  *
  * An x86 CPU model or family.
@@ -48,6 +49,7 @@ typedef struct X86CPUClass {
     CPUClass parent_class;
     /*< public >*/
 
+    DeviceRealize parent_realize;
     void (*parent_reset)(CPUState *cpu);
 } X86CPUClass;
 
@@ -72,8 +74,5 @@ static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
 
 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
 
-/* TODO Drop once ObjectClass::realize is available */
-void x86_cpu_realize(Object *obj, Error **errp);
-
 
 #endif
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 333745b..c988ac5 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2140,10 +2140,14 @@ static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
 }
 #endif
 
-void x86_cpu_realize(Object *obj, Error **errp)
+static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
 {
-    X86CPU *cpu = X86_CPU(obj);
+    X86CPU *cpu = X86_CPU(dev);
+    X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
     CPUX86State *env = &cpu->env;
+#ifndef CONFIG_USER_ONLY
+    Error *local_err = NULL;
+#endif
 
     if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
         env->cpuid_level = 7;
@@ -2185,8 +2189,9 @@ void x86_cpu_realize(Object *obj, Error **errp)
     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
 
     if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
-        x86_cpu_apic_init(cpu, errp);
-        if (error_is_set(errp)) {
+        x86_cpu_apic_init(cpu, &local_err);
+        if (local_err != NULL) {
+            error_propagate(errp, local_err);
             return;
         }
     }
@@ -2195,6 +2200,8 @@ void x86_cpu_realize(Object *obj, Error **errp)
     mce_init(cpu);
     qemu_init_vcpu(&cpu->env);
     cpu_reset(CPU(cpu));
+
+    xcc->parent_realize(dev, errp);
 }
 
 static void x86_cpu_initfn(Object *obj)
@@ -2247,6 +2254,10 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
 {
     X86CPUClass *xcc = X86_CPU_CLASS(oc);
     CPUClass *cc = CPU_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    xcc->parent_realize = dc->realize;
+    dc->realize = x86_cpu_realizefn;
 
     xcc->parent_reset = cc->reset;
     cc->reset = x86_cpu_reset;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 547c25e..bf43d6a 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1280,7 +1280,7 @@ X86CPU *cpu_x86_init(const char *cpu_model)
         return NULL;
     }
 
-    x86_cpu_realize(OBJECT(cpu), &error);
+    object_property_set_bool(OBJECT(cpu), true, "realized", &error);
     if (error) {
         error_free(error);
         object_delete(OBJECT(cpu));
-- 
1.7.10.4

  parent reply	other threads:[~2013-01-20  7:23 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-01-20  7:22 [Qemu-devel] [RFC qom-cpu v2 00/28] CPUState QOM realizefn support Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 01/28] cpu: Prepare QOM realizefn Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 02/28] target-alpha: Update AlphaCPU to " Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 03/28] target-arm: Update ARMCPU " Andreas Färber
2013-01-20  7:22 ` Andreas Färber [this message]
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 05/28] target-openrisc: Update OpenRISCCPU " Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 06/28] target-ppc: Update PowerPCCPU " Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 07/28] target-cris: Introduce QOM realizefn for CRISCPU Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 08/28] target-lm32: Introduce QOM realizefn for LM32CPU Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 09/28] target-m68k: Introduce QOM realizefn for M68kCPU Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 10/28] target-microblaze: Introduce QOM realizefn for MicroBlazeCPU Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 11/28] target-mips: Introduce QOM realizefn for MIPSCPU Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 12/28] target-s390x: Introduce QOM realizefn for S390CPU Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 13/28] target-sh4: Introduce QOM realizefn for SuperHCPU Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 14/28] target-sparc: Introduce QOM realizefn for SPARCCPU Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 15/28] target-unicore32: Introduce QOM realizefn for UniCore32CPU Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 16/28] target-xtensa: Introduce QOM realizefn for XtensaCPU Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 17/28] target-arm: Move TCG initialization to ARMCPU initfn Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 18/28] target-cris: Move TCG initialization to CRISCPU initfn Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 19/28] target-lm32: Move TCG initialization to LM32CPU initfn Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 20/28] target-m68k: Move TCG initialization to M68kCPU initfn Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 21/28] target-microblaze: Move TCG initialization to MicroBlazeCPU initfn Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 22/28] target-mips: Move TCG initialization to MIPSCPU initfn Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 23/28] target-ppc: Move TCG initialization to PowerPCCPU initfn Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 24/28] target-s390x: Move TCG initialization to S390CPU initfn Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 25/28] target-sh4: Move TCG initialization to SuperHCPU initfn Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 26/28] target-sparc: Move TCG initialization to SPARCCPU initfn Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 27/28] target-unicore32: Move TCG initialization to UniCore32CPU initfn Andreas Färber
2013-01-20  7:22 ` [Qemu-devel] [RFC qom-cpu v2 28/28] target-xtensa: Move TCG initialization to XtensaCPU initfn Andreas Färber

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