From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35376) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tx83t-0005LM-7v for qemu-devel@nongnu.org; Sun, 20 Jan 2013 22:28:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Tx83p-0001HD-Jy for qemu-devel@nongnu.org; Sun, 20 Jan 2013 22:28:41 -0500 Received: from cantor2.suse.de ([195.135.220.15]:46159 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tx83p-0001G5-6t for qemu-devel@nongnu.org; Sun, 20 Jan 2013 22:28:37 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 21 Jan 2013 04:28:25 +0100 Message-Id: <1358738906-13224-2-git-send-email-afaerber@suse.de> In-Reply-To: <1358738906-13224-1-git-send-email-afaerber@suse.de> References: <1358738906-13224-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [RFC qom-cpu v2 1/2] target-sh4: Introduce SuperHCPU subclasses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno Store legacy name in SuperHCPUClass for -cpu ? and for case-insensitive class lookup. List CPUs by iterating over TYPE_SUPERH_CPU subclasses. Signed-off-by: Andreas F=C3=A4rber --- target-sh4/cpu-qom.h | 7 +++ target-sh4/cpu.c | 124 ++++++++++++++++++++++++++++++++++++++++++= +++++- target-sh4/translate.c | 94 +++++++++++++----------------------- 3 Dateien ge=C3=A4ndert, 162 Zeilen hinzugef=C3=BCgt(+), 63 Zeilen entfe= rnt(-) diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h index d368db1..8326ceb 100644 --- a/target-sh4/cpu-qom.h +++ b/target-sh4/cpu-qom.h @@ -24,6 +24,10 @@ =20 #define TYPE_SUPERH_CPU "superh-cpu" =20 +#define TYPE_SH7750R_CPU "sh7750r-" TYPE_SUPERH_CPU +#define TYPE_SH7751R_CPU "sh7751r-" TYPE_SUPERH_CPU +#define TYPE_SH7785_CPU "sh7785-" TYPE_SUPERH_CPU + #define SUPERH_CPU_CLASS(klass) \ OBJECT_CLASS_CHECK(SuperHCPUClass, (klass), TYPE_SUPERH_CPU) #define SUPERH_CPU(obj) \ @@ -35,6 +39,7 @@ * SuperHCPUClass: * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. + * @name: The name. * * A SuperH CPU model. */ @@ -45,6 +50,8 @@ typedef struct SuperHCPUClass { =20 DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); + + const char *name; } SuperHCPUClass; =20 /** diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 223008a..80804ef 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -53,6 +53,125 @@ static void superh_cpu_reset(CPUState *s) set_default_nan_mode(1, &env->fp_status); } =20 +typedef struct SuperHCPUListState { + fprintf_function cpu_fprintf; + FILE *file; +} SuperHCPUListState; + +/* Sort alphabetically by type name. */ +static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b) +{ + ObjectClass *class_a =3D (ObjectClass *)a; + ObjectClass *class_b =3D (ObjectClass *)b; + const char *name_a, *name_b; + + name_a =3D object_class_get_name(class_a); + name_b =3D object_class_get_name(class_b); + return strcmp(name_a, name_b); +} + +static void superh_cpu_list_entry(gpointer data, gpointer user_data) +{ + ObjectClass *oc =3D data; + SuperHCPUClass *scc =3D SUPERH_CPU_CLASS(oc); + SuperHCPUListState *s =3D user_data; + + (*s->cpu_fprintf)(s->file, "%s\n", + scc->name); +} + +void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf) +{ + SuperHCPUListState s =3D { + .cpu_fprintf =3D cpu_fprintf, + .file =3D f, + }; + GSList *list; + + list =3D object_class_get_list(TYPE_SUPERH_CPU, false); + list =3D g_slist_sort(list, superh_cpu_list_compare); + g_slist_foreach(list, superh_cpu_list_entry, &s); + g_slist_free(list); +} + +static void sh7750r_cpu_initfn(Object *obj) +{ + SuperHCPU *cpu =3D SUPERH_CPU(obj); + CPUSH4State *env =3D &cpu->env; + + env->id =3D SH_CPU_SH7750R; + env->pvr =3D 0x00050000; + env->prr =3D 0x00000100; + env->cvr =3D 0x00110000; + env->features =3D SH_FEATURE_BCR3_AND_BCR4; +} + +static void sh7750r_class_init(ObjectClass *oc, void *data) +{ + SuperHCPUClass *scc =3D SUPERH_CPU_CLASS(oc); + + scc->name =3D "SH7750R"; +} + +static const TypeInfo sh7750r_type_info =3D { + .name =3D TYPE_SH7750R_CPU, + .parent =3D TYPE_SUPERH_CPU, + .class_init =3D sh7750r_class_init, + .instance_init =3D sh7750r_cpu_initfn, +}; + +static void sh7751r_cpu_initfn(Object *obj) +{ + SuperHCPU *cpu =3D SUPERH_CPU(obj); + CPUSH4State *env =3D &cpu->env; + + env->id =3D SH_CPU_SH7751R; + env->pvr =3D 0x04050005; + env->prr =3D 0x00000113; + env->cvr =3D 0x00110000; /* Neutered caches, should be 0x20480000 */ + env->features =3D SH_FEATURE_BCR3_AND_BCR4; +} + +static void sh7751r_class_init(ObjectClass *oc, void *data) +{ + SuperHCPUClass *scc =3D SUPERH_CPU_CLASS(oc); + + scc->name =3D "SH7751R"; +} + +static const TypeInfo sh7751r_type_info =3D { + .name =3D TYPE_SH7751R_CPU, + .parent =3D TYPE_SUPERH_CPU, + .class_init =3D sh7751r_class_init, + .instance_init =3D sh7751r_cpu_initfn, +}; + +static void sh7785_cpu_initfn(Object *obj) +{ + SuperHCPU *cpu =3D SUPERH_CPU(obj); + CPUSH4State *env =3D &cpu->env; + + env->id =3D SH_CPU_SH7785; + env->pvr =3D 0x10300700; + env->prr =3D 0x00000200; + env->cvr =3D 0x71440211; + env->features =3D SH_FEATURE_SH4A; +} + +static void sh7785_class_init(ObjectClass *oc, void *data) +{ + SuperHCPUClass *scc =3D SUPERH_CPU_CLASS(oc); + + scc->name =3D "SH7785"; +} + +static const TypeInfo sh7785_type_info =3D { + .name =3D TYPE_SH7785_CPU, + .parent =3D TYPE_SUPERH_CPU, + .class_init =3D sh7785_class_init, + .instance_init =3D sh7785_cpu_initfn, +}; + static void superh_cpu_realizefn(DeviceState *dev, Error **errp) { SuperHCPU *cpu =3D SUPERH_CPU(dev); @@ -96,7 +215,7 @@ static const TypeInfo superh_cpu_type_info =3D { .parent =3D TYPE_CPU, .instance_size =3D sizeof(SuperHCPU), .instance_init =3D superh_cpu_initfn, - .abstract =3D false, + .abstract =3D true, .class_size =3D sizeof(SuperHCPUClass), .class_init =3D superh_cpu_class_init, }; @@ -104,6 +223,9 @@ static const TypeInfo superh_cpu_type_info =3D { static void superh_cpu_register_types(void) { type_register_static(&superh_cpu_type_info); + type_register_static(&sh7750r_type_info); + type_register_static(&sh7751r_type_info); + type_register_static(&sh7785_type_info); } =20 type_init(superh_cpu_register_types) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index c58d79a..2bdf3b2 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -175,84 +175,54 @@ void cpu_dump_state(CPUSH4State * env, FILE * f, } } =20 -typedef struct { - const char *name; - int id; - uint32_t pvr; - uint32_t prr; - uint32_t cvr; - uint32_t features; -} sh4_def_t; - -static sh4_def_t sh4_defs[] =3D { - { - .name =3D "SH7750R", - .id =3D SH_CPU_SH7750R, - .pvr =3D 0x00050000, - .prr =3D 0x00000100, - .cvr =3D 0x00110000, - .features =3D SH_FEATURE_BCR3_AND_BCR4, - }, { - .name =3D "SH7751R", - .id =3D SH_CPU_SH7751R, - .pvr =3D 0x04050005, - .prr =3D 0x00000113, - .cvr =3D 0x00110000, /* Neutered caches, should be 0x20480000 */ - .features =3D SH_FEATURE_BCR3_AND_BCR4, - }, { - .name =3D "SH7785", - .id =3D SH_CPU_SH7785, - .pvr =3D 0x10300700, - .prr =3D 0x00000200, - .cvr =3D 0x71440211, - .features =3D SH_FEATURE_SH4A, - }, -}; - -static const sh4_def_t *cpu_sh4_find_by_name(const char *name) +static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b) { - int i; + const SuperHCPUClass *scc =3D SUPERH_CPU_CLASS(a); + const char *name =3D b; =20 - if (strcasecmp(name, "any") =3D=3D 0) - return &sh4_defs[0]; - - for (i =3D 0; i < ARRAY_SIZE(sh4_defs); i++) - if (strcasecmp(name, sh4_defs[i].name) =3D=3D 0) - return &sh4_defs[i]; - - return NULL; + return strcasecmp(scc->name, name); } =20 -void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf) +static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) { - int i; + ObjectClass *oc; + GSList *list, *item; =20 - for (i =3D 0; i < ARRAY_SIZE(sh4_defs); i++) - (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name); -} + if (cpu_model =3D=3D NULL) { + return NULL; + } + if (strcasecmp(cpu_model, "any") =3D=3D 0) { + return object_class_by_name(TYPE_SH7750R_CPU); + } =20 -static void cpu_register(CPUSH4State *env, const sh4_def_t *def) -{ - env->pvr =3D def->pvr; - env->prr =3D def->prr; - env->cvr =3D def->cvr; - env->id =3D def->id; + oc =3D object_class_by_name(cpu_model); + if (oc !=3D NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != =3D NULL) { + return oc; + } + + oc =3D NULL; + list =3D object_class_get_list(TYPE_SUPERH_CPU, false); + item =3D g_slist_find_custom(list, cpu_model, superh_cpu_name_compar= e); + if (item !=3D NULL) { + oc =3D item->data; + } + g_slist_free(list); + return oc; } =20 SuperHCPU *cpu_sh4_init(const char *cpu_model) { SuperHCPU *cpu; CPUSH4State *env; - const sh4_def_t *def; + ObjectClass *oc; =20 - def =3D cpu_sh4_find_by_name(cpu_model); - if (!def) - return NULL; - cpu =3D SUPERH_CPU(object_new(TYPE_SUPERH_CPU)); + oc =3D superh_cpu_class_by_name(cpu_model); + if (oc =3D=3D NULL) { + return NULL; + } + cpu =3D SUPERH_CPU(object_new(object_class_get_name(oc))); env =3D &cpu->env; - env->features =3D def->features; env->cpu_model_str =3D cpu_model; - cpu_register(env, def); =20 object_property_set_bool(OBJECT(cpu), true, "realized", NULL); =20 --=20 1.7.10.4