[Qemu-devel] [PATCH RFC qom-cpu-next 0/6] QOM CPUState VMStateDescriptions

[Qemu-devel] [PATCH RFC qom-cpu-next 0/6] QOM CPUState VMStateDescriptions

[Andreas Färber]

Hello,

In response to patches from Juan [1], this series implements a declarative way
for CPUs to register their CPU-specific VMStateDescription.

There are subtle differences between CPU and devices in how they register
their savevm handlers and VMStateDescription respectively:

* CPUs register one VMStateDescription "cpu_common" plus savevm handlers for
  the target-specifics (machine.c:cpu_{save,load}).
  Devices register one VMStateDescription with a subsection for common state
  where necessary.

* CPUs use their cpu_index field as instance_id.
  Devices pass -1 as instance_id, resulting in highest index on the bus plus 1.
  Note: The current cpu_index numbering is not hot-unplug-safe.

My code assumes that registering "cpu_common" for CPUArchState (until changed
in CPUState part 9 series) while registering "cpu" for CPUState is compatible,
since by not using DeviceState::vmsd infrastructure registration order remains
guaranteed the same.

Patches 4-5 demonstrate how two VMStateDescription-prepared but not yet
migratable targets would look like if we want to adopt a consistent pattern
for VMStateDescription registration and layout throughout targets.

Question is whether we want to take that legacy burden on us or whether to
simply expose exec.c:vmstate_cpu_common and embed it PCI-like into the
prepared VMStateDescriptions for alpha and openrisc and register them through
DeviceClass::vmsd instead.

An alternative might be registering "cpu_common" as before but with
instance_id -1 and registering "cpu" through DeviceClass::vmsd, since
exec.c:calculate_new_instance_id() takes the name string into account.
But that would be inconsistent with how devices behave VMState-wise.

Targets that have not yet been converted to VMState [1, 2] are left untouched.

Known conflicts:
- CPUState part 9 v1 series (target-*/cpu.c:class_init), to be rebased on this.

Available for testing here:
git://github.com/afaerber/qemu-cpu.git qom-cpu-vmstate.v1
https://github.com/afaerber/qemu-cpu/commits/qom-cpu-vmstate.v1

What triggered this series was moving the halted and interrupt_request fields
from CPU_COMMON to CPUState:
https://lists.nongnu.org/archive/html/qemu-devel/2013-02/msg00203.html
Since both are in vmstate_cpu_common, they needed to be moved together, and
"cpu_common" will need to operate on CPUState then. At the same time x86
can no longer access the halted field from CPUX86State via VMSTATE_ macros,
so either we need to drop uses of such fields (i.e., version 5) or make it
possible to access CPUState fields in x86 VMState through parent_obj field.
Further, in explaining intended uses of S390CPU vs. CPUS390XState I was
reminded that VMState is currently a limiting factor for placing fields into
CPUState-derived types rather than into CPU*State.

Regards,
Andreas

[1] https://lists.nongnu.org/archive/html/qemu-devel/2012-05/msg00524.html
[2] https://lists.nongnu.org/archive/html/qemu-devel/2012-09/msg03451.html

Cc: Juan Quintela <quintela@redhat.com>
Cc: Michael Roth <mdroth@linux.vnet.ibm.com>

Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Aurélien Jarno <aurelien@aurel32.net>

Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Michael Walle <michael@walle.cc>
Cc: Jia Liu <proljc@gmail.com>

Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Alexander Graf <agraf@suse.de>
Cc: qemu-ppc@nongnu.org

Andreas Färber (6):
  cpu: Register VMStateDescription through CPUState
  target-i386: Update VMStateDescription to X86CPU
  target-lm32: Update VMStateDescription to LM32CPU
  target-alpha: Register VMStateDescription for AlphaCPU
  target-openrisc: Register VMStateDescription for OpenRISCCPU
  cpu: Guard cpu_{save,load}() definitions

 exec.c                    |   13 ++-
 include/qemu-common.h     |    2 +
 include/qom/cpu.h         |    3 +
 target-alpha/cpu-qom.h    |    2 +
 target-alpha/cpu.c        |    3 +
 target-alpha/machine.c    |   64 ++++++--------
 target-i386/cpu-qom.h     |    2 +
 target-i386/cpu.c         |    4 +
 target-i386/cpu.h         |    2 -
 target-i386/machine.c     |  215 ++++++++++++++++++++++-----------------------
 target-lm32/cpu-qom.h     |    2 +
 target-lm32/cpu.c         |    4 +
 target-lm32/cpu.h         |    2 -
 target-lm32/machine.c     |   36 +++-----
 target-openrisc/cpu.c     |    3 +
 target-openrisc/cpu.h     |    2 +
 target-openrisc/machine.c |   33 +++----
 17 Dateien geändert, 200 Zeilen hinzugefügt(+), 192 Zeilen entfernt(-)

-- 
1.7.10.4

[Qemu-devel] [PATCH RFC qom-cpu-next 1/6] cpu: Register VMStateDescription through CPUState

[Andreas Färber]

In comparison to DeviceClass::vmsd, CPU VMState is split in two,
"cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1.
Therefore add a CPU-specific CPUClass::vmsd field.

Unlike the legacy CPUArchState registration, rather register CPUState.

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 exec.c            |   13 +++++++++++--
 include/qom/cpu.h |    3 +++
 2 Dateien geändert, 14 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)

diff --git a/exec.c b/exec.c
index b85508b..5eee174 100644
--- a/exec.c
+++ b/exec.c
@@ -219,7 +219,7 @@ void cpu_exec_init_all(void)
 #endif
 }
 
-#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
 
 static int cpu_common_post_load(void *opaque, int version_id)
 {
@@ -266,6 +266,9 @@ CPUState *qemu_get_cpu(int index)
 void cpu_exec_init(CPUArchState *env)
 {
     CPUState *cpu = ENV_GET_CPU(env);
+#if !defined(CONFIG_USER_ONLY) && !defined(CPU_SAVE_VERSION)
+    CPUClass *cc = CPU_GET_CLASS(cpu);
+#endif
     CPUArchState **penv;
     int cpu_index;
 
@@ -290,10 +293,16 @@ void cpu_exec_init(CPUArchState *env)
 #if defined(CONFIG_USER_ONLY)
     cpu_list_unlock();
 #endif
-#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
     vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
+#if defined(CPU_SAVE_VERSION)
     register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
                     cpu_save, cpu_load, env);
+#else
+    if (cc->vmsd != NULL) {
+        vmstate_register(NULL, cpu_index, cc->vmsd, cpu);
+    }
+#endif
 #endif
 }
 
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 46f2247..b870752 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -43,6 +43,7 @@ typedef struct CPUState CPUState;
  * @class_by_name: Callback to map -cpu command line model name to an
  * instantiatable CPU type.
  * @reset: Callback to reset the #CPUState to its initial state.
+ * @vmsd: State description for migration.
  *
  * Represents a CPU family or model.
  */
@@ -54,6 +55,8 @@ typedef struct CPUClass {
     ObjectClass *(*class_by_name)(const char *cpu_model);
 
     void (*reset)(CPUState *cpu);
+
+    const struct VMStateDescription *vmsd;
 } CPUClass;
 
 struct KVMState;
-- 
1.7.10.4

[Qemu-devel] [PATCH RFC qom-cpu-next 2/6] target-i386: Update VMStateDescription to X86CPU

[Andreas Färber]

Expose vmstate_cpu as vmstate_x86_cpu and hook it up to CPUClass::vmsd.
Adapt opaques and VMState fields to X86CPU. Drop cpu_{save,load}().

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-i386/cpu-qom.h |    2 +
 target-i386/cpu.c     |    4 +
 target-i386/cpu.h     |    2 -
 target-i386/machine.c |  215 ++++++++++++++++++++++++-------------------------
 4 Dateien geändert, 113 Zeilen hinzugefügt(+), 110 Zeilen entfernt(-)

diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
index 48e6b54..4a1e32b 100644
--- a/target-i386/cpu-qom.h
+++ b/target-i386/cpu-qom.h
@@ -74,5 +74,7 @@ static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
 
 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
 
+extern const struct VMStateDescription vmstate_x86_cpu;
+
 
 #endif
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index ea0ce0b..307fc81 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2214,6 +2214,10 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
 
     xcc->parent_reset = cc->reset;
     cc->reset = x86_cpu_reset;
+
+#ifndef CONFIG_USER_ONLY
+    cc->vmsd = &vmstate_x86_cpu;
+#endif
 }
 
 static const TypeInfo x86_cpu_type_info = {
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 9e6e1a6..2019f2b 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1082,8 +1082,6 @@ static inline CPUX86State *cpu_init(const char *cpu_model)
 #define cpu_list x86_cpu_list
 #define cpudef_setup	x86_cpudef_setup
 
-#define CPU_SAVE_VERSION 12
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _user
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 8df6a6b..c9984b8 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -171,14 +171,16 @@ static const VMStateInfo vmstate_fpreg_1_no_mmx = {
 
 static bool fpregs_is_0(void *opaque, int version_id)
 {
-    CPUX86State *env = opaque;
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
 
     return (env->fpregs_format_vmstate == 0);
 }
 
 static bool fpregs_is_1_mmx(void *opaque, int version_id)
 {
-    CPUX86State *env = opaque;
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
     int guess_mmx;
 
     guess_mmx = ((env->fptag_vmstate == 0xff) &&
@@ -188,7 +190,8 @@ static bool fpregs_is_1_mmx(void *opaque, int version_id)
 
 static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
 {
-    CPUX86State *env = opaque;
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
     int guess_mmx;
 
     guess_mmx = ((env->fptag_vmstate == 0xff) &&
@@ -237,7 +240,8 @@ static const VMStateInfo vmstate_hack_uint64_as_uint32 = {
 
 static void cpu_pre_save(void *opaque)
 {
-    CPUX86State *env = opaque;
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
     int i;
 
     /* FPU */
@@ -252,7 +256,8 @@ static void cpu_pre_save(void *opaque)
 
 static int cpu_post_load(void *opaque, int version_id)
 {
-    CPUX86State *env = opaque;
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
     int i;
 
     /* XXX: restore FPU round state */
@@ -275,16 +280,16 @@ static int cpu_post_load(void *opaque, int version_id)
 
 static bool async_pf_msr_needed(void *opaque)
 {
-    CPUX86State *cpu = opaque;
+    X86CPU *cpu = opaque;
 
-    return cpu->async_pf_en_msr != 0;
+    return cpu->env.async_pf_en_msr != 0;
 }
 
 static bool pv_eoi_msr_needed(void *opaque)
 {
-    CPUX86State *cpu = opaque;
+    X86CPU *cpu = opaque;
 
-    return cpu->pv_eoi_en_msr != 0;
+    return cpu->env.pv_eoi_en_msr != 0;
 }
 
 static const VMStateDescription vmstate_async_pf_msr = {
@@ -293,7 +298,7 @@ static const VMStateDescription vmstate_async_pf_msr = {
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields      = (VMStateField []) {
-        VMSTATE_UINT64(async_pf_en_msr, CPUX86State),
+        VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),
         VMSTATE_END_OF_LIST()
     }
 };
@@ -304,14 +309,15 @@ static const VMStateDescription vmstate_pv_eoi_msr = {
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields      = (VMStateField []) {
-        VMSTATE_UINT64(pv_eoi_en_msr, CPUX86State),
+        VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),
         VMSTATE_END_OF_LIST()
     }
 };
 
 static bool fpop_ip_dp_needed(void *opaque)
 {
-    CPUX86State *env = opaque;
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
 
     return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
 }
@@ -322,16 +328,17 @@ static const VMStateDescription vmstate_fpop_ip_dp = {
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields      = (VMStateField []) {
-        VMSTATE_UINT16(fpop, CPUX86State),
-        VMSTATE_UINT64(fpip, CPUX86State),
-        VMSTATE_UINT64(fpdp, CPUX86State),
+        VMSTATE_UINT16(env.fpop, X86CPU),
+        VMSTATE_UINT64(env.fpip, X86CPU),
+        VMSTATE_UINT64(env.fpdp, X86CPU),
         VMSTATE_END_OF_LIST()
     }
 };
 
 static bool tsc_adjust_needed(void *opaque)
 {
-    CPUX86State *env = opaque;
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
 
     return env->tsc_adjust != 0;
 }
@@ -342,14 +349,15 @@ static const VMStateDescription vmstate_msr_tsc_adjust = {
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields      = (VMStateField[]) {
-        VMSTATE_UINT64(tsc_adjust, CPUX86State),
+        VMSTATE_UINT64(env.tsc_adjust, X86CPU),
         VMSTATE_END_OF_LIST()
     }
 };
 
 static bool tscdeadline_needed(void *opaque)
 {
-    CPUX86State *env = opaque;
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
 
     return env->tsc_deadline != 0;
 }
@@ -360,14 +368,15 @@ static const VMStateDescription vmstate_msr_tscdeadline = {
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields      = (VMStateField []) {
-        VMSTATE_UINT64(tsc_deadline, CPUX86State),
+        VMSTATE_UINT64(env.tsc_deadline, X86CPU),
         VMSTATE_END_OF_LIST()
     }
 };
 
 static bool misc_enable_needed(void *opaque)
 {
-    CPUX86State *env = opaque;
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
 
     return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
 }
@@ -378,111 +387,111 @@ static const VMStateDescription vmstate_msr_ia32_misc_enable = {
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields      = (VMStateField []) {
-        VMSTATE_UINT64(msr_ia32_misc_enable, CPUX86State),
+        VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),
         VMSTATE_END_OF_LIST()
     }
 };
 
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_x86_cpu = {
     .name = "cpu",
-    .version_id = CPU_SAVE_VERSION,
+    .version_id = 12,
     .minimum_version_id = 3,
     .minimum_version_id_old = 3,
     .pre_save = cpu_pre_save,
     .post_load = cpu_post_load,
     .fields      = (VMStateField []) {
-        VMSTATE_UINTTL_ARRAY(regs, CPUX86State, CPU_NB_REGS),
-        VMSTATE_UINTTL(eip, CPUX86State),
-        VMSTATE_UINTTL(eflags, CPUX86State),
-        VMSTATE_UINT32(hflags, CPUX86State),
+        VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),
+        VMSTATE_UINTTL(env.eip, X86CPU),
+        VMSTATE_UINTTL(env.eflags, X86CPU),
+        VMSTATE_UINT32(env.hflags, X86CPU),
         /* FPU */
-        VMSTATE_UINT16(fpuc, CPUX86State),
-        VMSTATE_UINT16(fpus_vmstate, CPUX86State),
-        VMSTATE_UINT16(fptag_vmstate, CPUX86State),
-        VMSTATE_UINT16(fpregs_format_vmstate, CPUX86State),
-        VMSTATE_FP_REGS(fpregs, CPUX86State, 8),
-
-        VMSTATE_SEGMENT_ARRAY(segs, CPUX86State, 6),
-        VMSTATE_SEGMENT(ldt, CPUX86State),
-        VMSTATE_SEGMENT(tr, CPUX86State),
-        VMSTATE_SEGMENT(gdt, CPUX86State),
-        VMSTATE_SEGMENT(idt, CPUX86State),
-
-        VMSTATE_UINT32(sysenter_cs, CPUX86State),
+        VMSTATE_UINT16(env.fpuc, X86CPU),
+        VMSTATE_UINT16(env.fpus_vmstate, X86CPU),
+        VMSTATE_UINT16(env.fptag_vmstate, X86CPU),
+        VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),
+        VMSTATE_FP_REGS(env.fpregs, X86CPU, 8),
+
+        VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
+        VMSTATE_SEGMENT(env.ldt, X86CPU),
+        VMSTATE_SEGMENT(env.tr, X86CPU),
+        VMSTATE_SEGMENT(env.gdt, X86CPU),
+        VMSTATE_SEGMENT(env.idt, X86CPU),
+
+        VMSTATE_UINT32(env.sysenter_cs, X86CPU),
 #ifdef TARGET_X86_64
         /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
-        VMSTATE_HACK_UINT32(sysenter_esp, CPUX86State, less_than_7),
-        VMSTATE_HACK_UINT32(sysenter_eip, CPUX86State, less_than_7),
-        VMSTATE_UINTTL_V(sysenter_esp, CPUX86State, 7),
-        VMSTATE_UINTTL_V(sysenter_eip, CPUX86State, 7),
+        VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7),
+        VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7),
+        VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7),
+        VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7),
 #else
-        VMSTATE_UINTTL(sysenter_esp, CPUX86State),
-        VMSTATE_UINTTL(sysenter_eip, CPUX86State),
+        VMSTATE_UINTTL(env.sysenter_esp, X86CPU),
+        VMSTATE_UINTTL(env.sysenter_eip, X86CPU),
 #endif
 
-        VMSTATE_UINTTL(cr[0], CPUX86State),
-        VMSTATE_UINTTL(cr[2], CPUX86State),
-        VMSTATE_UINTTL(cr[3], CPUX86State),
-        VMSTATE_UINTTL(cr[4], CPUX86State),
-        VMSTATE_UINTTL_ARRAY(dr, CPUX86State, 8),
+        VMSTATE_UINTTL(env.cr[0], X86CPU),
+        VMSTATE_UINTTL(env.cr[2], X86CPU),
+        VMSTATE_UINTTL(env.cr[3], X86CPU),
+        VMSTATE_UINTTL(env.cr[4], X86CPU),
+        VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
         /* MMU */
-        VMSTATE_INT32(a20_mask, CPUX86State),
+        VMSTATE_INT32(env.a20_mask, X86CPU),
         /* XMM */
-        VMSTATE_UINT32(mxcsr, CPUX86State),
-        VMSTATE_XMM_REGS(xmm_regs, CPUX86State, CPU_NB_REGS),
+        VMSTATE_UINT32(env.mxcsr, X86CPU),
+        VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, CPU_NB_REGS),
 
 #ifdef TARGET_X86_64
-        VMSTATE_UINT64(efer, CPUX86State),
-        VMSTATE_UINT64(star, CPUX86State),
-        VMSTATE_UINT64(lstar, CPUX86State),
-        VMSTATE_UINT64(cstar, CPUX86State),
-        VMSTATE_UINT64(fmask, CPUX86State),
-        VMSTATE_UINT64(kernelgsbase, CPUX86State),
+        VMSTATE_UINT64(env.efer, X86CPU),
+        VMSTATE_UINT64(env.star, X86CPU),
+        VMSTATE_UINT64(env.lstar, X86CPU),
+        VMSTATE_UINT64(env.cstar, X86CPU),
+        VMSTATE_UINT64(env.fmask, X86CPU),
+        VMSTATE_UINT64(env.kernelgsbase, X86CPU),
 #endif
-        VMSTATE_UINT32_V(smbase, CPUX86State, 4),
-
-        VMSTATE_UINT64_V(pat, CPUX86State, 5),
-        VMSTATE_UINT32_V(hflags2, CPUX86State, 5),
-
-        VMSTATE_UINT32_TEST(halted, CPUX86State, version_is_5),
-        VMSTATE_UINT64_V(vm_hsave, CPUX86State, 5),
-        VMSTATE_UINT64_V(vm_vmcb, CPUX86State, 5),
-        VMSTATE_UINT64_V(tsc_offset, CPUX86State, 5),
-        VMSTATE_UINT64_V(intercept, CPUX86State, 5),
-        VMSTATE_UINT16_V(intercept_cr_read, CPUX86State, 5),
-        VMSTATE_UINT16_V(intercept_cr_write, CPUX86State, 5),
-        VMSTATE_UINT16_V(intercept_dr_read, CPUX86State, 5),
-        VMSTATE_UINT16_V(intercept_dr_write, CPUX86State, 5),
-        VMSTATE_UINT32_V(intercept_exceptions, CPUX86State, 5),
-        VMSTATE_UINT8_V(v_tpr, CPUX86State, 5),
+        VMSTATE_UINT32_V(env.smbase, X86CPU, 4),
+
+        VMSTATE_UINT64_V(env.pat, X86CPU, 5),
+        VMSTATE_UINT32_V(env.hflags2, X86CPU, 5),
+
+        VMSTATE_UINT32_TEST(env.halted, X86CPU, version_is_5),
+        VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5),
+        VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5),
+        VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5),
+        VMSTATE_UINT64_V(env.intercept, X86CPU, 5),
+        VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5),
+        VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5),
+        VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5),
+        VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5),
+        VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5),
+        VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5),
         /* MTRRs */
-        VMSTATE_UINT64_ARRAY_V(mtrr_fixed, CPUX86State, 11, 8),
-        VMSTATE_UINT64_V(mtrr_deftype, CPUX86State, 8),
-        VMSTATE_MTRR_VARS(mtrr_var, CPUX86State, 8, 8),
+        VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8),
+        VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8),
+        VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, 8, 8),
         /* KVM-related states */
-        VMSTATE_INT32_V(interrupt_injected, CPUX86State, 9),
-        VMSTATE_UINT32_V(mp_state, CPUX86State, 9),
-        VMSTATE_UINT64_V(tsc, CPUX86State, 9),
-        VMSTATE_INT32_V(exception_injected, CPUX86State, 11),
-        VMSTATE_UINT8_V(soft_interrupt, CPUX86State, 11),
-        VMSTATE_UINT8_V(nmi_injected, CPUX86State, 11),
-        VMSTATE_UINT8_V(nmi_pending, CPUX86State, 11),
-        VMSTATE_UINT8_V(has_error_code, CPUX86State, 11),
-        VMSTATE_UINT32_V(sipi_vector, CPUX86State, 11),
+        VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9),
+        VMSTATE_UINT32_V(env.mp_state, X86CPU, 9),
+        VMSTATE_UINT64_V(env.tsc, X86CPU, 9),
+        VMSTATE_INT32_V(env.exception_injected, X86CPU, 11),
+        VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11),
+        VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11),
+        VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11),
+        VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11),
+        VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11),
         /* MCE */
-        VMSTATE_UINT64_V(mcg_cap, CPUX86State, 10),
-        VMSTATE_UINT64_V(mcg_status, CPUX86State, 10),
-        VMSTATE_UINT64_V(mcg_ctl, CPUX86State, 10),
-        VMSTATE_UINT64_ARRAY_V(mce_banks, CPUX86State, MCE_BANKS_DEF *4, 10),
+        VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10),
+        VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10),
+        VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10),
+        VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10),
         /* rdtscp */
-        VMSTATE_UINT64_V(tsc_aux, CPUX86State, 11),
+        VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11),
         /* KVM pvclock msr */
-        VMSTATE_UINT64_V(system_time_msr, CPUX86State, 11),
-        VMSTATE_UINT64_V(wall_clock_msr, CPUX86State, 11),
+        VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11),
+        VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11),
         /* XSAVE related fields */
-        VMSTATE_UINT64_V(xcr0, CPUX86State, 12),
-        VMSTATE_UINT64_V(xstate_bv, CPUX86State, 12),
-        VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUX86State, CPU_NB_REGS, 12),
+        VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
+        VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
+        VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS, 12),
         VMSTATE_END_OF_LIST()
         /* The above list is not sorted /wrt version numbers, watch out! */
     },
@@ -510,13 +519,3 @@ static const VMStateDescription vmstate_cpu = {
         }
     }
 };
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
-    vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
-- 
1.7.10.4

[Qemu-devel] [PATCH RFC qom-cpu-next 3/6] target-lm32: Update VMStateDescription to LM32CPU

[Andreas Färber]

Expose vmstate_cpu as vmstate_lm32_cpu and hook it up to CPUClass::vmsd.
Adapt VMState fields to LM32CPU. Drop cpu_{save,load}().

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-lm32/cpu-qom.h |    2 ++
 target-lm32/cpu.c     |    4 ++++
 target-lm32/cpu.h     |    2 --
 target-lm32/machine.c |   36 +++++++++++++-----------------------
 4 Dateien geändert, 19 Zeilen hinzugefügt(+), 25 Zeilen entfernt(-)

diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h
index d7525b3..9dd9d66 100644
--- a/target-lm32/cpu-qom.h
+++ b/target-lm32/cpu-qom.h
@@ -69,5 +69,7 @@ static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env)
 
 #define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e))
 
+extern const struct VMStateDescription vmstate_lm32_cpu;
+
 
 #endif
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index 5f16734..89c365b 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -81,6 +81,10 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
 
     lcc->parent_reset = cc->reset;
     cc->reset = lm32_cpu_reset;
+
+#ifndef CONFIG_USER_ONLY
+    cc->vmsd = &vmstate_lm32_cpu;
+#endif
 }
 
 static const TypeInfo lm32_cpu_type_info = {
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 4e202db..65fc366 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -213,8 +213,6 @@ static inline CPULM32State *cpu_init(const char *cpu_model)
 #define cpu_gen_code cpu_lm32_gen_code
 #define cpu_signal_handler cpu_lm32_signal_handler
 
-#define CPU_SAVE_VERSION 1
-
 int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
                               int mmu_idx);
 #define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
diff --git a/target-lm32/machine.c b/target-lm32/machine.c
index 6802e81..aa4a9e1 100644
--- a/target-lm32/machine.c
+++ b/target-lm32/machine.c
@@ -1,33 +1,23 @@
 #include "hw/hw.h"
 #include "hw/boards.h"
 
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_lm32_cpu = {
     .name = "cpu",
-    .version_id = CPU_SAVE_VERSION,
+    .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields      = (VMStateField[]) {
-        VMSTATE_UINT32_ARRAY(regs, CPULM32State, 32),
-        VMSTATE_UINT32(pc, CPULM32State),
-        VMSTATE_UINT32(ie, CPULM32State),
-        VMSTATE_UINT32(icc, CPULM32State),
-        VMSTATE_UINT32(dcc, CPULM32State),
-        VMSTATE_UINT32(cc, CPULM32State),
-        VMSTATE_UINT32(eba, CPULM32State),
-        VMSTATE_UINT32(dc, CPULM32State),
-        VMSTATE_UINT32(deba, CPULM32State),
-        VMSTATE_UINT32_ARRAY(bp, CPULM32State, 4),
-        VMSTATE_UINT32_ARRAY(wp, CPULM32State, 4),
+        VMSTATE_UINT32_ARRAY(env.regs, LM32CPU, 32),
+        VMSTATE_UINT32(env.pc, LM32CPU),
+        VMSTATE_UINT32(env.ie, LM32CPU),
+        VMSTATE_UINT32(env.icc, LM32CPU),
+        VMSTATE_UINT32(env.dcc, LM32CPU),
+        VMSTATE_UINT32(env.cc, LM32CPU),
+        VMSTATE_UINT32(env.eba, LM32CPU),
+        VMSTATE_UINT32(env.dc, LM32CPU),
+        VMSTATE_UINT32(env.deba, LM32CPU),
+        VMSTATE_UINT32_ARRAY(env.bp, LM32CPU, 4),
+        VMSTATE_UINT32_ARRAY(env.wp, LM32CPU, 4),
         VMSTATE_END_OF_LIST()
     }
 };
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
-    vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu-next 4/6] target-alpha: Register VMStateDescription for AlphaCPU

[Andreas Färber]

Commit b758aca1f6cdb175634812b79f5560c36c902d00 (target-alpha: Enable
the alpha-softmmu target.) introduced cpu_{save,load}() functions but
didn't define CPU_SAVE_VERSION, so they were never registered.

Drop cpu_{save,load}() and register the VMStateDescription via CPUClass.
This operates on the AlphaCPU object instead of CPUAlphaState.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-alpha/cpu-qom.h |    2 ++
 target-alpha/cpu.c     |    3 +++
 target-alpha/machine.c |   64 ++++++++++++++++++++++--------------------------
 3 Dateien geändert, 34 Zeilen hinzugefügt(+), 35 Zeilen entfernt(-)

diff --git a/target-alpha/cpu-qom.h b/target-alpha/cpu-qom.h
index c0f6c6d..2cf6511 100644
--- a/target-alpha/cpu-qom.h
+++ b/target-alpha/cpu-qom.h
@@ -72,5 +72,7 @@ static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env)
 
 #define ENV_GET_CPU(e) CPU(alpha_env_get_cpu(e))
 
+extern const struct VMStateDescription vmstate_alpha_cpu;
+
 
 #endif
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 0cdae69..09f8cdc 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -261,6 +261,9 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
     dc->realize = alpha_cpu_realizefn;
 
     cc->class_by_name = alpha_cpu_class_by_name;
+#ifndef CONFIG_USER_ONLY
+    cc->vmsd = &vmstate_alpha_cpu;
+#endif
 }
 
 static const TypeInfo alpha_cpu_type_info = {
diff --git a/target-alpha/machine.c b/target-alpha/machine.c
index 1c9edd1..bdad91e 100644
--- a/target-alpha/machine.c
+++ b/target-alpha/machine.c
@@ -3,14 +3,18 @@
 
 static int get_fpcr(QEMUFile *f, void *opaque, size_t size)
 {
-    CPUAlphaState *env = opaque;
+    AlphaCPU *cpu = opaque;
+    CPUAlphaState *env = &cpu->env;
+
     cpu_alpha_store_fpcr(env, qemu_get_be64(f));
     return 0;
 }
 
 static void put_fpcr(QEMUFile *f, void *opaque, size_t size)
 {
-    CPUAlphaState *env = opaque;
+    AlphaCPU *cpu = opaque;
+    CPUAlphaState *env = &cpu->env;
+
     qemu_put_be64(f, cpu_alpha_load_fpcr(env));
 }
 
@@ -21,8 +25,8 @@ static const VMStateInfo vmstate_fpcr = {
 };
 
 static VMStateField vmstate_cpu_fields[] = {
-    VMSTATE_UINTTL_ARRAY(ir, CPUAlphaState, 31),
-    VMSTATE_UINTTL_ARRAY(fir, CPUAlphaState, 31),
+    VMSTATE_UINTTL_ARRAY(env.ir, AlphaCPU, 31),
+    VMSTATE_UINTTL_ARRAY(env.fir, AlphaCPU, 31),
     /* Save the architecture value of the fpcr, not the internally
        expanded version.  Since this architecture value does not
        exist in memory to be stored, this requires a but of hoop
@@ -37,51 +41,41 @@ static VMStateField vmstate_cpu_fields[] = {
         .flags = VMS_SINGLE,
         .offset = 0
     },
-    VMSTATE_UINTTL(pc, CPUAlphaState),
-    VMSTATE_UINTTL(unique, CPUAlphaState),
-    VMSTATE_UINTTL(lock_addr, CPUAlphaState),
-    VMSTATE_UINTTL(lock_value, CPUAlphaState),
+    VMSTATE_UINTTL(env.pc, AlphaCPU),
+    VMSTATE_UINTTL(env.unique, AlphaCPU),
+    VMSTATE_UINTTL(env.lock_addr, AlphaCPU),
+    VMSTATE_UINTTL(env.lock_value, AlphaCPU),
     /* Note that lock_st_addr is not saved; it is a temporary
        used during the execution of the st[lq]_c insns.  */
 
-    VMSTATE_UINT8(ps, CPUAlphaState),
-    VMSTATE_UINT8(intr_flag, CPUAlphaState),
-    VMSTATE_UINT8(pal_mode, CPUAlphaState),
-    VMSTATE_UINT8(fen, CPUAlphaState),
+    VMSTATE_UINT8(env.ps, AlphaCPU),
+    VMSTATE_UINT8(env.intr_flag, AlphaCPU),
+    VMSTATE_UINT8(env.pal_mode, AlphaCPU),
+    VMSTATE_UINT8(env.fen, AlphaCPU),
 
-    VMSTATE_UINT32(pcc_ofs, CPUAlphaState),
+    VMSTATE_UINT32(env.pcc_ofs, AlphaCPU),
 
-    VMSTATE_UINTTL(trap_arg0, CPUAlphaState),
-    VMSTATE_UINTTL(trap_arg1, CPUAlphaState),
-    VMSTATE_UINTTL(trap_arg2, CPUAlphaState),
+    VMSTATE_UINTTL(env.trap_arg0, AlphaCPU),
+    VMSTATE_UINTTL(env.trap_arg1, AlphaCPU),
+    VMSTATE_UINTTL(env.trap_arg2, AlphaCPU),
 
-    VMSTATE_UINTTL(exc_addr, CPUAlphaState),
-    VMSTATE_UINTTL(palbr, CPUAlphaState),
-    VMSTATE_UINTTL(ptbr, CPUAlphaState),
-    VMSTATE_UINTTL(vptptr, CPUAlphaState),
-    VMSTATE_UINTTL(sysval, CPUAlphaState),
-    VMSTATE_UINTTL(usp, CPUAlphaState),
+    VMSTATE_UINTTL(env.exc_addr, AlphaCPU),
+    VMSTATE_UINTTL(env.palbr, AlphaCPU),
+    VMSTATE_UINTTL(env.ptbr, AlphaCPU),
+    VMSTATE_UINTTL(env.vptptr, AlphaCPU),
+    VMSTATE_UINTTL(env.sysval, AlphaCPU),
+    VMSTATE_UINTTL(env.usp, AlphaCPU),
 
-    VMSTATE_UINTTL_ARRAY(shadow, CPUAlphaState, 8),
-    VMSTATE_UINTTL_ARRAY(scratch, CPUAlphaState, 24),
+    VMSTATE_UINTTL_ARRAY(env.shadow, AlphaCPU, 8),
+    VMSTATE_UINTTL_ARRAY(env.scratch, AlphaCPU, 24),
 
     VMSTATE_END_OF_LIST()
 };
 
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_alpha_cpu = {
     .name = "cpu",
     .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields = vmstate_cpu_fields,
 };
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
-    vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu-next 5/6] target-openrisc: Register VMStateDescription for OpenRISCCPU

[Andreas Färber]

Since commit e67db06e9f6d7e514ee2a9b9b769ecd42977f6fb (target-or32: Add
target stubs and QOM cpu) a VMStateDescription existed, but
CPU_SAVE_VERSION was not set, so it was never registered.

Register it through CPUState.
Use a version_id of 1 and specify minimum versions as well.

Cc: Jia Liu <proljc@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-openrisc/cpu.c     |    3 +++
 target-openrisc/cpu.h     |    2 ++
 target-openrisc/machine.c |   33 +++++++++++++--------------------
 3 Dateien geändert, 18 Zeilen hinzugefügt(+), 20 Zeilen entfernt(-)

diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index d8cc533..d0873e8 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -146,6 +146,9 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
     cc->reset = openrisc_cpu_reset;
 
     cc->class_by_name = openrisc_cpu_class_by_name;
+#ifndef CONFIG_USER_ONLY
+    cc->vmsd = &vmstate_openrisc_cpu;
+#endif
 }
 
 static void cpu_register(const OpenRISCCPUInfo *info)
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 419f007..1d350d2 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -358,6 +358,8 @@ int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
 #define cpu_signal_handler cpu_openrisc_signal_handler
 
 #ifndef CONFIG_USER_ONLY
+extern const struct VMStateDescription vmstate_openrisc_cpu;
+
 /* hw/openrisc_pic.c */
 void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
 
diff --git a/target-openrisc/machine.c b/target-openrisc/machine.c
index cba9811..7d335e0 100644
--- a/target-openrisc/machine.c
+++ b/target-openrisc/machine.c
@@ -20,28 +20,21 @@
 #include "hw/hw.h"
 #include "hw/boards.h"
 
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_openrisc_cpu = {
     .name = "cpu",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
     .fields = (VMStateField[]) {
-        VMSTATE_UINT32_ARRAY(gpr, CPUOpenRISCState, 32),
-        VMSTATE_UINT32(sr, CPUOpenRISCState),
-        VMSTATE_UINT32(epcr, CPUOpenRISCState),
-        VMSTATE_UINT32(eear, CPUOpenRISCState),
-        VMSTATE_UINT32(esr, CPUOpenRISCState),
-        VMSTATE_UINT32(fpcsr, CPUOpenRISCState),
-        VMSTATE_UINT32(pc, CPUOpenRISCState),
-        VMSTATE_UINT32(npc, CPUOpenRISCState),
-        VMSTATE_UINT32(ppc, CPUOpenRISCState),
+        VMSTATE_UINT32_ARRAY(env.gpr, OpenRISCCPU, 32),
+        VMSTATE_UINT32(env.sr, OpenRISCCPU),
+        VMSTATE_UINT32(env.epcr, OpenRISCCPU),
+        VMSTATE_UINT32(env.eear, OpenRISCCPU),
+        VMSTATE_UINT32(env.esr, OpenRISCCPU),
+        VMSTATE_UINT32(env.fpcsr, OpenRISCCPU),
+        VMSTATE_UINT32(env.pc, OpenRISCCPU),
+        VMSTATE_UINT32(env.npc, OpenRISCCPU),
+        VMSTATE_UINT32(env.ppc, OpenRISCCPU),
         VMSTATE_END_OF_LIST()
     }
 };
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
-    vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
-- 
1.7.10.4

[Qemu-devel] [RFC qom-cpu-next 6/6] cpu: Guard cpu_{save, load}() definitions

[Andreas Färber]

A few targets already managed to implement cpu_save() and cpu_load()
without defining CPU_SAVE_VERSION that causes them to be registered.

Guard the prototypes with CPU_SAVE_VERSION to avoid this happening again
until all targets are converted to VMState or QIDL.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 include/qemu-common.h |    2 ++
 1 Datei geändert, 2 Zeilen hinzugefügt(+)

diff --git a/include/qemu-common.h b/include/qemu-common.h
index af2379f..ef8a3fd 100644
--- a/include/qemu-common.h
+++ b/include/qemu-common.h
@@ -276,8 +276,10 @@ bool tcg_enabled(void);
 void cpu_exec_init_all(void);
 
 /* CPU save/load.  */
+#ifdef CPU_SAVE_VERSION
 void cpu_save(QEMUFile *f, void *opaque);
 int cpu_load(QEMUFile *f, void *opaque, int version_id);
+#endif
 
 /* Unblock cpu */
 void qemu_cpu_kick_self(void);
-- 
1.7.10.4