From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:46112) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCfpJ-00067a-CW for qemu-devel@nongnu.org; Mon, 04 Mar 2013 19:33:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCfpG-0004Be-HC for qemu-devel@nongnu.org; Mon, 04 Mar 2013 19:33:53 -0500 Received: from mail-ia0-x22b.google.com ([2607:f8b0:4001:c02::22b]:37161) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCfpG-0004BO-Bn for qemu-devel@nongnu.org; Mon, 04 Mar 2013 19:33:50 -0500 Received: by mail-ia0-f171.google.com with SMTP id z13so5439578iaz.2 for ; Mon, 04 Mar 2013 16:33:50 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Mon, 4 Mar 2013 16:33:01 -0800 Message-Id: <1362443590-28191-19-git-send-email-rth@twiddle.net> In-Reply-To: <1362443590-28191-1-git-send-email-rth@twiddle.net> References: <1362443590-28191-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 18/27] tcg-ppc64: Implement compound logicals List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: av1474@comtv.ru Mostly copied from the ppc32 port. Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 34 ++++++++++++++++++++++++++++++++++ tcg/ppc64/tcg-target.h | 20 ++++++++++---------- 2 files changed, 44 insertions(+), 10 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 576effc..a1be15a 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -385,6 +385,10 @@ static int tcg_target_const_match (tcg_target_long val, #define NOR XO31(124) #define CNTLZW XO31( 26) #define CNTLZD XO31( 58) +#define ANDC XO31( 60) +#define ORC XO31(412) +#define EQV XO31(284) +#define NAND XO31(476) #define MULLD XO31(233) #define MULHD XO31( 73) @@ -1415,6 +1419,26 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out32(s, XOR | SAB(a1, a0, a2)); } break; + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + tcg_out32(s, ANDC | SAB(args[1], args[0], args[2])); + break; + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); + break; + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); + break; + case INDEX_op_nand_i32: + case INDEX_op_nand_i64: + tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); + break; + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: + tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); + break; case INDEX_op_mul_i32: if (const_args[2]) { @@ -1788,6 +1812,11 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_and_i32, { "r", "r", "ri" } }, { INDEX_op_or_i32, { "r", "r", "ri" } }, { INDEX_op_xor_i32, { "r", "r", "ri" } }, + { INDEX_op_andc_i32, { "r", "r", "r" } }, + { INDEX_op_orc_i32, { "r", "r", "r" } }, + { INDEX_op_eqv_i32, { "r", "r", "r" } }, + { INDEX_op_nand_i32, { "r", "r", "r" } }, + { INDEX_op_nor_i32, { "r", "r", "r" } }, { INDEX_op_shl_i32, { "r", "r", "ri" } }, { INDEX_op_shr_i32, { "r", "r", "ri" } }, @@ -1806,6 +1835,11 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_and_i64, { "r", "r", "rU" } }, { INDEX_op_or_i64, { "r", "r", "rU" } }, { INDEX_op_xor_i64, { "r", "r", "rU" } }, + { INDEX_op_andc_i64, { "r", "r", "r" } }, + { INDEX_op_orc_i64, { "r", "r", "r" } }, + { INDEX_op_eqv_i64, { "r", "r", "r" } }, + { INDEX_op_nand_i64, { "r", "r", "r" } }, + { INDEX_op_nor_i64, { "r", "r", "r" } }, { INDEX_op_shl_i64, { "r", "r", "ri" } }, { INDEX_op_shr_i64, { "r", "r", "ri" } }, diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index d8e1820..35414cf 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -82,11 +82,11 @@ typedef enum { #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_neg_i32 1 -#define TCG_TARGET_HAS_andc_i32 0 -#define TCG_TARGET_HAS_orc_i32 0 -#define TCG_TARGET_HAS_eqv_i32 0 -#define TCG_TARGET_HAS_nand_i32 0 -#define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_andc_i32 1 +#define TCG_TARGET_HAS_orc_i32 1 +#define TCG_TARGET_HAS_eqv_i32 1 +#define TCG_TARGET_HAS_nand_i32 1 +#define TCG_TARGET_HAS_nor_i32 1 #define TCG_TARGET_HAS_deposit_i32 0 #define TCG_TARGET_HAS_movcond_i32 0 #define TCG_TARGET_HAS_add2_i32 0 @@ -105,11 +105,11 @@ typedef enum { #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_neg_i64 1 -#define TCG_TARGET_HAS_andc_i64 0 -#define TCG_TARGET_HAS_orc_i64 0 -#define TCG_TARGET_HAS_eqv_i64 0 -#define TCG_TARGET_HAS_nand_i64 0 -#define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_andc_i64 1 +#define TCG_TARGET_HAS_orc_i64 1 +#define TCG_TARGET_HAS_eqv_i64 1 +#define TCG_TARGET_HAS_nand_i64 1 +#define TCG_TARGET_HAS_nor_i64 1 #define TCG_TARGET_HAS_deposit_i64 0 #define TCG_TARGET_HAS_movcond_i64 0 #define TCG_TARGET_HAS_add2_i64 0 -- 1.8.1.2