From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:60007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCh0e-0003E5-FM for qemu-devel@nongnu.org; Mon, 04 Mar 2013 20:49:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCh0W-0007XI-Bo for qemu-devel@nongnu.org; Mon, 04 Mar 2013 20:49:40 -0500 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:60938 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCh0W-0007VY-3j for qemu-devel@nongnu.org; Mon, 04 Mar 2013 20:49:32 -0500 From: Peter Maydell Date: Tue, 5 Mar 2013 01:12:00 +0000 Message-Id: <1362445931-4383-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1362445931-4383-1-git-send-email-peter.maydell@linaro.org> References: <1362445931-4383-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 02/13] target-arm: Don't decode RFE or SRS on M profile cores List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno , Blue Swirl Cc: Anthony Liguori , qemu-devel@nongnu.org, Paul Brook M profile cores do not have the RFE or SRS instructions, so correctly UNDEF these insn patterns on those cores. Signed-off-by: Peter Maydell --- target-arm/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index e16c113..35a21be 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -8180,9 +8180,10 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw } else { /* Load/store multiple, RFE, SRS. */ if (((insn >> 23) & 1) == ((insn >> 24) & 1)) { - /* Not available in user mode. */ - if (IS_USER(s)) + /* RFE, SRS: not available in user mode or on M profile */ + if (IS_USER(s) || IS_M(env)) { goto illegal_op; + } if (insn & (1 << 20)) { /* rfe */ addr = load_reg(s, rn); -- 1.7.9.5