From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:60633) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCu7D-0007Db-Hw for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:49:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCty3-0001pG-Hh for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:39:58 -0500 Received: from mail-we0-x231.google.com ([2a00:1450:400c:c03::231]:64355) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCtQP-0007qq-4J for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:05:05 -0500 Received: by mail-we0-f177.google.com with SMTP id d7so6350279wer.22 for ; Tue, 05 Mar 2013 07:05:04 -0800 (PST) Sender: Paolo Bonzini From: Paolo Bonzini Date: Tue, 5 Mar 2013 16:04:55 +0100 Message-Id: <1362495898-15352-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 0/3] Implement x86 soft reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: lersek@redhat.com, aliguori@us.ibm.com, dwmw2@infradead.org This series makes various devices (port 92h, pckbd and the PIIX4/ICH9 southbridges) implement x86 soft reset correctly. Paolo Bonzini (3): cpu: make CPU_INTERRUPT_RESET available on all targets pc: port 92 reset requires a low->high transition x86: correctly implement soft reset cpu-exec.c | 24 ++++++++++++++---------- cpus.c | 9 +++++++++ hw/lpc_ich9.c | 7 ++++++- hw/pc.c | 6 ++++-- hw/pckbd.c | 5 +++-- hw/piix_pci.c | 8 ++++++-- include/exec/cpu-all.h | 8 +++++--- include/sysemu/cpus.h | 1 + target-i386/cpu.h | 7 ++++--- 9 files changed, 52 insertions(+), 23 deletions(-) -- 1.8.1.4