From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:54736) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCtsO-0004MM-Cr for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:34:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCtsN-00086k-6L for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:34:00 -0500 Received: from mail-wg0-f48.google.com ([74.125.82.48]:42980) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCtQS-0007te-4Y for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:05:08 -0500 Received: by mail-wg0-f48.google.com with SMTP id 16so5714959wgi.15 for ; Tue, 05 Mar 2013 07:05:07 -0800 (PST) Sender: Paolo Bonzini From: Paolo Bonzini Date: Tue, 5 Mar 2013 16:04:57 +0100 Message-Id: <1362495898-15352-3-git-send-email-pbonzini@redhat.com> In-Reply-To: <1362495898-15352-1-git-send-email-pbonzini@redhat.com> References: <1362495898-15352-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 2/3] pc: port 92 reset requires a low->high transition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: lersek@redhat.com, aliguori@us.ibm.com, dwmw2@infradead.org The PIIX datasheet says that "before another INIT pulse can be generated via [port 92h], [bit 0] must be written back to a zero. This bug is masked right now because a full reset will clear the value of port 92h. But once we implement soft reset correctly, the next attempt to enable the A20 line by setting bit 1 (and leaving the others untouched) will cause another reset. Signed-off-by: Paolo Bonzini --- hw/pc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/pc.c b/hw/pc.c index 07caba7..523db1f 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -435,11 +435,12 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { Port92State *s = opaque; + int oldval = s->outport; DPRINTF("port92: write 0x%02x\n", val); s->outport = val; qemu_set_irq(*s->a20_out, (val >> 1) & 1); - if (val & 1) { + if ((val & 1) && !(oldval & 1)) { qemu_system_reset_request(); } } -- 1.8.1.4