From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35491) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCuEb-00043E-Rh for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:57:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCuEX-0008Dx-8f for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:56:57 -0500 Received: from mail-ia0-x235.google.com ([2607:f8b0:4001:c02::235]:37582) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCuEX-0008Do-2v for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:56:53 -0500 Received: by mail-ia0-f181.google.com with SMTP id w33so6302070iag.12 for ; Tue, 05 Mar 2013 07:56:52 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Tue, 5 Mar 2013 07:56:35 -0800 Message-Id: <1362498998-7824-2-git-send-email-rth@twiddle.net> In-Reply-To: <1362498998-7824-1-git-send-email-rth@twiddle.net> References: <1362498998-7824-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 1/4] tcg-arm: Implement deposit for armv7 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org We have BFI and BFC available for implementing it. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 36 ++++++++++++++++++++++++++++++++++++ tcg/arm/tcg-target.h | 5 ++++- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 94c6ca4..3422bd7 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -644,6 +644,35 @@ static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) } } +bool tcg_target_deposit_i32_value(int ofs, int len) +{ + /* ??? Without bfi, we could improve over generic code by combining + the right-shift from a non-zero ofs with the orr. We do run into + problems when rd == rs, and the mask generated from ofs+len don't + fit into an immediate. We would have to be careful not to pessimize + wrt the optimizations performed on the expanded code. */ + return use_armv7_instructions; +} + +static inline void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len, bool const_a1) +{ + if (const_a1) { + uint32_t mask = (2u << (len - 1)) - 1; + a1 &= mask; + if (a1 == 0) { + /* bfi becomes bfc with rn == 15. */ + a1 = 15; + } else { + tcg_out_movi32(s, cond, TCG_REG_R8, a1); + a1 = TCG_REG_R8; + } + } + /* bfi/bfc */ + tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 + | (ofs << 7) | ((ofs + len - 1) << 16)); +} + static inline void tcg_out_ld32_12(TCGContext *s, int cond, int rd, int rn, tcg_target_long im) { @@ -1773,6 +1802,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_ext16u(s, COND_AL, args[0], args[1]); break; + case INDEX_op_deposit_i32: + tcg_out_deposit(s, COND_AL, args[0], args[2], + args[3], args[4], const_args[2]); + break; + default: tcg_abort(); } @@ -1858,6 +1892,8 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_ext16s_i32, { "r", "r" } }, { INDEX_op_ext16u_i32, { "r", "r" } }, + { INDEX_op_deposit_i32, { "r", "0", "ri" } }, + { -1 }, }; diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index b6eed1f..cb89419 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -73,10 +73,13 @@ typedef enum { #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 -#define TCG_TARGET_HAS_deposit_i32 0 +#define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 1 +extern bool tcg_target_deposit_i32_value(int ofs, int len); +#define TCG_TARGET_deposit_i32_valid tcg_target_deposit_i32_value + enum { TCG_AREG0 = TCG_REG_R6, }; -- 1.8.1.2