From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:34201) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCx75-0003FL-4b for qemu-devel@nongnu.org; Tue, 05 Mar 2013 14:01:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCx70-0005f2-6I for qemu-devel@nongnu.org; Tue, 05 Mar 2013 14:01:23 -0500 Received: from mail-qa0-f49.google.com ([209.85.216.49]:53602) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCx70-0005ek-1v for qemu-devel@nongnu.org; Tue, 05 Mar 2013 14:01:18 -0500 Received: by mail-qa0-f49.google.com with SMTP id o13so2085979qaj.8 for ; Tue, 05 Mar 2013 11:01:17 -0800 (PST) Sender: Paolo Bonzini From: Paolo Bonzini Date: Tue, 5 Mar 2013 20:00:53 +0100 Message-Id: <1362510056-3316-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH v2 0/3] Implement x86 soft reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: dwmw2@infradead.org, aliguori@us.ibm.com, lersek@redhat.com, afaerber@suse.de This series makes various devices (port 92h, pckbd and the PIIX4/ICH9 southbridges) implement x86 soft reset correctly. v1->v2: rebased onto Andreas's branch, fixed target-ppc/cpu.h, renamed function Paolo Bonzini (3): cpu: make CPU_INTERRUPT_RESET available on all targets pc: port 92 reset requires a low->high transition hw: correctly implement soft reset cpu-exec.c | 24 ++++++++++++++---------- cpus.c | 9 +++++++++ hw/lpc_ich9.c | 7 ++++++- hw/pc.c | 6 ++++-- hw/pckbd.c | 5 +++-- hw/piix_pci.c | 8 ++++++-- include/exec/cpu-all.h | 8 +++++--- include/sysemu/cpus.h | 1 + target-i386/cpu.h | 7 ++++--- target-ppc/cpu.h | 3 --- 10 files changed, 52 insertions(+), 26 deletions(-) -- 1.8.1.2