From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:34235) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCx77-0003Fz-SL for qemu-devel@nongnu.org; Tue, 05 Mar 2013 14:01:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCx76-0005gK-90 for qemu-devel@nongnu.org; Tue, 05 Mar 2013 14:01:25 -0500 Received: from mail-qa0-f52.google.com ([209.85.216.52]:37760) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCx76-0005gC-5A for qemu-devel@nongnu.org; Tue, 05 Mar 2013 14:01:24 -0500 Received: by mail-qa0-f52.google.com with SMTP id bs12so2099385qab.4 for ; Tue, 05 Mar 2013 11:01:23 -0800 (PST) Sender: Paolo Bonzini From: Paolo Bonzini Date: Tue, 5 Mar 2013 20:00:56 +0100 Message-Id: <1362510056-3316-4-git-send-email-pbonzini@redhat.com> In-Reply-To: <1362510056-3316-1-git-send-email-pbonzini@redhat.com> References: <1362510056-3316-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH v2 3/3] hw: correctly implement soft reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: dwmw2@infradead.org, aliguori@us.ibm.com, lersek@redhat.com, afaerber@suse.de Do not do a hard reset for port 92h, keyboard controller, or cf9h soft reset. These only reset the CPU. Reviewed-by: Anthony Liguori Signed-off-by: Paolo Bonzini --- hw/lpc_ich9.c | 7 ++++++- hw/pc.c | 3 ++- hw/pckbd.c | 5 +++-- hw/piix_pci.c | 8 ++++++-- 4 files changed, 17 insertions(+), 6 deletions(-) diff --git a/hw/lpc_ich9.c b/hw/lpc_ich9.c index e473758..5540f61 100644 --- a/hw/lpc_ich9.c +++ b/hw/lpc_ich9.c @@ -45,6 +45,7 @@ #include "pci/pci_bus.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" +#include "sysemu/cpus.h" static int ich9_lpc_sci_irq(ICH9LPCState *lpc); @@ -506,7 +507,11 @@ static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, ICH9LPCState *lpc = opaque; if (val & 4) { - qemu_system_reset_request(); + if (val & 0xA) { + qemu_system_reset_request(); + } else { + cpu_reset_all_async(); + } return; } lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ diff --git a/hw/pc.c b/hw/pc.c index 3e1cf2e..54f5b72 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -45,6 +45,7 @@ #include "kvm_i386.h" #include "xen.h" #include "sysemu/blockdev.h" +#include "sysemu/cpus.h" #include "hw/block-common.h" #include "ui/qemu-spice.h" #include "exec/memory.h" @@ -443,7 +444,7 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val, s->outport = val; qemu_set_irq(*s->a20_out, (val >> 1) & 1); if ((val & 1) && !(oldval & 1)) { - qemu_system_reset_request(); + cpu_reset_all_async(); } } diff --git a/hw/pckbd.c b/hw/pckbd.c index 3bad09b..fd66788 100644 --- a/hw/pckbd.c +++ b/hw/pckbd.c @@ -26,6 +26,7 @@ #include "pc.h" #include "ps2.h" #include "sysemu/sysemu.h" +#include "sysemu/cpus.h" /* debug PC keyboard */ //#define DEBUG_KBD @@ -220,7 +221,7 @@ static void outport_write(KBDState *s, uint32_t val) qemu_set_irq(*s->a20_out, (val >> 1) & 1); } if (!(val & 1)) { - qemu_system_reset_request(); + cpu_reset_all_async(); } } @@ -299,7 +300,7 @@ static void kbd_write_command(void *opaque, hwaddr addr, s->outport &= ~KBD_OUT_A20; break; case KBD_CCMD_RESET: - qemu_system_reset_request(); + cpu_reset_all_async(); break; case KBD_CCMD_NO_OP: /* ignore that */ diff --git a/hw/piix_pci.c b/hw/piix_pci.c index 6c77e49..785e0a7 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -32,6 +32,7 @@ #include "xen.h" #include "pam.h" #include "sysemu/sysemu.h" +#include "sysemu/cpus.h" /* * I440FX chipset data sheet. @@ -521,8 +522,11 @@ static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) PIIX3State *d = opaque; if (val & 4) { - qemu_system_reset_request(); - return; + if (val & 2) { + qemu_system_reset_request(); + } else { + cpu_reset_all_async(); + } } d->rcr = val & 2; /* keep System Reset type only */ } -- 1.8.1.2