* [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08
@ 2013-03-08 20:06 Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 01/66] pseries: Add cleanup hook for PAPR virtual LAN device Alexander Graf
` (66 more replies)
0 siblings, 67 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Aurélien Jarno
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 4421 bytes --]
Hi Blue / Aurelien,
This is my current patch queue for ppc. Please pull.
Alex
The following changes since commit 0bc472a9d6b80567c212023c5eae413f4dfb53ad:
Kuo-Jung Su (1):
hw/nand.c: correct the sense of the BUSY/READY status bit
are available in the git repository at:
git://github.com/agraf/qemu.git ppc-for-upstream
Amadeusz Sławiński (2):
PPC: Fix dma interrupt
PPC: xnu kernel expects FLUSH to be cleared on STOP
Andreas Färber (58):
target-ppc: Fix CPU_POWERPC_MPC8547E
target-ppc: Fix "G2leGP3" PVR
target-ppc: Update error handling in ppc_cpu_realize()
target-ppc: Drop nested TARGET_PPC64 guard for POWER7
target-ppc: Inline comma into POWERPC_DEF_SVR() macro
target-ppc: Extract aliases from definitions list
target-ppc: Make -cpu "ppc" an alias to "ppc32"
target-ppc: Extract MPC5xx aliases
target-ppc: Extract MGT823/MPC8xx as aliases
target-ppc: Extract 40x aliases
target-ppc: Extract 440 aliases
target-ppc: Turn "ppc32" and "ppc64" CPUs into aliases
target-ppc: Extract 74x7[A] aliases
target-ppc: Extract 74x5 as aliases
target-ppc: Extract 74x1 aliases
target-ppc: Extract 7450 alias
target-ppc: Extract 7448 alias
target-ppc: Extract 7410 alias
target-ppc: Extract 7400 alias
target-ppc: Extract 7x5 aliases
target-ppc: Extract 750 aliases
target-ppc: Extract 740/750 aliases
target-ppc: Extract 603e alias
target-ppc: Extract 603r alias
target-ppc: Extract 601/601v aliases
target-ppc: Extract 604e alias
target-ppc: Extract MPC85xx aliases
target-ppc: Extract e500v1/e500v2 aliases
target-ppc: Extract MPC83xx aliases
target-ppc: Extract e300 alias
target-ppc: Extract e200 alias
target-ppc: Extract MPC82xx alias
target-ppc: Extract MPC8247/MPC8248/MPC8270-80 aliases
target-ppc: Extract MPC82xx aliases to *_HiP4
target-ppc: Extract MPC82xx_HiP{3, 4} aliases
target-ppc: Extract MPC52xx alias
target-ppc: Extract MPC5200/MPC5200B aliases
target-ppc: Extract MPC8240 alias
target-ppc: Extract 405GPe alias
target-ppc: Extract 970 aliases
target-ppc: Extract POWER7 alias
target-ppc: Get model name from type name
target-ppc: Convert CPU definitions
target-ppc: Introduce abstract CPU family types
target-ppc: Set instruction flags on CPU family classes
target-ppc: Register all types for TARGET_PPCEMB
target-ppc: Set remaining fields on CPU family classes
target-ppc: Turn descriptive CPU family comments into device descriptions
target-ppc: Turn descriptive CPU model comments into device descriptions
target-ppc: Update Coding Style for CPU models
target-ppc: Split model definitions out of translate_init.c
target-ppc: Fix remaining microcontroller typos among models
target-ppc: Change "POWER7" CPU alias
target-ppc: Fix PPC_DUMP_SPR_ACCESS build
target-ppc: Make host CPU a subclass of the host's CPU model
target-ppc: List alias names alongside CPU models
target-ppc: Report CPU aliases for QMP
target-ppc: Move CPU aliases out of translate_init.c
David Gibson (4):
pseries: Add cleanup hook for PAPR virtual LAN device
target-ppc: Add mechanism for synchronizing SPRs with KVM
target-ppc: Synchronize FPU state with KVM
pseries: Add compatible property to root of device tree
Erlon Cruz (1):
pseries: Implement h_read hcall
Fabien Chouteau (1):
Save memory allocation in the elf loader
hw/elf_ops.h | 19 +-
hw/loader.c | 75 +-
hw/loader.h | 2 +
hw/mac_dbdma.c | 4 +
hw/ppc/mac_newworld.c | 2 +-
hw/spapr.c | 1 +
hw/spapr_hcall.c | 31 +
hw/spapr_llan.c | 8 +
target-ppc/Makefile.objs | 1 +
target-ppc/cpu-models.c | 1419 ++++++++++++
target-ppc/cpu-models.h | 741 ++++++
target-ppc/cpu-qom.h | 17 +-
target-ppc/cpu.h | 26 +-
target-ppc/kvm.c | 311 +++-
target-ppc/translate_init.c | 5275 +++++++++++++------------------------------
15 files changed, 4117 insertions(+), 3815 deletions(-)
create mode 100644 target-ppc/cpu-models.c
create mode 100644 target-ppc/cpu-models.h
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 01/66] pseries: Add cleanup hook for PAPR virtual LAN device
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 02/66] target-ppc: Fix CPU_POWERPC_MPC8547E Alexander Graf
` (65 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Aurélien Jarno,
David Gibson
From: David Gibson <david@gibson.dropbear.id.au>
Currently the spapr-vlan device does not supply a cleanup call for its
NetClientInfo structure. With current qemu versions, that leads to a SEGV
on exit, when net_cleanup() attempts to call the cleanup handlers on all
net clients.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/spapr_llan.c | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/hw/spapr_llan.c b/hw/spapr_llan.c
index 6ef2936..0ace2eb 100644
--- a/hw/spapr_llan.c
+++ b/hw/spapr_llan.c
@@ -175,11 +175,19 @@ static ssize_t spapr_vlan_receive(NetClientState *nc, const uint8_t *buf,
return size;
}
+static void spapr_vlan_cleanup(NetClientState *nc)
+{
+ VIOsPAPRVLANDevice *dev = qemu_get_nic_opaque(nc);
+
+ dev->nic = NULL;
+}
+
static NetClientInfo net_spapr_vlan_info = {
.type = NET_CLIENT_OPTIONS_KIND_NIC,
.size = sizeof(NICState),
.can_receive = spapr_vlan_can_receive,
.receive = spapr_vlan_receive,
+ .cleanup = spapr_vlan_cleanup,
};
static void spapr_vlan_reset(VIOsPAPRDevice *sdev)
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 02/66] target-ppc: Fix CPU_POWERPC_MPC8547E
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 01/66] pseries: Add cleanup hook for PAPR virtual LAN device Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 03/66] target-ppc: Fix "G2leGP3" PVR Alexander Graf
` (64 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
It was defined to ..._MPC8545E_v21 rather than ..._MPC8547E_v21.
Due to both resolving to CPU_POWERPC_e500v2_v21 this did not show.
Fixing this nontheless helps with QOM'ifying CPU aliases.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index f5fc9b1..a2e1fc9 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7282,7 +7282,7 @@ enum {
#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
+#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8547E_v21
#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 03/66] target-ppc: Fix "G2leGP3" PVR
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 01/66] pseries: Add cleanup hook for PAPR virtual LAN device Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 02/66] target-ppc: Fix CPU_POWERPC_MPC8547E Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 04/66] target-ppc: Update error handling in ppc_cpu_realize() Alexander Graf
` (63 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Unlike derived PVR constants mapped to CPU_POWERPC_G2LEgp3, the
"G2leGP3" model definition itself used the CPU_POWERPC_G2LEgp1 PVR.
Fixing this will allow to alias CPU_POWERPC_G2LEgp3-using types to
"G2leGP3".
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index a2e1fc9..d2706f7 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8243,7 +8243,7 @@ static const ppc_def_t ppc_defs[] = {
/* PowerPC G2LE GP1 core */
POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
/* PowerPC G2LE GP3 core */
- POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
+ POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2LE),
/* PowerPC MPC603 microcontrollers */
/* MPC8240 */
POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 04/66] target-ppc: Update error handling in ppc_cpu_realize()
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (2 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 03/66] target-ppc: Fix "G2leGP3" PVR Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 05/66] target-ppc: Drop nested TARGET_PPC64 guard for POWER7 Alexander Graf
` (62 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Commit fe828a4d4b7a5617cda7b24e95e327bfb71d790e added a new fatal error
message while QOM realize'ification was in flight.
Convert it to return an Error instead of exit()ing.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d2706f7..d00c737 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -10043,9 +10043,9 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
#if !defined(CONFIG_USER_ONLY)
if (smp_threads > max_smt) {
- fprintf(stderr, "Cannot support more than %d threads on PPC with %s\n",
- max_smt, kvm_enabled() ? "KVM" : "TCG");
- exit(1);
+ error_setg(errp, "Cannot support more than %d threads on PPC with %s",
+ max_smt, kvm_enabled() ? "KVM" : "TCG");
+ return;
}
#endif
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 05/66] target-ppc: Drop nested TARGET_PPC64 guard for POWER7
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (3 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 04/66] target-ppc: Update error handling in ppc_cpu_realize() Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 06/66] target-ppc: Inline comma into POWERPC_DEF_SVR() macro Alexander Graf
` (61 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
It is within a large TARGET_PPC64 section from 970 to 620,
so an #endif /* TARGET_PPC64 */ is confusing. Clean this up.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d00c737..98a64e1 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6671,7 +6671,6 @@ static void init_proc_970MP (CPUPPCState *env)
vscr_init(env, 0x00010000);
}
-#if defined(TARGET_PPC64)
/* POWER7 */
#define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -6755,7 +6754,6 @@ static void init_proc_POWER7 (CPUPPCState *env)
* value is the one used by 74xx processors. */
vscr_init(env, 0x00010000);
}
-#endif /* TARGET_PPC64 */
/* PowerPC 620 */
#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 06/66] target-ppc: Inline comma into POWERPC_DEF_SVR() macro
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (4 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 05/66] target-ppc: Drop nested TARGET_PPC64 guard for POWER7 Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 07/66] target-ppc: Extract aliases from definitions list Alexander Graf
` (60 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
To repurpose the POWERPC_DEF_SVR() macro outside of an array,
move the comma into the macro. No functional change.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 1206 +++++++++++++++++++++---------------------
1 files changed, 603 insertions(+), 603 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 98a64e1..3f75bef 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7714,7 +7714,7 @@ enum {
.flags = glue(POWERPC_FLAG_,_type), \
.init_proc = &glue(init_proc_,_type), \
.check_pow = &glue(check_pow_,_type), \
- }
+ },
#define POWERPC_DEF(_name, _pvr, _type) \
POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
@@ -7722,1621 +7722,1621 @@ static const ppc_def_t ppc_defs[] = {
/* Embedded PowerPC */
/* PowerPC 401 family */
/* Generic PowerPC 401 */
- POWERPC_DEF("401", CPU_POWERPC_401, 401),
+ POWERPC_DEF("401", CPU_POWERPC_401, 401)
/* PowerPC 401 cores */
/* PowerPC 401A1 */
- POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
+ POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401)
/* PowerPC 401B2 */
- POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
+ POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2)
#if defined (TODO)
/* PowerPC 401B3 */
- POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
+ POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3)
#endif
/* PowerPC 401C2 */
- POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
+ POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2)
/* PowerPC 401D2 */
- POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
+ POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2)
/* PowerPC 401E2 */
- POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
+ POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2)
/* PowerPC 401F2 */
- POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
+ POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2)
/* PowerPC 401G2 */
/* XXX: to be checked */
- POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
+ POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2)
/* PowerPC 401 microcontrolers */
#if defined (TODO)
/* PowerPC 401GF */
- POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
+ POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401)
#endif
/* IOP480 (401 microcontroler) */
- POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
+ POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480)
/* IBM Processor for Network Resources */
- POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
+ POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401)
#if defined (TODO)
- POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
+ POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401)
#endif
/* PowerPC 403 family */
/* Generic PowerPC 403 */
- POWERPC_DEF("403", CPU_POWERPC_403, 403),
+ POWERPC_DEF("403", CPU_POWERPC_403, 403)
/* PowerPC 403 microcontrolers */
/* PowerPC 403 GA */
- POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
+ POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403)
/* PowerPC 403 GB */
- POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
+ POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403)
/* PowerPC 403 GC */
- POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
+ POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403)
/* PowerPC 403 GCX */
- POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
+ POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX)
#if defined (TODO)
/* PowerPC 403 GP */
- POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
+ POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403)
#endif
/* PowerPC 405 family */
/* Generic PowerPC 405 */
- POWERPC_DEF("405", CPU_POWERPC_405, 405),
+ POWERPC_DEF("405", CPU_POWERPC_405, 405)
/* PowerPC 405 cores */
#if defined (TODO)
/* PowerPC 405 A3 */
- POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
+ POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405)
#endif
#if defined (TODO)
/* PowerPC 405 A4 */
- POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
+ POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405)
#endif
#if defined (TODO)
/* PowerPC 405 B3 */
- POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
+ POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405)
#endif
#if defined (TODO)
/* PowerPC 405 B4 */
- POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
+ POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405)
#endif
#if defined (TODO)
/* PowerPC 405 C3 */
- POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
+ POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405)
#endif
#if defined (TODO)
/* PowerPC 405 C4 */
- POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
+ POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405)
#endif
/* PowerPC 405 D2 */
- POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
+ POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405)
#if defined (TODO)
/* PowerPC 405 D3 */
- POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
+ POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405)
#endif
/* PowerPC 405 D4 */
- POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
+ POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405)
#if defined (TODO)
/* PowerPC 405 D5 */
- POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
+ POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405)
#endif
#if defined (TODO)
/* PowerPC 405 E4 */
- POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
+ POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405)
#endif
#if defined (TODO)
/* PowerPC 405 F4 */
- POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
+ POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405)
#endif
#if defined (TODO)
/* PowerPC 405 F5 */
- POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
+ POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405)
#endif
#if defined (TODO)
/* PowerPC 405 F6 */
- POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
+ POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405)
#endif
/* PowerPC 405 microcontrolers */
/* PowerPC 405 CR */
- POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
+ POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405)
/* PowerPC 405 CRa */
- POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
+ POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405)
/* PowerPC 405 CRb */
- POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
+ POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405)
/* PowerPC 405 CRc */
- POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
+ POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405)
/* PowerPC 405 EP */
- POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
+ POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405)
#if defined(TODO)
/* PowerPC 405 EXr */
- POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
+ POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405)
#endif
/* PowerPC 405 EZ */
- POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
+ POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405)
#if defined(TODO)
/* PowerPC 405 FX */
- POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
+ POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405)
#endif
/* PowerPC 405 GP */
- POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
+ POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405)
/* PowerPC 405 GPa */
- POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
+ POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405)
/* PowerPC 405 GPb */
- POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
+ POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405)
/* PowerPC 405 GPc */
- POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
+ POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405)
/* PowerPC 405 GPd */
- POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
+ POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405)
/* PowerPC 405 GPe */
- POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
+ POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405)
/* PowerPC 405 GPR */
- POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
+ POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405)
#if defined(TODO)
/* PowerPC 405 H */
- POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
+ POWERPC_DEF("405H", CPU_POWERPC_405H, 405)
#endif
#if defined(TODO)
/* PowerPC 405 L */
- POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
+ POWERPC_DEF("405L", CPU_POWERPC_405L, 405)
#endif
/* PowerPC 405 LP */
- POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
+ POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405)
#if defined(TODO)
/* PowerPC 405 PM */
- POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
+ POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405)
#endif
#if defined(TODO)
/* PowerPC 405 PS */
- POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
+ POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405)
#endif
#if defined(TODO)
/* PowerPC 405 S */
- POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
+ POWERPC_DEF("405S", CPU_POWERPC_405S, 405)
#endif
/* Npe405 H */
- POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
+ POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405)
/* Npe405 H2 */
- POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
+ POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405)
/* Npe405 L */
- POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
+ POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405)
/* Npe4GS3 */
- POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
+ POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405)
#if defined (TODO)
- POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
+ POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405)
#endif
#if defined (TODO)
- POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
+ POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405)
#endif
#if defined (TODO)
/* PowerPC LC77700 (Sanyo) */
- POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
+ POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405)
#endif
/* PowerPC 401/403/405 based set-top-box microcontrolers */
#if defined (TODO)
/* STB010000 */
- POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
+ POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2)
#endif
#if defined (TODO)
/* STB01010 */
- POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
+ POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2)
#endif
#if defined (TODO)
/* STB0210 */
- POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
+ POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3)
#endif
/* STB03xx */
- POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
+ POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405)
#if defined (TODO)
/* STB043x */
- POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
+ POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405)
#endif
#if defined (TODO)
/* STB045x */
- POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
+ POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405)
#endif
/* STB04xx */
- POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
+ POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405)
/* STB25xx */
- POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
+ POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405)
#if defined (TODO)
/* STB130 */
- POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
+ POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405)
#endif
/* Xilinx PowerPC 405 cores */
- POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
- POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
- POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
- POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
+ POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405)
+ POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405)
+ POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405)
+ POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405)
#if defined (TODO)
/* Zarlink ZL10310 */
- POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
+ POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405)
#endif
#if defined (TODO)
/* Zarlink ZL10311 */
- POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
+ POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405)
#endif
#if defined (TODO)
/* Zarlink ZL10320 */
- POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
+ POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405)
#endif
#if defined (TODO)
/* Zarlink ZL10321 */
- POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
+ POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405)
#endif
/* PowerPC 440 family */
#if defined(TODO_USER_ONLY)
/* Generic PowerPC 440 */
- POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
+ POWERPC_DEF("440", CPU_POWERPC_440, 440GP)
#endif
/* PowerPC 440 cores */
#if defined (TODO)
/* PowerPC 440 A4 */
- POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
+ POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4)
#endif
/* PowerPC 440 Xilinx 5 */
- POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
+ POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5)
#if defined (TODO)
/* PowerPC 440 A5 */
- POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
+ POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5)
#endif
#if defined (TODO)
/* PowerPC 440 B4 */
- POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
+ POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4)
#endif
#if defined (TODO)
/* PowerPC 440 G4 */
- POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
+ POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4)
#endif
#if defined (TODO)
/* PowerPC 440 F5 */
- POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
+ POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5)
#endif
#if defined (TODO)
/* PowerPC 440 G5 */
- POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
+ POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5)
#endif
#if defined (TODO)
/* PowerPC 440H4 */
- POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
+ POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4)
#endif
#if defined (TODO)
/* PowerPC 440H6 */
- POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
+ POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5)
#endif
/* PowerPC 440 microcontrolers */
/* PowerPC 440 EP */
- POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
+ POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP)
/* PowerPC 440 EPa */
- POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
+ POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP)
/* PowerPC 440 EPb */
- POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
+ POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP)
/* PowerPC 440 EPX */
- POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
+ POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP)
#if defined(TODO_USER_ONLY)
/* PowerPC 440 GP */
- POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
+ POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP)
#endif
#if defined(TODO_USER_ONLY)
/* PowerPC 440 GPb */
- POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
+ POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP)
#endif
#if defined(TODO_USER_ONLY)
/* PowerPC 440 GPc */
- POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
+ POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP)
#endif
#if defined(TODO_USER_ONLY)
/* PowerPC 440 GR */
- POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
+ POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5)
#endif
#if defined(TODO_USER_ONLY)
/* PowerPC 440 GRa */
- POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
+ POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5)
#endif
#if defined(TODO_USER_ONLY)
/* PowerPC 440 GRX */
- POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
+ POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5)
#endif
#if defined(TODO_USER_ONLY)
/* PowerPC 440 GX */
- POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
+ POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP)
#endif
#if defined(TODO_USER_ONLY)
/* PowerPC 440 GXa */
- POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
+ POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP)
#endif
#if defined(TODO_USER_ONLY)
/* PowerPC 440 GXb */
- POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
+ POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP)
#endif
#if defined(TODO_USER_ONLY)
/* PowerPC 440 GXc */
- POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
+ POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP)
#endif
#if defined(TODO_USER_ONLY)
/* PowerPC 440 GXf */
- POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
+ POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP)
#endif
#if defined(TODO)
/* PowerPC 440 S */
- POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
+ POWERPC_DEF("440S", CPU_POWERPC_440S, 440)
#endif
#if defined(TODO_USER_ONLY)
/* PowerPC 440 SP */
- POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
+ POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP)
#endif
#if defined(TODO_USER_ONLY)
/* PowerPC 440 SP2 */
- POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
+ POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP)
#endif
#if defined(TODO_USER_ONLY)
/* PowerPC 440 SPE */
- POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
+ POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP)
#endif
/* PowerPC 460 family */
#if defined (TODO)
/* Generic PowerPC 464 */
- POWERPC_DEF("464", CPU_POWERPC_464, 460),
+ POWERPC_DEF("464", CPU_POWERPC_464, 460)
#endif
/* PowerPC 464 microcontrolers */
#if defined (TODO)
/* PowerPC 464H90 */
- POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
+ POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460)
#endif
#if defined (TODO)
/* PowerPC 464H90F */
- POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
+ POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F)
#endif
/* Freescale embedded PowerPC cores */
/* MPC5xx family (aka RCPU) */
#if defined(TODO_USER_ONLY)
/* Generic MPC5xx core */
- POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
+ POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx)
#endif
#if defined(TODO_USER_ONLY)
/* Codename for MPC5xx core */
- POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
+ POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx)
#endif
/* MPC5xx microcontrollers */
#if defined(TODO_USER_ONLY)
/* MGT560 */
- POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
+ POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC509 */
- POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
+ POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC533 */
- POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
+ POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC534 */
- POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
+ POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC555 */
- POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
+ POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC556 */
- POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
+ POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC560 */
- POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
+ POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC561 */
- POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
+ POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC562 */
- POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
+ POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC563 */
- POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
+ POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC564 */
- POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
+ POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC565 */
- POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
+ POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC566 */
- POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
+ POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx)
#endif
/* MPC8xx family (aka PowerQUICC) */
#if defined(TODO_USER_ONLY)
/* Generic MPC8xx core */
- POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
+ POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* Codename for MPC8xx core */
- POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
+ POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx)
#endif
/* MPC8xx microcontrollers */
#if defined(TODO_USER_ONLY)
/* MGT823 */
- POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
+ POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC821 */
- POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
+ POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC823 */
- POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
+ POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC850 */
- POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
+ POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC852T */
- POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
+ POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC855T */
- POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
+ POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC857 */
- POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
+ POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC859 */
- POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
+ POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC860 */
- POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
+ POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC862 */
- POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
+ POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC866 */
- POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
+ POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC870 */
- POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
+ POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC875 */
- POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
+ POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC880 */
- POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
+ POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx)
#endif
#if defined(TODO_USER_ONLY)
/* MPC885 */
- POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
+ POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx)
#endif
/* MPC82xx family (aka PowerQUICC-II) */
/* Generic MPC52xx core */
POWERPC_DEF_SVR("MPC52xx",
- CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
+ CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE)
/* Generic MPC82xx core */
- POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
+ POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2)
/* Codename for MPC82xx */
- POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
+ POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2)
/* PowerPC G2 core */
- POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
+ POWERPC_DEF("G2", CPU_POWERPC_G2, G2)
/* PowerPC G2 H4 core */
- POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
+ POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2)
/* PowerPC G2 GP core */
- POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
+ POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2)
/* PowerPC G2 LS core */
- POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
+ POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2)
/* PowerPC G2 HiP3 core */
- POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
+ POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2)
/* PowerPC G2 HiP4 core */
- POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
+ POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2)
/* PowerPC MPC603 core */
- POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
+ POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E)
/* PowerPC G2le core (same as G2 plus little-endian mode support) */
- POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
+ POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE)
/* PowerPC G2LE GP core */
- POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
+ POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE)
/* PowerPC G2LE LS core */
- POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
+ POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE)
/* PowerPC G2LE GP1 core */
- POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
+ POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE)
/* PowerPC G2LE GP3 core */
- POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2LE),
+ POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2LE)
/* PowerPC MPC603 microcontrollers */
/* MPC8240 */
- POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
+ POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E)
/* PowerPC G2 microcontrollers */
#if defined(TODO)
/* MPC5121 */
POWERPC_DEF_SVR("MPC5121",
- CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
+ CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE)
#endif
/* MPC5200 */
POWERPC_DEF_SVR("MPC5200",
- CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
+ CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE)
/* MPC5200 v1.0 */
POWERPC_DEF_SVR("MPC5200_v10",
- CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
+ CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE)
/* MPC5200 v1.1 */
POWERPC_DEF_SVR("MPC5200_v11",
- CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
+ CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE)
/* MPC5200 v1.2 */
POWERPC_DEF_SVR("MPC5200_v12",
- CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
+ CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE)
/* MPC5200B */
POWERPC_DEF_SVR("MPC5200B",
- CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
+ CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE)
/* MPC5200B v2.0 */
POWERPC_DEF_SVR("MPC5200B_v20",
- CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
+ CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
/* MPC5200B v2.1 */
POWERPC_DEF_SVR("MPC5200B_v21",
- CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
+ CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
/* MPC8241 */
- POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
+ POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2)
/* MPC8245 */
- POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
+ POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2)
/* MPC8247 */
- POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
+ POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE)
/* MPC8248 */
- POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
+ POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE)
/* MPC8250 */
- POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
+ POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2)
/* MPC8250 HiP3 */
- POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
+ POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2)
/* MPC8250 HiP4 */
- POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
+ POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2)
/* MPC8255 */
- POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
+ POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2)
/* MPC8255 HiP3 */
- POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
+ POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2)
/* MPC8255 HiP4 */
- POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
+ POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2)
/* MPC8260 */
- POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
+ POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2)
/* MPC8260 HiP3 */
- POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
+ POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2)
/* MPC8260 HiP4 */
- POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
+ POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2)
/* MPC8264 */
- POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
+ POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2)
/* MPC8264 HiP3 */
- POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
+ POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2)
/* MPC8264 HiP4 */
- POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
+ POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2)
/* MPC8265 */
- POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
+ POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2)
/* MPC8265 HiP3 */
- POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
+ POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2)
/* MPC8265 HiP4 */
- POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
+ POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2)
/* MPC8266 */
- POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
+ POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2)
/* MPC8266 HiP3 */
- POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
+ POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2)
/* MPC8266 HiP4 */
- POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
+ POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2)
/* MPC8270 */
- POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
+ POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE)
/* MPC8271 */
- POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
+ POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE)
/* MPC8272 */
- POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
+ POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE)
/* MPC8275 */
- POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
+ POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE)
/* MPC8280 */
- POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
+ POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE)
/* e200 family */
/* Generic PowerPC e200 core */
- POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
+ POWERPC_DEF("e200", CPU_POWERPC_e200, e200)
/* Generic MPC55xx core */
#if defined (TODO)
POWERPC_DEF_SVR("MPC55xx",
- CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
+ CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200)
#endif
#if defined (TODO)
/* PowerPC e200z0 core */
- POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
+ POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200)
#endif
#if defined (TODO)
/* PowerPC e200z1 core */
- POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
+ POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200)
#endif
#if defined (TODO)
/* PowerPC e200z3 core */
- POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
+ POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200)
#endif
/* PowerPC e200z5 core */
- POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
+ POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200)
/* PowerPC e200z6 core */
- POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
+ POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200)
/* PowerPC e200 microcontrollers */
#if defined (TODO)
/* MPC5514E */
POWERPC_DEF_SVR("MPC5514E",
- CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
+ CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200)
#endif
#if defined (TODO)
/* MPC5514E v0 */
POWERPC_DEF_SVR("MPC5514E_v0",
- CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
+ CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200)
#endif
#if defined (TODO)
/* MPC5514E v1 */
POWERPC_DEF_SVR("MPC5514E_v1",
- CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
+ CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200)
#endif
#if defined (TODO)
/* MPC5514G */
POWERPC_DEF_SVR("MPC5514G",
- CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
+ CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200)
#endif
#if defined (TODO)
/* MPC5514G v0 */
POWERPC_DEF_SVR("MPC5514G_v0",
- CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
+ CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200)
#endif
#if defined (TODO)
/* MPC5514G v1 */
POWERPC_DEF_SVR("MPC5514G_v1",
- CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
+ CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200)
#endif
#if defined (TODO)
/* MPC5515S */
POWERPC_DEF_SVR("MPC5515S",
- CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
+ CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200)
#endif
#if defined (TODO)
/* MPC5516E */
POWERPC_DEF_SVR("MPC5516E",
- CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
+ CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200)
#endif
#if defined (TODO)
/* MPC5516E v0 */
POWERPC_DEF_SVR("MPC5516E_v0",
- CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
+ CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200)
#endif
#if defined (TODO)
/* MPC5516E v1 */
POWERPC_DEF_SVR("MPC5516E_v1",
- CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
+ CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200)
#endif
#if defined (TODO)
/* MPC5516G */
POWERPC_DEF_SVR("MPC5516G",
- CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
+ CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200)
#endif
#if defined (TODO)
/* MPC5516G v0 */
POWERPC_DEF_SVR("MPC5516G_v0",
- CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
+ CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200)
#endif
#if defined (TODO)
/* MPC5516G v1 */
POWERPC_DEF_SVR("MPC5516G_v1",
- CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
+ CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200)
#endif
#if defined (TODO)
/* MPC5516S */
POWERPC_DEF_SVR("MPC5516S",
- CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
+ CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200)
#endif
#if defined (TODO)
/* MPC5533 */
POWERPC_DEF_SVR("MPC5533",
- CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
+ CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200)
#endif
#if defined (TODO)
/* MPC5534 */
POWERPC_DEF_SVR("MPC5534",
- CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
+ CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200)
#endif
#if defined (TODO)
/* MPC5553 */
POWERPC_DEF_SVR("MPC5553",
- CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
+ CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200)
#endif
#if defined (TODO)
/* MPC5554 */
POWERPC_DEF_SVR("MPC5554",
- CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
+ CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200)
#endif
#if defined (TODO)
/* MPC5561 */
POWERPC_DEF_SVR("MPC5561",
- CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
+ CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200)
#endif
#if defined (TODO)
/* MPC5565 */
POWERPC_DEF_SVR("MPC5565",
- CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
+ CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200)
#endif
#if defined (TODO)
/* MPC5566 */
POWERPC_DEF_SVR("MPC5566",
- CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
+ CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200)
#endif
#if defined (TODO)
/* MPC5567 */
POWERPC_DEF_SVR("MPC5567",
- CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
+ CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200)
#endif
/* e300 family */
/* Generic PowerPC e300 core */
- POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
+ POWERPC_DEF("e300", CPU_POWERPC_e300, e300)
/* PowerPC e300c1 core */
- POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
+ POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300)
/* PowerPC e300c2 core */
- POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
+ POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300)
/* PowerPC e300c3 core */
- POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
+ POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300)
/* PowerPC e300c4 core */
- POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
+ POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300)
/* PowerPC e300 microcontrollers */
#if defined (TODO)
/* MPC8313 */
POWERPC_DEF_SVR("MPC8313",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300)
#endif
#if defined (TODO)
/* MPC8313E */
POWERPC_DEF_SVR("MPC8313E",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300)
#endif
#if defined (TODO)
/* MPC8314 */
POWERPC_DEF_SVR("MPC8314",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300)
#endif
#if defined (TODO)
/* MPC8314E */
POWERPC_DEF_SVR("MPC8314E",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300)
#endif
#if defined (TODO)
/* MPC8315 */
POWERPC_DEF_SVR("MPC8315",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300)
#endif
#if defined (TODO)
/* MPC8315E */
POWERPC_DEF_SVR("MPC8315E",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300)
#endif
#if defined (TODO)
/* MPC8321 */
POWERPC_DEF_SVR("MPC8321",
- CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
+ CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300)
#endif
#if defined (TODO)
/* MPC8321E */
POWERPC_DEF_SVR("MPC8321E",
- CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
+ CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300)
#endif
#if defined (TODO)
/* MPC8323 */
POWERPC_DEF_SVR("MPC8323",
- CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
+ CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300)
#endif
#if defined (TODO)
/* MPC8323E */
POWERPC_DEF_SVR("MPC8323E",
- CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
+ CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300)
#endif
/* MPC8343 */
POWERPC_DEF_SVR("MPC8343",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300)
/* MPC8343A */
POWERPC_DEF_SVR("MPC8343A",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300)
/* MPC8343E */
POWERPC_DEF_SVR("MPC8343E",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300)
/* MPC8343EA */
POWERPC_DEF_SVR("MPC8343EA",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300)
/* MPC8347 */
POWERPC_DEF_SVR("MPC8347",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300)
/* MPC8347T */
POWERPC_DEF_SVR("MPC8347T",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300)
/* MPC8347P */
POWERPC_DEF_SVR("MPC8347P",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300)
/* MPC8347A */
POWERPC_DEF_SVR("MPC8347A",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300)
/* MPC8347AT */
POWERPC_DEF_SVR("MPC8347AT",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300)
/* MPC8347AP */
POWERPC_DEF_SVR("MPC8347AP",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300)
/* MPC8347E */
POWERPC_DEF_SVR("MPC8347E",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300)
/* MPC8347ET */
POWERPC_DEF_SVR("MPC8347ET",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300)
/* MPC8343EP */
POWERPC_DEF_SVR("MPC8347EP",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300)
/* MPC8347EA */
POWERPC_DEF_SVR("MPC8347EA",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300)
/* MPC8347EAT */
POWERPC_DEF_SVR("MPC8347EAT",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300)
/* MPC8343EAP */
POWERPC_DEF_SVR("MPC8347EAP",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300)
/* MPC8349 */
POWERPC_DEF_SVR("MPC8349",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300)
/* MPC8349A */
POWERPC_DEF_SVR("MPC8349A",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300)
/* MPC8349E */
POWERPC_DEF_SVR("MPC8349E",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300)
/* MPC8349EA */
POWERPC_DEF_SVR("MPC8349EA",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300)
#if defined (TODO)
/* MPC8358E */
POWERPC_DEF_SVR("MPC8358E",
- CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
+ CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300)
#endif
#if defined (TODO)
/* MPC8360E */
POWERPC_DEF_SVR("MPC8360E",
- CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
+ CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300)
#endif
/* MPC8377 */
POWERPC_DEF_SVR("MPC8377",
- CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300)
/* MPC8377E */
POWERPC_DEF_SVR("MPC8377E",
- CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300)
/* MPC8378 */
POWERPC_DEF_SVR("MPC8378",
- CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300)
/* MPC8378E */
POWERPC_DEF_SVR("MPC8378E",
- CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300)
/* MPC8379 */
POWERPC_DEF_SVR("MPC8379",
- CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300)
/* MPC8379E */
POWERPC_DEF_SVR("MPC8379E",
- CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300)
/* e500 family */
/* PowerPC e500 core */
- POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
+ POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2)
/* PowerPC e500v1 core */
- POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
+ POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1)
/* PowerPC e500 v1.0 core */
- POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
+ POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1)
/* PowerPC e500 v2.0 core */
- POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
+ POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1)
/* PowerPC e500v2 core */
- POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
+ POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2)
/* PowerPC e500v2 v1.0 core */
- POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
+ POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2)
/* PowerPC e500v2 v2.0 core */
- POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
+ POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2)
/* PowerPC e500v2 v2.1 core */
- POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
+ POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2)
/* PowerPC e500v2 v2.2 core */
- POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
+ POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2)
/* PowerPC e500v2 v3.0 core */
- POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
- POWERPC_DEF_SVR("e500mc", CPU_POWERPC_e500mc, POWERPC_SVR_E500, e500mc),
+ POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2)
+ POWERPC_DEF_SVR("e500mc", CPU_POWERPC_e500mc, POWERPC_SVR_E500, e500mc)
#ifdef TARGET_PPC64
- POWERPC_DEF_SVR("e5500", CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500),
+ POWERPC_DEF_SVR("e5500", CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500)
#endif
/* PowerPC e500 microcontrollers */
/* MPC8533 */
POWERPC_DEF_SVR("MPC8533",
- CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
+ CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2)
/* MPC8533 v1.0 */
POWERPC_DEF_SVR("MPC8533_v10",
- CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
+ CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2)
/* MPC8533 v1.1 */
POWERPC_DEF_SVR("MPC8533_v11",
- CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
+ CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2)
/* MPC8533E */
POWERPC_DEF_SVR("MPC8533E",
- CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
+ CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2)
/* MPC8533E v1.0 */
POWERPC_DEF_SVR("MPC8533E_v10",
- CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
+ CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2)
POWERPC_DEF_SVR("MPC8533E_v11",
- CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
+ CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2)
/* MPC8540 */
POWERPC_DEF_SVR("MPC8540",
- CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
+ CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1)
/* MPC8540 v1.0 */
POWERPC_DEF_SVR("MPC8540_v10",
- CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
+ CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1)
/* MPC8540 v2.0 */
POWERPC_DEF_SVR("MPC8540_v20",
- CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
+ CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1)
/* MPC8540 v2.1 */
POWERPC_DEF_SVR("MPC8540_v21",
- CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
+ CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1)
/* MPC8541 */
POWERPC_DEF_SVR("MPC8541",
- CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
+ CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1)
/* MPC8541 v1.0 */
POWERPC_DEF_SVR("MPC8541_v10",
- CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
+ CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1)
/* MPC8541 v1.1 */
POWERPC_DEF_SVR("MPC8541_v11",
- CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
+ CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1)
/* MPC8541E */
POWERPC_DEF_SVR("MPC8541E",
- CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
+ CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1)
/* MPC8541E v1.0 */
POWERPC_DEF_SVR("MPC8541E_v10",
- CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
+ CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1)
/* MPC8541E v1.1 */
POWERPC_DEF_SVR("MPC8541E_v11",
- CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
+ CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1)
/* MPC8543 */
POWERPC_DEF_SVR("MPC8543",
- CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
+ CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2)
/* MPC8543 v1.0 */
POWERPC_DEF_SVR("MPC8543_v10",
- CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
+ CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2)
/* MPC8543 v1.1 */
POWERPC_DEF_SVR("MPC8543_v11",
- CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
+ CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2)
/* MPC8543 v2.0 */
POWERPC_DEF_SVR("MPC8543_v20",
- CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
+ CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2)
/* MPC8543 v2.1 */
POWERPC_DEF_SVR("MPC8543_v21",
- CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
+ CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2)
/* MPC8543E */
POWERPC_DEF_SVR("MPC8543E",
- CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
+ CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2)
/* MPC8543E v1.0 */
POWERPC_DEF_SVR("MPC8543E_v10",
- CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
+ CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2)
/* MPC8543E v1.1 */
POWERPC_DEF_SVR("MPC8543E_v11",
- CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
+ CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2)
/* MPC8543E v2.0 */
POWERPC_DEF_SVR("MPC8543E_v20",
- CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
+ CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2)
/* MPC8543E v2.1 */
POWERPC_DEF_SVR("MPC8543E_v21",
- CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
+ CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2)
/* MPC8544 */
POWERPC_DEF_SVR("MPC8544",
- CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
+ CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2)
/* MPC8544 v1.0 */
POWERPC_DEF_SVR("MPC8544_v10",
- CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
+ CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2)
/* MPC8544 v1.1 */
POWERPC_DEF_SVR("MPC8544_v11",
- CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
+ CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2)
/* MPC8544E */
POWERPC_DEF_SVR("MPC8544E",
- CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
+ CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2)
/* MPC8544E v1.0 */
POWERPC_DEF_SVR("MPC8544E_v10",
- CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
+ CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2)
/* MPC8544E v1.1 */
POWERPC_DEF_SVR("MPC8544E_v11",
- CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
+ CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2)
/* MPC8545 */
POWERPC_DEF_SVR("MPC8545",
- CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
+ CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2)
/* MPC8545 v2.0 */
POWERPC_DEF_SVR("MPC8545_v20",
- CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
+ CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2)
/* MPC8545 v2.1 */
POWERPC_DEF_SVR("MPC8545_v21",
- CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
+ CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2)
/* MPC8545E */
POWERPC_DEF_SVR("MPC8545E",
- CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
+ CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2)
/* MPC8545E v2.0 */
POWERPC_DEF_SVR("MPC8545E_v20",
- CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
+ CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2)
/* MPC8545E v2.1 */
POWERPC_DEF_SVR("MPC8545E_v21",
- CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
+ CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2)
/* MPC8547E */
POWERPC_DEF_SVR("MPC8547E",
- CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
+ CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2)
/* MPC8547E v2.0 */
POWERPC_DEF_SVR("MPC8547E_v20",
- CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
+ CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2)
/* MPC8547E v2.1 */
POWERPC_DEF_SVR("MPC8547E_v21",
- CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
+ CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2)
/* MPC8548 */
POWERPC_DEF_SVR("MPC8548",
- CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
+ CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2)
/* MPC8548 v1.0 */
POWERPC_DEF_SVR("MPC8548_v10",
- CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
+ CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2)
/* MPC8548 v1.1 */
POWERPC_DEF_SVR("MPC8548_v11",
- CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
+ CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2)
/* MPC8548 v2.0 */
POWERPC_DEF_SVR("MPC8548_v20",
- CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
+ CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2)
/* MPC8548 v2.1 */
POWERPC_DEF_SVR("MPC8548_v21",
- CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
+ CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2)
/* MPC8548E */
POWERPC_DEF_SVR("MPC8548E",
- CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
+ CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2)
/* MPC8548E v1.0 */
POWERPC_DEF_SVR("MPC8548E_v10",
- CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
+ CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2)
/* MPC8548E v1.1 */
POWERPC_DEF_SVR("MPC8548E_v11",
- CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
+ CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2)
/* MPC8548E v2.0 */
POWERPC_DEF_SVR("MPC8548E_v20",
- CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
+ CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2)
/* MPC8548E v2.1 */
POWERPC_DEF_SVR("MPC8548E_v21",
- CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
+ CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2)
/* MPC8555 */
POWERPC_DEF_SVR("MPC8555",
- CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
+ CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2)
/* MPC8555 v1.0 */
POWERPC_DEF_SVR("MPC8555_v10",
- CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
+ CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2)
/* MPC8555 v1.1 */
POWERPC_DEF_SVR("MPC8555_v11",
- CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
+ CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2)
/* MPC8555E */
POWERPC_DEF_SVR("MPC8555E",
- CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
+ CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2)
/* MPC8555E v1.0 */
POWERPC_DEF_SVR("MPC8555E_v10",
- CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
+ CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2)
/* MPC8555E v1.1 */
POWERPC_DEF_SVR("MPC8555E_v11",
- CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
+ CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2)
/* MPC8560 */
POWERPC_DEF_SVR("MPC8560",
- CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
+ CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2)
/* MPC8560 v1.0 */
POWERPC_DEF_SVR("MPC8560_v10",
- CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
+ CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2)
/* MPC8560 v2.0 */
POWERPC_DEF_SVR("MPC8560_v20",
- CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
+ CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2)
/* MPC8560 v2.1 */
POWERPC_DEF_SVR("MPC8560_v21",
- CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
+ CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2)
/* MPC8567 */
POWERPC_DEF_SVR("MPC8567",
- CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
+ CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2)
/* MPC8567E */
POWERPC_DEF_SVR("MPC8567E",
- CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
+ CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2)
/* MPC8568 */
POWERPC_DEF_SVR("MPC8568",
- CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
+ CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2)
/* MPC8568E */
POWERPC_DEF_SVR("MPC8568E",
- CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
+ CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2)
/* MPC8572 */
POWERPC_DEF_SVR("MPC8572",
- CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
+ CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2)
/* MPC8572E */
POWERPC_DEF_SVR("MPC8572E",
- CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
+ CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2)
/* e600 family */
/* PowerPC e600 core */
- POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
+ POWERPC_DEF("e600", CPU_POWERPC_e600, 7400)
/* PowerPC e600 microcontrollers */
#if defined (TODO)
/* MPC8610 */
POWERPC_DEF_SVR("MPC8610",
- CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
+ CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400)
#endif
/* MPC8641 */
POWERPC_DEF_SVR("MPC8641",
- CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
+ CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400)
/* MPC8641D */
POWERPC_DEF_SVR("MPC8641D",
- CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
+ CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400)
/* 32 bits "classic" PowerPC */
/* PowerPC 6xx family */
/* PowerPC 601 */
- POWERPC_DEF("601", CPU_POWERPC_601, 601v),
+ POWERPC_DEF("601", CPU_POWERPC_601, 601v)
/* PowerPC 601v0 */
- POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
+ POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601)
/* PowerPC 601v1 */
- POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
+ POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601)
/* PowerPC 601v */
- POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
+ POWERPC_DEF("601v", CPU_POWERPC_601v, 601v)
/* PowerPC 601v2 */
- POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
+ POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v)
/* PowerPC 602 */
- POWERPC_DEF("602", CPU_POWERPC_602, 602),
+ POWERPC_DEF("602", CPU_POWERPC_602, 602)
/* PowerPC 603 */
- POWERPC_DEF("603", CPU_POWERPC_603, 603),
+ POWERPC_DEF("603", CPU_POWERPC_603, 603)
/* Code name for PowerPC 603 */
- POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
+ POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603)
/* PowerPC 603e (aka PID6) */
- POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
+ POWERPC_DEF("603e", CPU_POWERPC_603E, 603E)
/* Code name for PowerPC 603e */
- POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
+ POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E)
/* PowerPC 603e v1.1 */
- POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
+ POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E)
/* PowerPC 603e v1.2 */
- POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
+ POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E)
/* PowerPC 603e v1.3 */
- POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
+ POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E)
/* PowerPC 603e v1.4 */
- POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
+ POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E)
/* PowerPC 603e v2.2 */
- POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
+ POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E)
/* PowerPC 603e v3 */
- POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
+ POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E)
/* PowerPC 603e v4 */
- POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
+ POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E)
/* PowerPC 603e v4.1 */
- POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
+ POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E)
/* PowerPC 603e (aka PID7) */
- POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
+ POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E)
/* PowerPC 603e7t */
- POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
+ POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E)
/* PowerPC 603e7v */
- POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
+ POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E)
/* Code name for PowerPC 603ev */
- POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
+ POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E)
/* PowerPC 603e7v1 */
- POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
+ POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E)
/* PowerPC 603e7v2 */
- POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
+ POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E)
/* PowerPC 603p (aka PID7v) */
- POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
+ POWERPC_DEF("603p", CPU_POWERPC_603P, 603E)
/* PowerPC 603r (aka PID7t) */
- POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
+ POWERPC_DEF("603r", CPU_POWERPC_603R, 603E)
/* Code name for PowerPC 603r */
- POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
+ POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E)
/* PowerPC 604 */
- POWERPC_DEF("604", CPU_POWERPC_604, 604),
+ POWERPC_DEF("604", CPU_POWERPC_604, 604)
/* PowerPC 604e (aka PID9) */
- POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
+ POWERPC_DEF("604e", CPU_POWERPC_604E, 604E)
/* Code name for PowerPC 604e */
- POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
+ POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E)
/* PowerPC 604e v1.0 */
- POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
+ POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E)
/* PowerPC 604e v2.2 */
- POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
+ POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E)
/* PowerPC 604e v2.4 */
- POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
+ POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E)
/* PowerPC 604r (aka PIDA) */
- POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
+ POWERPC_DEF("604r", CPU_POWERPC_604R, 604E)
/* Code name for PowerPC 604r */
- POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
+ POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E)
#if defined(TODO)
/* PowerPC 604ev */
- POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
+ POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E)
#endif
/* PowerPC 7xx family */
/* Generic PowerPC 740 (G3) */
- POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
+ POWERPC_DEF("740", CPU_POWERPC_7x0, 740)
/* Code name for PowerPC 740 */
- POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
+ POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740)
/* Generic PowerPC 750 (G3) */
- POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
+ POWERPC_DEF("750", CPU_POWERPC_7x0, 750)
/* Code name for PowerPC 750 */
- POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
+ POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750)
/* PowerPC 740/750 is also known as G3 */
- POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
+ POWERPC_DEF("G3", CPU_POWERPC_7x0, 750)
/* PowerPC 740 v1.0 (G3) */
- POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
+ POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740)
/* PowerPC 750 v1.0 (G3) */
- POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
+ POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750)
/* PowerPC 740 v2.0 (G3) */
- POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
+ POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740)
/* PowerPC 750 v2.0 (G3) */
- POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
+ POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750)
/* PowerPC 740 v2.1 (G3) */
- POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
+ POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740)
/* PowerPC 750 v2.1 (G3) */
- POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
+ POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750)
/* PowerPC 740 v2.2 (G3) */
- POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
+ POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740)
/* PowerPC 750 v2.2 (G3) */
- POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
+ POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750)
/* PowerPC 740 v3.0 (G3) */
- POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
+ POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740)
/* PowerPC 750 v3.0 (G3) */
- POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
+ POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750)
/* PowerPC 740 v3.1 (G3) */
- POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
+ POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740)
/* PowerPC 750 v3.1 (G3) */
- POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
+ POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750)
/* PowerPC 740E (G3) */
- POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
+ POWERPC_DEF("740e", CPU_POWERPC_740E, 740)
/* PowerPC 750E (G3) */
- POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
+ POWERPC_DEF("750e", CPU_POWERPC_750E, 750)
/* PowerPC 740P (G3) */
- POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
+ POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740)
/* PowerPC 750P (G3) */
- POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
+ POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750)
/* Code name for PowerPC 740P/750P (G3) */
- POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
+ POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750)
/* PowerPC 750CL (G3 embedded) */
- POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
+ POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl)
/* PowerPC 750CL v1.0 */
- POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
+ POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl)
/* PowerPC 750CL v2.0 */
- POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
+ POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl)
/* PowerPC 750CX (G3 embedded) */
- POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
+ POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx)
/* PowerPC 750CX v1.0 (G3 embedded) */
- POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
+ POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx)
/* PowerPC 750CX v2.1 (G3 embedded) */
- POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
+ POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx)
/* PowerPC 750CX v2.1 (G3 embedded) */
- POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
+ POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx)
/* PowerPC 750CX v2.2 (G3 embedded) */
- POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
+ POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx)
/* PowerPC 750CXe (G3 embedded) */
- POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
+ POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx)
/* PowerPC 750CXe v2.1 (G3 embedded) */
- POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
+ POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx)
/* PowerPC 750CXe v2.2 (G3 embedded) */
- POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
+ POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx)
/* PowerPC 750CXe v2.3 (G3 embedded) */
- POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
+ POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx)
/* PowerPC 750CXe v2.4 (G3 embedded) */
- POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
+ POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx)
/* PowerPC 750CXe v2.4b (G3 embedded) */
- POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
+ POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx)
/* PowerPC 750CXe v3.0 (G3 embedded) */
- POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
+ POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx)
/* PowerPC 750CXe v3.1 (G3 embedded) */
- POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
+ POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx)
/* PowerPC 750CXe v3.1b (G3 embedded) */
- POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
+ POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx)
/* PowerPC 750CXr (G3 embedded) */
- POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
+ POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx)
/* PowerPC 750FL (G3 embedded) */
- POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
+ POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx)
/* PowerPC 750FX (G3 embedded) */
- POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
+ POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx)
/* PowerPC 750FX v1.0 (G3 embedded) */
- POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
+ POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx)
/* PowerPC 750FX v2.0 (G3 embedded) */
- POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
+ POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx)
/* PowerPC 750FX v2.1 (G3 embedded) */
- POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
+ POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx)
/* PowerPC 750FX v2.2 (G3 embedded) */
- POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
+ POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx)
/* PowerPC 750FX v2.3 (G3 embedded) */
- POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
+ POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx)
/* PowerPC 750GL (G3 embedded) */
- POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
+ POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx)
/* PowerPC 750GX (G3 embedded) */
- POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
+ POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx)
/* PowerPC 750GX v1.0 (G3 embedded) */
- POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
+ POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx)
/* PowerPC 750GX v1.1 (G3 embedded) */
- POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
+ POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx)
/* PowerPC 750GX v1.2 (G3 embedded) */
- POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
+ POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx)
/* PowerPC 750L (G3 embedded) */
- POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
+ POWERPC_DEF("750l", CPU_POWERPC_750L, 750)
/* Code name for PowerPC 750L (G3 embedded) */
- POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
+ POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750)
/* PowerPC 750L v2.0 (G3 embedded) */
- POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
+ POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750)
/* PowerPC 750L v2.1 (G3 embedded) */
- POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
+ POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750)
/* PowerPC 750L v2.2 (G3 embedded) */
- POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
+ POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750)
/* PowerPC 750L v3.0 (G3 embedded) */
- POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
+ POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750)
/* PowerPC 750L v3.2 (G3 embedded) */
- POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
+ POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750)
/* Generic PowerPC 745 */
- POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
+ POWERPC_DEF("745", CPU_POWERPC_7x5, 745)
/* Generic PowerPC 755 */
- POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
+ POWERPC_DEF("755", CPU_POWERPC_7x5, 755)
/* Code name for PowerPC 745/755 */
- POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
+ POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755)
/* PowerPC 745 v1.0 */
- POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
+ POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745)
/* PowerPC 755 v1.0 */
- POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
+ POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755)
/* PowerPC 745 v1.1 */
- POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
+ POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745)
/* PowerPC 755 v1.1 */
- POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
+ POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755)
/* PowerPC 745 v2.0 */
- POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
+ POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745)
/* PowerPC 755 v2.0 */
- POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
+ POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755)
/* PowerPC 745 v2.1 */
- POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
+ POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745)
/* PowerPC 755 v2.1 */
- POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
+ POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755)
/* PowerPC 745 v2.2 */
- POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
+ POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745)
/* PowerPC 755 v2.2 */
- POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
+ POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755)
/* PowerPC 745 v2.3 */
- POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
+ POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745)
/* PowerPC 755 v2.3 */
- POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
+ POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755)
/* PowerPC 745 v2.4 */
- POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
+ POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745)
/* PowerPC 755 v2.4 */
- POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
+ POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755)
/* PowerPC 745 v2.5 */
- POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
+ POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745)
/* PowerPC 755 v2.5 */
- POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
+ POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755)
/* PowerPC 745 v2.6 */
- POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
+ POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745)
/* PowerPC 755 v2.6 */
- POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
+ POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755)
/* PowerPC 745 v2.7 */
- POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
+ POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745)
/* PowerPC 755 v2.7 */
- POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
+ POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755)
/* PowerPC 745 v2.8 */
- POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
+ POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745)
/* PowerPC 755 v2.8 */
- POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
+ POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755)
#if defined (TODO)
/* PowerPC 745P (G3) */
- POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
+ POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745)
/* PowerPC 755P (G3) */
- POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
+ POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755)
#endif
/* PowerPC 74xx family */
/* PowerPC 7400 (G4) */
- POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
+ POWERPC_DEF("7400", CPU_POWERPC_7400, 7400)
/* Code name for PowerPC 7400 */
- POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
+ POWERPC_DEF("Max", CPU_POWERPC_7400, 7400)
/* PowerPC 74xx is also well known as G4 */
- POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
+ POWERPC_DEF("G4", CPU_POWERPC_7400, 7400)
/* PowerPC 7400 v1.0 (G4) */
- POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
+ POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400)
/* PowerPC 7400 v1.1 (G4) */
- POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
+ POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400)
/* PowerPC 7400 v2.0 (G4) */
- POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
+ POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400)
/* PowerPC 7400 v2.1 (G4) */
- POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
+ POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400)
/* PowerPC 7400 v2.2 (G4) */
- POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
+ POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400)
/* PowerPC 7400 v2.6 (G4) */
- POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
+ POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400)
/* PowerPC 7400 v2.7 (G4) */
- POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
+ POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400)
/* PowerPC 7400 v2.8 (G4) */
- POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
+ POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400)
/* PowerPC 7400 v2.9 (G4) */
- POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
+ POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400)
/* PowerPC 7410 (G4) */
- POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
+ POWERPC_DEF("7410", CPU_POWERPC_7410, 7410)
/* Code name for PowerPC 7410 */
- POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
+ POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410)
/* PowerPC 7410 v1.0 (G4) */
- POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
+ POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410)
/* PowerPC 7410 v1.1 (G4) */
- POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
+ POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410)
/* PowerPC 7410 v1.2 (G4) */
- POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
+ POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410)
/* PowerPC 7410 v1.3 (G4) */
- POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
+ POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410)
/* PowerPC 7410 v1.4 (G4) */
- POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
+ POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410)
/* PowerPC 7448 (G4) */
- POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
+ POWERPC_DEF("7448", CPU_POWERPC_7448, 7400)
/* PowerPC 7448 v1.0 (G4) */
- POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
+ POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400)
/* PowerPC 7448 v1.1 (G4) */
- POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
+ POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400)
/* PowerPC 7448 v2.0 (G4) */
- POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
+ POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400)
/* PowerPC 7448 v2.1 (G4) */
- POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
+ POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400)
/* PowerPC 7450 (G4) */
- POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
+ POWERPC_DEF("7450", CPU_POWERPC_7450, 7450)
/* Code name for PowerPC 7450 */
- POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
+ POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450)
/* PowerPC 7450 v1.0 (G4) */
- POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
+ POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450)
/* PowerPC 7450 v1.1 (G4) */
- POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
+ POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450)
/* PowerPC 7450 v1.2 (G4) */
- POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
+ POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450)
/* PowerPC 7450 v2.0 (G4) */
- POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
+ POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450)
/* PowerPC 7450 v2.1 (G4) */
- POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
+ POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450)
/* PowerPC 7441 (G4) */
- POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
+ POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440)
/* PowerPC 7451 (G4) */
- POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
+ POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450)
/* PowerPC 7441 v2.1 (G4) */
- POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
+ POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440)
/* PowerPC 7441 v2.3 (G4) */
- POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
+ POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440)
/* PowerPC 7451 v2.3 (G4) */
- POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
+ POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450)
/* PowerPC 7441 v2.10 (G4) */
- POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
+ POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440)
/* PowerPC 7451 v2.10 (G4) */
- POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
+ POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450)
/* PowerPC 7445 (G4) */
- POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
+ POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445)
/* PowerPC 7455 (G4) */
- POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
+ POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455)
/* Code name for PowerPC 7445/7455 */
- POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
+ POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455)
/* PowerPC 7445 v1.0 (G4) */
- POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
+ POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445)
/* PowerPC 7455 v1.0 (G4) */
- POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
+ POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455)
/* PowerPC 7445 v2.1 (G4) */
- POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
+ POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445)
/* PowerPC 7455 v2.1 (G4) */
- POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
+ POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455)
/* PowerPC 7445 v3.2 (G4) */
- POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
+ POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445)
/* PowerPC 7455 v3.2 (G4) */
- POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
+ POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455)
/* PowerPC 7445 v3.3 (G4) */
- POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
+ POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445)
/* PowerPC 7455 v3.3 (G4) */
- POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
+ POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455)
/* PowerPC 7445 v3.4 (G4) */
- POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
+ POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445)
/* PowerPC 7455 v3.4 (G4) */
- POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
+ POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455)
/* PowerPC 7447 (G4) */
- POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
+ POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445)
/* PowerPC 7457 (G4) */
- POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
+ POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455)
/* Code name for PowerPC 7447/7457 */
- POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
+ POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455)
/* PowerPC 7447 v1.0 (G4) */
- POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
+ POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445)
/* PowerPC 7457 v1.0 (G4) */
- POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
+ POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455)
/* PowerPC 7447 v1.1 (G4) */
- POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
+ POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445)
/* PowerPC 7457 v1.1 (G4) */
- POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
+ POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455)
/* PowerPC 7457 v1.2 (G4) */
- POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
+ POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455)
/* PowerPC 7447A (G4) */
- POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
+ POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445)
/* PowerPC 7457A (G4) */
- POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
+ POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455)
/* PowerPC 7447A v1.0 (G4) */
- POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
+ POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445)
/* PowerPC 7457A v1.0 (G4) */
- POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
+ POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455)
/* Code name for PowerPC 7447A/7457A */
- POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
+ POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455)
/* PowerPC 7447A v1.1 (G4) */
- POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
+ POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445)
/* PowerPC 7457A v1.1 (G4) */
- POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
+ POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455)
/* PowerPC 7447A v1.2 (G4) */
- POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
+ POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445)
/* PowerPC 7457A v1.2 (G4) */
- POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
+ POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455)
/* 64 bits PowerPC */
#if defined (TARGET_PPC64)
/* PowerPC 620 */
- POWERPC_DEF("620", CPU_POWERPC_620, 620),
+ POWERPC_DEF("620", CPU_POWERPC_620, 620)
/* Code name for PowerPC 620 */
- POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
+ POWERPC_DEF("Trident", CPU_POWERPC_620, 620)
#if defined (TODO)
/* PowerPC 630 (POWER3) */
- POWERPC_DEF("630", CPU_POWERPC_630, 630),
- POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
+ POWERPC_DEF("630", CPU_POWERPC_630, 630)
+ POWERPC_DEF("POWER3", CPU_POWERPC_630, 630)
/* Code names for POWER3 */
- POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
- POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
+ POWERPC_DEF("Boxer", CPU_POWERPC_630, 630)
+ POWERPC_DEF("Dino", CPU_POWERPC_630, 630)
#endif
#if defined (TODO)
/* PowerPC 631 (Power 3+) */
- POWERPC_DEF("631", CPU_POWERPC_631, 631),
- POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
+ POWERPC_DEF("631", CPU_POWERPC_631, 631)
+ POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631)
#endif
#if defined (TODO)
/* POWER4 */
- POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
+ POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4)
#endif
#if defined (TODO)
/* POWER4p */
- POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
+ POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P)
#endif
#if defined (TODO)
/* POWER5 */
- POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
+ POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5)
/* POWER5GR */
- POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
+ POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5)
#endif
#if defined (TODO)
/* POWER5+ */
- POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
+ POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P)
/* POWER5GS */
- POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
+ POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P)
#endif
#if defined (TODO)
/* POWER6 */
- POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
+ POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6)
/* POWER6 running in POWER5 mode */
- POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
+ POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5)
/* POWER6A */
- POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
+ POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6)
#endif
/* POWER7 */
- POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
- POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
- POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7),
- POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7),
+ POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7)
+ POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7)
+ POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7)
+ POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7)
/* PowerPC 970 */
- POWERPC_DEF("970", CPU_POWERPC_970, 970),
+ POWERPC_DEF("970", CPU_POWERPC_970, 970)
/* PowerPC 970FX (G5) */
- POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
+ POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX)
/* PowerPC 970FX v1.0 (G5) */
- POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
+ POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX)
/* PowerPC 970FX v2.0 (G5) */
- POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
+ POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX)
/* PowerPC 970FX v2.1 (G5) */
- POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
+ POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX)
/* PowerPC 970FX v3.0 (G5) */
- POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
+ POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX)
/* PowerPC 970FX v3.1 (G5) */
- POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
+ POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX)
/* PowerPC 970GX (G5) */
- POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
+ POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX)
/* PowerPC 970MP */
- POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
+ POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP)
/* PowerPC 970MP v1.0 */
- POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
+ POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP)
/* PowerPC 970MP v1.1 */
- POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
+ POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP)
#if defined (TODO)
/* PowerPC Cell */
- POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
+ POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970)
#endif
#if defined (TODO)
/* PowerPC Cell v1.0 */
- POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
+ POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970)
#endif
#if defined (TODO)
/* PowerPC Cell v2.0 */
- POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
+ POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970)
#endif
#if defined (TODO)
/* PowerPC Cell v3.0 */
- POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
+ POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970)
#endif
#if defined (TODO)
/* PowerPC Cell v3.1 */
- POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
+ POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970)
#endif
#if defined (TODO)
/* PowerPC Cell v3.2 */
- POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
+ POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970)
#endif
#if defined (TODO)
/* RS64 (Apache/A35) */
@@ -9344,57 +9344,57 @@ static const ppc_def_t ppc_defs[] = {
* and the PowerPC 64 one.
*/
/* What about A10 & A30 ? */
- POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
- POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
- POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
+ POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64)
+ POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64)
+ POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64)
#endif
#if defined (TODO)
/* RS64-II (NorthStar/A50) */
- POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
- POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
- POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
+ POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64)
+ POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64)
+ POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64)
#endif
#if defined (TODO)
/* RS64-III (Pulsar) */
- POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
- POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
+ POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64)
+ POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64)
#endif
#if defined (TODO)
/* RS64-IV (IceStar/IStar/SStar) */
- POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
- POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
- POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
- POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
+ POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64)
+ POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64)
+ POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64)
+ POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64)
#endif
#endif /* defined (TARGET_PPC64) */
/* POWER */
#if defined (TODO)
/* Original POWER */
- POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
- POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
- POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
- POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
- POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
+ POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER)
+ POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER)
+ POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER)
+ POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER)
+ POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER)
#endif
#if defined (TODO)
/* POWER2 */
- POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
- POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
- POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
+ POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER)
+ POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER)
+ POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER)
#endif
/* PA semi cores */
#if defined (TODO)
/* PA PA6T */
- POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
+ POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T)
#endif
/* Generic PowerPCs */
#if defined (TARGET_PPC64)
- POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
+ POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64)
#endif
- POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
- POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
+ POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32)
+ POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT)
/* Fallback */
- POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
+ POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT)
};
/*****************************************************************************/
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 07/66] target-ppc: Extract aliases from definitions list
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (5 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 06/66] target-ppc: Inline comma into POWERPC_DEF_SVR() macro Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 08/66] target-ppc: Make -cpu "ppc" an alias to "ppc32" Alexander Graf
` (59 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Move definitions that were 100% identical except for the name into a
list of aliases so that we don't register duplicate CPU types.
Drop the accompanying comments since they don't really add value.
We need to support recursive lookup due to code names referencing a
generic name referencing a specific model revision.
List aliases separately for -cpu ?.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 145 +++++++++++++++++++++----------------------
1 files changed, 72 insertions(+), 73 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3f75bef..862f40a 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8083,10 +8083,6 @@ static const ppc_def_t ppc_defs[] = {
/* Generic MPC5xx core */
POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx)
#endif
-#if defined(TODO_USER_ONLY)
- /* Codename for MPC5xx core */
- POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx)
-#endif
/* MPC5xx microcontrollers */
#if defined(TODO_USER_ONLY)
/* MGT560 */
@@ -8145,10 +8141,6 @@ static const ppc_def_t ppc_defs[] = {
/* Generic MPC8xx core */
POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx)
#endif
-#if defined(TODO_USER_ONLY)
- /* Codename for MPC8xx core */
- POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx)
-#endif
/* MPC8xx microcontrollers */
#if defined(TODO_USER_ONLY)
/* MGT823 */
@@ -8216,8 +8208,6 @@ static const ppc_def_t ppc_defs[] = {
CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE)
/* Generic MPC82xx core */
POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2)
- /* Codename for MPC82xx */
- POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2)
/* PowerPC G2 core */
POWERPC_DEF("G2", CPU_POWERPC_G2, G2)
/* PowerPC G2 H4 core */
@@ -8612,8 +8602,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF_SVR("MPC8379E",
CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300)
/* e500 family */
- /* PowerPC e500 core */
- POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2)
/* PowerPC e500v1 core */
POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1)
/* PowerPC e500 v1.0 core */
@@ -8868,12 +8856,8 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("602", CPU_POWERPC_602, 602)
/* PowerPC 603 */
POWERPC_DEF("603", CPU_POWERPC_603, 603)
- /* Code name for PowerPC 603 */
- POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603)
/* PowerPC 603e (aka PID6) */
POWERPC_DEF("603e", CPU_POWERPC_603E, 603E)
- /* Code name for PowerPC 603e */
- POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E)
/* PowerPC 603e v1.1 */
POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E)
/* PowerPC 603e v1.2 */
@@ -8896,8 +8880,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E)
/* PowerPC 603e7v */
POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E)
- /* Code name for PowerPC 603ev */
- POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E)
/* PowerPC 603e7v1 */
POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E)
/* PowerPC 603e7v2 */
@@ -8906,14 +8888,10 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("603p", CPU_POWERPC_603P, 603E)
/* PowerPC 603r (aka PID7t) */
POWERPC_DEF("603r", CPU_POWERPC_603R, 603E)
- /* Code name for PowerPC 603r */
- POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E)
/* PowerPC 604 */
POWERPC_DEF("604", CPU_POWERPC_604, 604)
/* PowerPC 604e (aka PID9) */
POWERPC_DEF("604e", CPU_POWERPC_604E, 604E)
- /* Code name for PowerPC 604e */
- POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E)
/* PowerPC 604e v1.0 */
POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E)
/* PowerPC 604e v2.2 */
@@ -8922,8 +8900,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E)
/* PowerPC 604r (aka PIDA) */
POWERPC_DEF("604r", CPU_POWERPC_604R, 604E)
- /* Code name for PowerPC 604r */
- POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E)
#if defined(TODO)
/* PowerPC 604ev */
POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E)
@@ -8931,14 +8907,8 @@ static const ppc_def_t ppc_defs[] = {
/* PowerPC 7xx family */
/* Generic PowerPC 740 (G3) */
POWERPC_DEF("740", CPU_POWERPC_7x0, 740)
- /* Code name for PowerPC 740 */
- POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740)
/* Generic PowerPC 750 (G3) */
POWERPC_DEF("750", CPU_POWERPC_7x0, 750)
- /* Code name for PowerPC 750 */
- POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750)
- /* PowerPC 740/750 is also known as G3 */
- POWERPC_DEF("G3", CPU_POWERPC_7x0, 750)
/* PowerPC 740 v1.0 (G3) */
POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740)
/* PowerPC 750 v1.0 (G3) */
@@ -8971,8 +8941,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740)
/* PowerPC 750P (G3) */
POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750)
- /* Code name for PowerPC 740P/750P (G3) */
- POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750)
/* PowerPC 750CL (G3 embedded) */
POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl)
/* PowerPC 750CL v1.0 */
@@ -9035,8 +9003,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx)
/* PowerPC 750L (G3 embedded) */
POWERPC_DEF("750l", CPU_POWERPC_750L, 750)
- /* Code name for PowerPC 750L (G3 embedded) */
- POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750)
/* PowerPC 750L v2.0 (G3 embedded) */
POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750)
/* PowerPC 750L v2.1 (G3 embedded) */
@@ -9051,8 +9017,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("745", CPU_POWERPC_7x5, 745)
/* Generic PowerPC 755 */
POWERPC_DEF("755", CPU_POWERPC_7x5, 755)
- /* Code name for PowerPC 745/755 */
- POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755)
/* PowerPC 745 v1.0 */
POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745)
/* PowerPC 755 v1.0 */
@@ -9106,10 +9070,6 @@ static const ppc_def_t ppc_defs[] = {
/* PowerPC 74xx family */
/* PowerPC 7400 (G4) */
POWERPC_DEF("7400", CPU_POWERPC_7400, 7400)
- /* Code name for PowerPC 7400 */
- POWERPC_DEF("Max", CPU_POWERPC_7400, 7400)
- /* PowerPC 74xx is also well known as G4 */
- POWERPC_DEF("G4", CPU_POWERPC_7400, 7400)
/* PowerPC 7400 v1.0 (G4) */
POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400)
/* PowerPC 7400 v1.1 (G4) */
@@ -9130,8 +9090,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400)
/* PowerPC 7410 (G4) */
POWERPC_DEF("7410", CPU_POWERPC_7410, 7410)
- /* Code name for PowerPC 7410 */
- POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410)
/* PowerPC 7410 v1.0 (G4) */
POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410)
/* PowerPC 7410 v1.1 (G4) */
@@ -9154,8 +9112,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400)
/* PowerPC 7450 (G4) */
POWERPC_DEF("7450", CPU_POWERPC_7450, 7450)
- /* Code name for PowerPC 7450 */
- POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450)
/* PowerPC 7450 v1.0 (G4) */
POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450)
/* PowerPC 7450 v1.1 (G4) */
@@ -9184,8 +9140,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445)
/* PowerPC 7455 (G4) */
POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455)
- /* Code name for PowerPC 7445/7455 */
- POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455)
/* PowerPC 7445 v1.0 (G4) */
POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445)
/* PowerPC 7455 v1.0 (G4) */
@@ -9210,8 +9164,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445)
/* PowerPC 7457 (G4) */
POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455)
- /* Code name for PowerPC 7447/7457 */
- POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455)
/* PowerPC 7447 v1.0 (G4) */
POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445)
/* PowerPC 7457 v1.0 (G4) */
@@ -9230,8 +9182,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445)
/* PowerPC 7457A v1.0 (G4) */
POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455)
- /* Code name for PowerPC 7447A/7457A */
- POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455)
/* PowerPC 7447A v1.1 (G4) */
POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445)
/* PowerPC 7457A v1.1 (G4) */
@@ -9244,20 +9194,13 @@ static const ppc_def_t ppc_defs[] = {
#if defined (TARGET_PPC64)
/* PowerPC 620 */
POWERPC_DEF("620", CPU_POWERPC_620, 620)
- /* Code name for PowerPC 620 */
- POWERPC_DEF("Trident", CPU_POWERPC_620, 620)
#if defined (TODO)
/* PowerPC 630 (POWER3) */
POWERPC_DEF("630", CPU_POWERPC_630, 630)
- POWERPC_DEF("POWER3", CPU_POWERPC_630, 630)
- /* Code names for POWER3 */
- POWERPC_DEF("Boxer", CPU_POWERPC_630, 630)
- POWERPC_DEF("Dino", CPU_POWERPC_630, 630)
#endif
#if defined (TODO)
/* PowerPC 631 (Power 3+) */
POWERPC_DEF("631", CPU_POWERPC_631, 631)
- POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631)
#endif
#if defined (TODO)
/* POWER4 */
@@ -9345,42 +9288,28 @@ static const ppc_def_t ppc_defs[] = {
*/
/* What about A10 & A30 ? */
POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64)
- POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64)
- POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64)
#endif
#if defined (TODO)
/* RS64-II (NorthStar/A50) */
POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64)
- POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64)
- POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64)
#endif
#if defined (TODO)
/* RS64-III (Pulsar) */
POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64)
- POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64)
#endif
#if defined (TODO)
/* RS64-IV (IceStar/IStar/SStar) */
POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64)
- POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64)
- POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64)
- POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64)
#endif
#endif /* defined (TARGET_PPC64) */
/* POWER */
#if defined (TODO)
/* Original POWER */
POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER)
- POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER)
- POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER)
- POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER)
- POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER)
#endif
#if defined (TODO)
/* POWER2 */
POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER)
- POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER)
- POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER)
#endif
/* PA semi cores */
#if defined (TODO)
@@ -9393,8 +9322,60 @@ static const ppc_def_t ppc_defs[] = {
#endif
POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32)
POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT)
- /* Fallback */
- POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT)
+};
+
+typedef struct PowerPCCPUAlias {
+ const char *alias;
+ const char *model;
+} PowerPCCPUAlias;
+
+static const PowerPCCPUAlias ppc_cpu_aliases[] = {
+ { "RCPU", "MPC5xx" },
+ { "PowerQUICC", "MPC8xx" },
+ { "PowerQUICC-II", "MPC82xx" },
+ { "e500", "e500v2_v22" },
+ { "Vanilla", "603" },
+ { "Stretch", "603e" },
+ { "Vaillant", "603e7v" },
+ { "Goldeneye", "603r" },
+ { "Sirocco", "604e" },
+ { "Mach5", "604r" },
+ { "Arthur", "740" },
+ { "Typhoon", "750" },
+ { "G3", "750" },
+ { "Conan/Doyle", "750p" },
+ { "LoneStar", "750l" },
+ { "Goldfinger", "755" },
+ { "Max", "7400" },
+ { "G4", "7400" },
+ { "Nitro", "7410" },
+ { "Vger", "7450" },
+ { "Apollo6", "7455" },
+ { "Apollo7", "7457" },
+ { "Apollo7PM", "7457A_v1.0" },
+#if defined(TARGET_PPC64)
+ { "Trident", "620" },
+ { "POWER3", "630" },
+ { "Boxer", "POWER3" },
+ { "Dino", "POWER3" },
+ { "POWER3+", "631" },
+ { "Apache", "RS64" },
+ { "A35", "RS64" },
+ { "NorthStar", "RS64-II" },
+ { "A50", "RS64-II" },
+ { "Pulsar", "RS64-III" },
+ { "IceStar", "RS64-IV" },
+ { "IStar", "RS64-IV" },
+ { "SStar", "RS64-IV" },
+#endif
+ { "RIOS", "POWER" },
+ { "RSC", "POWER" },
+ { "RSC3308", "POWER" },
+ { "RSC4608", "POWER" },
+ { "RSC2", "POWER2" },
+ { "P2SC", "POWER2" },
+
+ { "default", "ppc" },
};
/*****************************************************************************/
@@ -10323,6 +10304,12 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name)
}
}
+ for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
+ if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
+ return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
+ }
+ }
+
list = object_class_get_list(TYPE_POWERPC_CPU, false);
item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
if (item != NULL) {
@@ -10403,11 +10390,23 @@ void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
.cpu_fprintf = cpu_fprintf,
};
GSList *list;
+ int i;
list = object_class_get_list(TYPE_POWERPC_CPU, false);
list = g_slist_sort(list, ppc_cpu_list_compare);
g_slist_foreach(list, ppc_cpu_list_entry, &s);
g_slist_free(list);
+
+ cpu_fprintf(f, "\n");
+ for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
+ ObjectClass *oc = ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
+ if (oc == NULL) {
+ /* Hide aliases that point to a TODO or TODO_USER_ONLY model */
+ continue;
+ }
+ cpu_fprintf(f, "PowerPC %-16s\n",
+ ppc_cpu_aliases[i].alias);
+ }
}
static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 08/66] target-ppc: Make -cpu "ppc" an alias to "ppc32"
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (6 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 07/66] target-ppc: Extract aliases from definitions list Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 09/66] target-ppc: Extract MPC5xx aliases Alexander Graf
` (58 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Drop the #if 0'ed alternative to make it "ppc64" for TARGET_PPC64.
If we ever want to change it, we can more easily do so now.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 29 +----------------------------
1 files changed, 1 insertions(+), 28 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 862f40a..8923105 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6824,33 +6824,6 @@ static void init_proc_620 (CPUPPCState *env)
#define check_pow_PPC64 check_pow_970FX
#define init_proc_PPC64 init_proc_970FX
-/* Default PowerPC target will be PowerPC 32 */
-#if defined (TARGET_PPC64) && 0 // XXX: TODO
-#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
-#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
-#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC64
-#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
-#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
-#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
-#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
-#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
-#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
-#define check_pow_DEFAULT check_pow_PPC64
-#define init_proc_DEFAULT init_proc_PPC64
-#else
-#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
-#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
-#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC32
-#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
-#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
-#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
-#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
-#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
-#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
-#define check_pow_DEFAULT check_pow_PPC32
-#define init_proc_DEFAULT init_proc_PPC32
-#endif
-
/*****************************************************************************/
/* PVR definitions for most known PowerPC */
enum {
@@ -9321,7 +9294,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64)
#endif
POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32)
- POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT)
};
typedef struct PowerPCCPUAlias {
@@ -9375,6 +9347,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "RSC2", "POWER2" },
{ "P2SC", "POWER2" },
+ { "ppc", "ppc32" },
{ "default", "ppc" },
};
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 09/66] target-ppc: Extract MPC5xx aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (7 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 08/66] target-ppc: Make -cpu "ppc" an alias to "ppc32" Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 10/66] target-ppc: Extract MGT823/MPC8xx as aliases Alexander Graf
` (57 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Their PVR differed but was defined to MPC5xx.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 81 ++++++++-----------------------------------
1 files changed, 15 insertions(+), 66 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 8923105..6a5f7e8 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7057,19 +7057,6 @@ enum {
/* Freescale embedded PowerPC cores */
/* PowerPC MPC 5xx cores (aka RCPU) */
CPU_POWERPC_MPC5xx = 0x00020020,
-#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
-#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
-#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
-#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
-#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
-#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
-#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
-#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
-#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
-#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
-#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
-#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
-#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
/* PowerPC MPC 8xx cores (aka PowerQUICC) */
CPU_POWERPC_MPC8xx = 0x00500000,
#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
@@ -8056,59 +8043,6 @@ static const ppc_def_t ppc_defs[] = {
/* Generic MPC5xx core */
POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx)
#endif
- /* MPC5xx microcontrollers */
-#if defined(TODO_USER_ONLY)
- /* MGT560 */
- POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC509 */
- POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC533 */
- POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC534 */
- POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC555 */
- POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC556 */
- POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC560 */
- POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC561 */
- POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC562 */
- POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC563 */
- POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC564 */
- POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC565 */
- POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC566 */
- POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx)
-#endif
/* MPC8xx family (aka PowerQUICC) */
#if defined(TODO_USER_ONLY)
/* Generic MPC8xx core */
@@ -9303,6 +9237,21 @@ typedef struct PowerPCCPUAlias {
static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "RCPU", "MPC5xx" },
+ /* MPC5xx microcontrollers */
+ { "MGT560", "MPC5xx" },
+ { "MPC509", "MPC5xx" },
+ { "MPC533", "MPC5xx" },
+ { "MPC534", "MPC5xx" },
+ { "MPC555", "MPC5xx" },
+ { "MPC556", "MPC5xx" },
+ { "MPC560", "MPC5xx" },
+ { "MPC561", "MPC5xx" },
+ { "MPC562", "MPC5xx" },
+ { "MPC563", "MPC5xx" },
+ { "MPC564", "MPC5xx" },
+ { "MPC565", "MPC5xx" },
+ { "MPC566", "MPC5xx" },
+
{ "PowerQUICC", "MPC8xx" },
{ "PowerQUICC-II", "MPC82xx" },
{ "e500", "e500v2_v22" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 10/66] target-ppc: Extract MGT823/MPC8xx as aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (8 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 09/66] target-ppc: Extract MPC5xx aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 11/66] target-ppc: Extract 40x aliases Alexander Graf
` (56 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
They used different PVRs but were defined to MPC8xx.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 93 ++++++++-----------------------------------
1 files changed, 17 insertions(+), 76 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6a5f7e8..6a86e10 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7059,21 +7059,6 @@ enum {
CPU_POWERPC_MPC5xx = 0x00020020,
/* PowerPC MPC 8xx cores (aka PowerQUICC) */
CPU_POWERPC_MPC8xx = 0x00500000,
-#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
-#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
/* G2 cores (aka PowerQUICC-II) */
CPU_POWERPC_G2 = 0x00810011,
CPU_POWERPC_G2H4 = 0x80811010,
@@ -8048,67 +8033,6 @@ static const ppc_def_t ppc_defs[] = {
/* Generic MPC8xx core */
POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx)
#endif
- /* MPC8xx microcontrollers */
-#if defined(TODO_USER_ONLY)
- /* MGT823 */
- POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC821 */
- POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC823 */
- POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC850 */
- POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC852T */
- POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC855T */
- POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC857 */
- POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC859 */
- POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC860 */
- POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC862 */
- POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC866 */
- POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC870 */
- POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC875 */
- POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC880 */
- POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx)
-#endif
-#if defined(TODO_USER_ONLY)
- /* MPC885 */
- POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx)
-#endif
/* MPC82xx family (aka PowerQUICC-II) */
/* Generic MPC52xx core */
POWERPC_DEF_SVR("MPC52xx",
@@ -9253,6 +9177,23 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "MPC566", "MPC5xx" },
{ "PowerQUICC", "MPC8xx" },
+ /* MPC8xx microcontrollers */
+ { "MGT823", "MPC8xx" },
+ { "MPC821", "MPC8xx" },
+ { "MPC823", "MPC8xx" },
+ { "MPC850", "MPC8xx" },
+ { "MPC852T", "MPC8xx" },
+ { "MPC855T", "MPC8xx" },
+ { "MPC857", "MPC8xx" },
+ { "MPC859", "MPC8xx" },
+ { "MPC860", "MPC8xx" },
+ { "MPC862", "MPC8xx" },
+ { "MPC866", "MPC8xx" },
+ { "MPC870", "MPC8xx" },
+ { "MPC875", "MPC8xx" },
+ { "MPC880", "MPC8xx" },
+ { "MPC885", "MPC8xx" },
+
{ "PowerQUICC-II", "MPC82xx" },
{ "e500", "e500v2_v22" },
{ "Vanilla", "603" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 11/66] target-ppc: Extract 40x aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (9 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 10/66] target-ppc: Extract MGT823/MPC8xx as aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 12/66] target-ppc: Extract 440 aliases Alexander Graf
` (55 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 25 +++++++------------------
1 files changed, 7 insertions(+), 18 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6a86e10..8a3cf9f 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6852,8 +6852,6 @@ enum {
CPU_POWERPC_XIPCHIP = xxx,
#endif
/* PowerPC 403 family */
- /* Generic PowerPC 403 */
-#define CPU_POWERPC_403 CPU_POWERPC_403GC
/* PowerPC 403 microcontrollers */
CPU_POWERPC_403GA = 0x00200011,
CPU_POWERPC_403GB = 0x00200100,
@@ -6863,8 +6861,6 @@ enum {
CPU_POWERPC_403GP = xxx,
#endif
/* PowerPC 405 family */
- /* Generic PowerPC 405 */
-#define CPU_POWERPC_405 CPU_POWERPC_405D4
/* PowerPC 405 cores */
#if 0
CPU_POWERPC_405A3 = xxx,
@@ -6906,7 +6902,6 @@ enum {
#endif
/* PowerPC 405 microcontrolers */
/* XXX: missing 0x200108a0 */
-#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
CPU_POWERPC_405CRa = 0x40110041,
CPU_POWERPC_405CRb = 0x401100C5,
CPU_POWERPC_405CRc = 0x40110145,
@@ -6918,7 +6913,6 @@ enum {
#if 0
CPU_POWERPC_405FX = xxx,
#endif
-#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
CPU_POWERPC_405GPa = 0x40110000,
CPU_POWERPC_405GPb = 0x40110040,
CPU_POWERPC_405GPc = 0x40110082,
@@ -6979,9 +6973,7 @@ enum {
#endif
/* Xilinx cores */
CPU_POWERPC_X2VP4 = 0x20010820,
-#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
CPU_POWERPC_X2VP20 = 0x20010860,
-#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
#if 0
CPU_POWERPC_ZL10310 = xxx,
#endif
@@ -7701,8 +7693,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401)
#endif
/* PowerPC 403 family */
- /* Generic PowerPC 403 */
- POWERPC_DEF("403", CPU_POWERPC_403, 403)
/* PowerPC 403 microcontrolers */
/* PowerPC 403 GA */
POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403)
@@ -7717,8 +7707,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403)
#endif
/* PowerPC 405 family */
- /* Generic PowerPC 405 */
- POWERPC_DEF("405", CPU_POWERPC_405, 405)
/* PowerPC 405 cores */
#if defined (TODO)
/* PowerPC 405 A3 */
@@ -7773,8 +7761,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405)
#endif
/* PowerPC 405 microcontrolers */
- /* PowerPC 405 CR */
- POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405)
/* PowerPC 405 CRa */
POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405)
/* PowerPC 405 CRb */
@@ -7793,8 +7779,6 @@ static const ppc_def_t ppc_defs[] = {
/* PowerPC 405 FX */
POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405)
#endif
- /* PowerPC 405 GP */
- POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405)
/* PowerPC 405 GPa */
POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405)
/* PowerPC 405 GPb */
@@ -7880,9 +7864,7 @@ static const ppc_def_t ppc_defs[] = {
#endif
/* Xilinx PowerPC 405 cores */
POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405)
- POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405)
POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405)
- POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405)
#if defined (TODO)
/* Zarlink ZL10310 */
POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405)
@@ -9160,6 +9142,13 @@ typedef struct PowerPCCPUAlias {
} PowerPCCPUAlias;
static const PowerPCCPUAlias ppc_cpu_aliases[] = {
+ { "403", "403GC" },
+ { "405", "405D4" },
+ { "405CR", "405CRc" },
+ { "405GP", "405GPd" },
+ { "x2vp7", "x2vp4" },
+ { "x2vp50", "x2vp20" },
+
{ "RCPU", "MPC5xx" },
/* MPC5xx microcontrollers */
{ "MGT560", "MPC5xx" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 12/66] target-ppc: Extract 440 aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (10 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 11/66] target-ppc: Extract 40x aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 13/66] target-ppc: Turn "ppc32" and "ppc64" CPUs into aliases Alexander Graf
` (54 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 23 +++++------------------
1 files changed, 5 insertions(+), 18 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 8a3cf9f..fb0a366 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7013,17 +7013,13 @@ enum {
CPU_POWERPC_440H6 = xxx,
#endif
/* PowerPC 440 microcontrolers */
-#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
CPU_POWERPC_440EPa = 0x42221850,
CPU_POWERPC_440EPb = 0x422218D3,
-#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
CPU_POWERPC_440GPb = 0x40120440,
CPU_POWERPC_440GPc = 0x40120481,
-#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
CPU_POWERPC_440GRX = 0x200008D0,
#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
-#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
CPU_POWERPC_440GXa = 0x51B21850,
CPU_POWERPC_440GXb = 0x51B21851,
CPU_POWERPC_440GXc = 0x51B21892,
@@ -7922,8 +7918,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5)
#endif
/* PowerPC 440 microcontrolers */
- /* PowerPC 440 EP */
- POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP)
/* PowerPC 440 EPa */
POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP)
/* PowerPC 440 EPb */
@@ -7931,10 +7925,6 @@ static const ppc_def_t ppc_defs[] = {
/* PowerPC 440 EPX */
POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP)
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 GP */
- POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP)
-#endif
-#if defined(TODO_USER_ONLY)
/* PowerPC 440 GPb */
POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP)
#endif
@@ -7943,10 +7933,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP)
#endif
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 GR */
- POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5)
-#endif
-#if defined(TODO_USER_ONLY)
/* PowerPC 440 GRa */
POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5)
#endif
@@ -7955,10 +7941,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5)
#endif
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 GX */
- POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP)
-#endif
-#if defined(TODO_USER_ONLY)
/* PowerPC 440 GXa */
POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP)
#endif
@@ -9149,6 +9131,11 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "x2vp7", "x2vp4" },
{ "x2vp50", "x2vp20" },
+ { "440EP", "440EPb" },
+ { "440GP", "440GPc" },
+ { "440GR", "440GRa" },
+ { "440GX", "440GXf" },
+
{ "RCPU", "MPC5xx" },
/* MPC5xx microcontrollers */
{ "MGT560", "MPC5xx" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 13/66] target-ppc: Turn "ppc32" and "ppc64" CPUs into aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (11 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 12/66] target-ppc: Extract 440 aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 14/66] target-ppc: Extract 74x7[A] aliases Alexander Graf
` (53 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 36 +++++-------------------------------
1 files changed, 5 insertions(+), 31 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index fb0a366..86b5c91 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6798,32 +6798,6 @@ static void init_proc_620 (CPUPPCState *env)
}
#endif /* defined (TARGET_PPC64) */
-/* Default 32 bits PowerPC target will be 604 */
-#define CPU_POWERPC_PPC32 CPU_POWERPC_604
-#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
-#define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
-#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
-#define POWERPC_MMU_PPC32 POWERPC_MMU_604
-#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
-#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
-#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
-#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
-#define check_pow_PPC32 check_pow_604
-#define init_proc_PPC32 init_proc_604
-
-/* Default 64 bits PowerPC target will be 970 FX */
-#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
-#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
-#define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
-#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
-#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
-#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
-#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
-#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
-#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
-#define check_pow_PPC64 check_pow_970FX
-#define init_proc_PPC64 init_proc_970FX
-
/*****************************************************************************/
/* PVR definitions for most known PowerPC */
enum {
@@ -9111,11 +9085,6 @@ static const ppc_def_t ppc_defs[] = {
/* PA PA6T */
POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T)
#endif
- /* Generic PowerPCs */
-#if defined (TARGET_PPC64)
- POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64)
-#endif
- POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32)
};
typedef struct PowerPCCPUAlias {
@@ -9213,6 +9182,11 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "RSC2", "POWER2" },
{ "P2SC", "POWER2" },
+ /* Generic PowerPCs */
+#if defined(TARGET_PPC64)
+ { "ppc64", "970fx" },
+#endif
+ { "ppc32", "604" },
{ "ppc", "ppc32" },
{ "default", "ppc" },
};
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 14/66] target-ppc: Extract 74x7[A] aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (12 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 13/66] target-ppc: Turn "ppc32" and "ppc64" CPUs into aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 15/66] target-ppc: Extract 74x5 as aliases Alexander Graf
` (52 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 14 ++++----------
1 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 86b5c91..27e625e 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7368,11 +7368,9 @@ enum {
CPU_POWERPC_74x5_v32 = 0x80010302,
CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
-#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
-#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
@@ -8929,10 +8927,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445)
/* PowerPC 7455 v3.4 (G4) */
POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455)
- /* PowerPC 7447 (G4) */
- POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445)
- /* PowerPC 7457 (G4) */
- POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455)
/* PowerPC 7447 v1.0 (G4) */
POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445)
/* PowerPC 7457 v1.0 (G4) */
@@ -8943,10 +8937,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455)
/* PowerPC 7457 v1.2 (G4) */
POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455)
- /* PowerPC 7447A (G4) */
- POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445)
- /* PowerPC 7457A (G4) */
- POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455)
/* PowerPC 7447A v1.0 (G4) */
POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445)
/* PowerPC 7457A v1.0 (G4) */
@@ -9158,7 +9148,11 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "Nitro", "7410" },
{ "Vger", "7450" },
{ "Apollo6", "7455" },
+ { "7447", "7447_v1.2" },
+ { "7457", "7457_v1.2" },
{ "Apollo7", "7457" },
+ { "7447A", "7447A_v1.2" },
+ { "7457A", "7457A_v1.2" },
{ "Apollo7PM", "7457A_v1.0" },
#if defined(TARGET_PPC64)
{ "Trident", "620" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 15/66] target-ppc: Extract 74x5 as aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (13 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 14/66] target-ppc: Extract 74x7[A] aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 16/66] target-ppc: Extract 74x1 aliases Alexander Graf
` (51 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 7 ++-----
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 27e625e..b7c9781 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7361,7 +7361,6 @@ enum {
CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
/* XXX: this entry might be a bug in some documentation */
CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
-#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
CPU_POWERPC_74x5_v10 = 0x80010100,
/* XXX: missing 0x80010200 */
CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
@@ -8903,10 +8902,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440)
/* PowerPC 7451 v2.10 (G4) */
POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450)
- /* PowerPC 7445 (G4) */
- POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445)
- /* PowerPC 7455 (G4) */
- POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455)
/* PowerPC 7445 v1.0 (G4) */
POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445)
/* PowerPC 7455 v1.0 (G4) */
@@ -9147,6 +9142,8 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "G4", "7400" },
{ "Nitro", "7410" },
{ "Vger", "7450" },
+ { "7445", "7445_v3.2" },
+ { "7455", "7455_v3.2" },
{ "Apollo6", "7455" },
{ "7447", "7447_v1.2" },
{ "7457", "7457_v1.2" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 16/66] target-ppc: Extract 74x1 aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (14 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 15/66] target-ppc: Extract 74x5 as aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 17/66] target-ppc: Extract 7450 alias Alexander Graf
` (50 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 7 ++-----
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index b7c9781..bd3076c 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7357,7 +7357,6 @@ enum {
CPU_POWERPC_7450_v12 = 0x80000102,
CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
-#define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
/* XXX: this entry might be a bug in some documentation */
CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
@@ -8888,10 +8887,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450)
/* PowerPC 7450 v2.1 (G4) */
POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450)
- /* PowerPC 7441 (G4) */
- POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440)
- /* PowerPC 7451 (G4) */
- POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450)
/* PowerPC 7441 v2.1 (G4) */
POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440)
/* PowerPC 7441 v2.3 (G4) */
@@ -9142,6 +9137,8 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "G4", "7400" },
{ "Nitro", "7410" },
{ "Vger", "7450" },
+ { "7441", "7441_v2.3" },
+ { "7451", "7451_v2.3" },
{ "7445", "7445_v3.2" },
{ "7455", "7455_v3.2" },
{ "Apollo6", "7455" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 17/66] target-ppc: Extract 7450 alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (15 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 16/66] target-ppc: Extract 74x1 aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 18/66] target-ppc: Extract 7448 alias Alexander Graf
` (49 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index bd3076c..7bc401b 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7351,7 +7351,6 @@ enum {
CPU_POWERPC_7448_v11 = 0x80040101,
CPU_POWERPC_7448_v20 = 0x80040200,
CPU_POWERPC_7448_v21 = 0x80040201,
-#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
CPU_POWERPC_7450_v10 = 0x80000100,
CPU_POWERPC_7450_v11 = 0x80000101,
CPU_POWERPC_7450_v12 = 0x80000102,
@@ -8875,8 +8874,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400)
/* PowerPC 7448 v2.1 (G4) */
POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400)
- /* PowerPC 7450 (G4) */
- POWERPC_DEF("7450", CPU_POWERPC_7450, 7450)
/* PowerPC 7450 v1.0 (G4) */
POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450)
/* PowerPC 7450 v1.1 (G4) */
@@ -9136,6 +9133,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "Max", "7400" },
{ "G4", "7400" },
{ "Nitro", "7410" },
+ { "7450", "7450_v2.1" },
{ "Vger", "7450" },
{ "7441", "7441_v2.3" },
{ "7451", "7451_v2.3" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 18/66] target-ppc: Extract 7448 alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (16 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 17/66] target-ppc: Extract 7450 alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 19/66] target-ppc: Extract 7410 alias Alexander Graf
` (48 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 7bc401b..4a4444f 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7346,7 +7346,6 @@ enum {
CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
-#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
CPU_POWERPC_7448_v10 = 0x80040100,
CPU_POWERPC_7448_v11 = 0x80040101,
CPU_POWERPC_7448_v20 = 0x80040200,
@@ -8864,8 +8863,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410)
/* PowerPC 7410 v1.4 (G4) */
POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410)
- /* PowerPC 7448 (G4) */
- POWERPC_DEF("7448", CPU_POWERPC_7448, 7400)
/* PowerPC 7448 v1.0 (G4) */
POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400)
/* PowerPC 7448 v1.1 (G4) */
@@ -9133,6 +9130,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "Max", "7400" },
{ "G4", "7400" },
{ "Nitro", "7410" },
+ { "7448", "7448_v2.1" },
{ "7450", "7450_v2.1" },
{ "Vger", "7450" },
{ "7441", "7441_v2.3" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 19/66] target-ppc: Extract 7410 alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (17 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 18/66] target-ppc: Extract 7448 alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 20/66] target-ppc: Extract 7400 alias Alexander Graf
` (47 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4a4444f..3fd8fd7 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7340,7 +7340,6 @@ enum {
CPU_POWERPC_7400_v27 = 0x000C0207,
CPU_POWERPC_7400_v28 = 0x000C0208,
CPU_POWERPC_7400_v29 = 0x000C0209,
-#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
CPU_POWERPC_7410_v10 = 0x800C1100,
CPU_POWERPC_7410_v11 = 0x800C1101,
CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
@@ -8851,8 +8850,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400)
/* PowerPC 7400 v2.9 (G4) */
POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400)
- /* PowerPC 7410 (G4) */
- POWERPC_DEF("7410", CPU_POWERPC_7410, 7410)
/* PowerPC 7410 v1.0 (G4) */
POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410)
/* PowerPC 7410 v1.1 (G4) */
@@ -9129,6 +9126,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "Goldfinger", "755" },
{ "Max", "7400" },
{ "G4", "7400" },
+ { "7410", "7410_v1.4" },
{ "Nitro", "7410" },
{ "7448", "7448_v2.1" },
{ "7450", "7450_v2.1" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 20/66] target-ppc: Extract 7400 alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (18 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 19/66] target-ppc: Extract 7410 alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 21/66] target-ppc: Extract 7x5 aliases Alexander Graf
` (46 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3fd8fd7..a97dfb7 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7330,7 +7330,6 @@ enum {
#endif
/* PowerPC 74xx cores (aka G4) */
/* XXX: missing 0x000C1101 */
-#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
CPU_POWERPC_7400_v10 = 0x000C0100,
CPU_POWERPC_7400_v11 = 0x000C0101,
CPU_POWERPC_7400_v20 = 0x000C0200,
@@ -8830,8 +8829,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755)
#endif
/* PowerPC 74xx family */
- /* PowerPC 7400 (G4) */
- POWERPC_DEF("7400", CPU_POWERPC_7400, 7400)
/* PowerPC 7400 v1.0 (G4) */
POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400)
/* PowerPC 7400 v1.1 (G4) */
@@ -9124,6 +9121,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "Conan/Doyle", "750p" },
{ "LoneStar", "750l" },
{ "Goldfinger", "755" },
+ { "7400", "7400_v2.9" },
{ "Max", "7400" },
{ "G4", "7400" },
{ "7410", "7410_v1.4" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 21/66] target-ppc: Extract 7x5 aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (19 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 20/66] target-ppc: Extract 7400 alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 22/66] target-ppc: Extract 750 aliases Alexander Graf
` (45 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 7 ++-----
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index a97dfb7..5981d98 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7313,7 +7313,6 @@ enum {
CPU_POWERPC_750L_v30 = 0x00088300,
CPU_POWERPC_750L_v32 = 0x00088302,
/* PowerPC 745/755 cores */
-#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
CPU_POWERPC_7x5_v10 = 0x00083100,
CPU_POWERPC_7x5_v11 = 0x00083101,
CPU_POWERPC_7x5_v20 = 0x00083200,
@@ -8774,10 +8773,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750)
/* PowerPC 750L v3.2 (G3 embedded) */
POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750)
- /* Generic PowerPC 745 */
- POWERPC_DEF("745", CPU_POWERPC_7x5, 745)
- /* Generic PowerPC 755 */
- POWERPC_DEF("755", CPU_POWERPC_7x5, 755)
/* PowerPC 745 v1.0 */
POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745)
/* PowerPC 755 v1.0 */
@@ -9120,6 +9115,8 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "G3", "750" },
{ "Conan/Doyle", "750p" },
{ "LoneStar", "750l" },
+ { "745", "745_v2.8" },
+ { "755", "755_v2.8" },
{ "Goldfinger", "755" },
{ "7400", "7400_v2.9" },
{ "Max", "7400" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 22/66] target-ppc: Extract 750 aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (20 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 21/66] target-ppc: Extract 7x5 aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 23/66] target-ppc: Extract 740/750 aliases Alexander Graf
` (44 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 24 ++++++------------------
1 files changed, 6 insertions(+), 18 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 5981d98..86db9a5 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7276,15 +7276,12 @@ enum {
CPU_POWERPC_750E = 0x00080200,
CPU_POWERPC_7x0P = 0x10080000,
/* XXX: missing 0x00087010 (CL ?) */
-#define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
CPU_POWERPC_750CL_v10 = 0x00087200,
CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
-#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
CPU_POWERPC_750CX_v10 = 0x00082100,
CPU_POWERPC_750CX_v20 = 0x00082200,
CPU_POWERPC_750CX_v21 = 0x00082201,
CPU_POWERPC_750CX_v22 = 0x00082202,
-#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
CPU_POWERPC_750CXE_v21 = 0x00082211,
CPU_POWERPC_750CXE_v22 = 0x00082212,
CPU_POWERPC_750CXE_v23 = 0x00082213,
@@ -7295,18 +7292,15 @@ enum {
CPU_POWERPC_750CXE_v31b = 0x00083311,
CPU_POWERPC_750CXR = 0x00083410,
CPU_POWERPC_750FL = 0x70000203,
-#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
CPU_POWERPC_750FX_v10 = 0x70000100,
CPU_POWERPC_750FX_v20 = 0x70000200,
CPU_POWERPC_750FX_v21 = 0x70000201,
CPU_POWERPC_750FX_v22 = 0x70000202,
CPU_POWERPC_750FX_v23 = 0x70000203,
CPU_POWERPC_750GL = 0x70020102,
-#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
CPU_POWERPC_750GX_v10 = 0x70020100,
CPU_POWERPC_750GX_v11 = 0x70020101,
CPU_POWERPC_750GX_v12 = 0x70020102,
-#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
CPU_POWERPC_750L_v20 = 0x00088200,
CPU_POWERPC_750L_v21 = 0x00088201,
CPU_POWERPC_750L_v22 = 0x00088202,
@@ -8701,14 +8695,10 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740)
/* PowerPC 750P (G3) */
POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750)
- /* PowerPC 750CL (G3 embedded) */
- POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl)
/* PowerPC 750CL v1.0 */
POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl)
/* PowerPC 750CL v2.0 */
POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl)
- /* PowerPC 750CX (G3 embedded) */
- POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx)
/* PowerPC 750CX v1.0 (G3 embedded) */
POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx)
/* PowerPC 750CX v2.1 (G3 embedded) */
@@ -8717,8 +8707,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx)
/* PowerPC 750CX v2.2 (G3 embedded) */
POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx)
- /* PowerPC 750CXe (G3 embedded) */
- POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx)
/* PowerPC 750CXe v2.1 (G3 embedded) */
POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx)
/* PowerPC 750CXe v2.2 (G3 embedded) */
@@ -8739,8 +8727,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx)
/* PowerPC 750FL (G3 embedded) */
POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx)
- /* PowerPC 750FX (G3 embedded) */
- POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx)
/* PowerPC 750FX v1.0 (G3 embedded) */
POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx)
/* PowerPC 750FX v2.0 (G3 embedded) */
@@ -8753,16 +8739,12 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx)
/* PowerPC 750GL (G3 embedded) */
POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx)
- /* PowerPC 750GX (G3 embedded) */
- POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx)
/* PowerPC 750GX v1.0 (G3 embedded) */
POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx)
/* PowerPC 750GX v1.1 (G3 embedded) */
POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx)
/* PowerPC 750GX v1.2 (G3 embedded) */
POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx)
- /* PowerPC 750L (G3 embedded) */
- POWERPC_DEF("750l", CPU_POWERPC_750L, 750)
/* PowerPC 750L v2.0 (G3 embedded) */
POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750)
/* PowerPC 750L v2.1 (G3 embedded) */
@@ -9114,6 +9096,12 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "Typhoon", "750" },
{ "G3", "750" },
{ "Conan/Doyle", "750p" },
+ { "750cl", "750cl_v2.0" },
+ { "750cx", "750cx_v2.2" },
+ { "750cxe", "750cxe_v3.1b" },
+ { "750fx", "750fx_v2.3" },
+ { "750gx", "750gx_v1.2" },
+ { "750l", "750l_v3.2" },
{ "LoneStar", "750l" },
{ "745", "745_v2.8" },
{ "755", "755_v2.8" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 23/66] target-ppc: Extract 740/750 aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (21 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 22/66] target-ppc: Extract 750 aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 24/66] target-ppc: Extract 603e alias Alexander Graf
` (43 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 7 ++-----
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 86db9a5..e6be35c 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7265,7 +7265,6 @@ enum {
#endif
/* PowerPC 740/750 cores (aka G3) */
/* XXX: missing 0x00084202 */
-#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
CPU_POWERPC_7x0_v10 = 0x00080100,
CPU_POWERPC_7x0_v20 = 0x00080200,
CPU_POWERPC_7x0_v21 = 0x00080201,
@@ -8659,10 +8658,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E)
#endif
/* PowerPC 7xx family */
- /* Generic PowerPC 740 (G3) */
- POWERPC_DEF("740", CPU_POWERPC_7x0, 740)
- /* Generic PowerPC 750 (G3) */
- POWERPC_DEF("750", CPU_POWERPC_7x0, 750)
/* PowerPC 740 v1.0 (G3) */
POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740)
/* PowerPC 750 v1.0 (G3) */
@@ -9092,7 +9087,9 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "Goldeneye", "603r" },
{ "Sirocco", "604e" },
{ "Mach5", "604r" },
+ { "740", "740_v3.1" },
{ "Arthur", "740" },
+ { "750", "750_v3.1" },
{ "Typhoon", "750" },
{ "G3", "750" },
{ "Conan/Doyle", "750p" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 24/66] target-ppc: Extract 603e alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (22 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 23/66] target-ppc: Extract 740/750 aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 25/66] target-ppc: Extract 603r alias Alexander Graf
` (42 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index e6be35c..59a1644 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7232,7 +7232,6 @@ enum {
CPU_POWERPC_601_v2 = 0x00010002,
CPU_POWERPC_602 = 0x00050100,
CPU_POWERPC_603 = 0x00030100,
-#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
CPU_POWERPC_603E_v11 = 0x00060101,
CPU_POWERPC_603E_v12 = 0x00060102,
CPU_POWERPC_603E_v13 = 0x00060103,
@@ -8609,8 +8608,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("602", CPU_POWERPC_602, 602)
/* PowerPC 603 */
POWERPC_DEF("603", CPU_POWERPC_603, 603)
- /* PowerPC 603e (aka PID6) */
- POWERPC_DEF("603e", CPU_POWERPC_603E, 603E)
/* PowerPC 603e v1.1 */
POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E)
/* PowerPC 603e v1.2 */
@@ -9082,6 +9079,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "PowerQUICC-II", "MPC82xx" },
{ "e500", "e500v2_v22" },
{ "Vanilla", "603" },
+ { "603e", "603e_v4.1" },
{ "Stretch", "603e" },
{ "Vaillant", "603e7v" },
{ "Goldeneye", "603r" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 25/66] target-ppc: Extract 603r alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (23 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 24/66] target-ppc: Extract 603e alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 26/66] target-ppc: Extract 601/601v aliases Alexander Graf
` (41 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 59a1644..69455c4 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7246,7 +7246,6 @@ enum {
CPU_POWERPC_603E7v2 = 0x00070201,
CPU_POWERPC_603E7 = 0x00070200,
CPU_POWERPC_603P = 0x00070000,
-#define CPU_POWERPC_603R CPU_POWERPC_603E7t
/* XXX: missing 0x00040303 (604) */
CPU_POWERPC_604 = 0x00040103,
#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
@@ -8636,8 +8635,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E)
/* PowerPC 603p (aka PID7v) */
POWERPC_DEF("603p", CPU_POWERPC_603P, 603E)
- /* PowerPC 603r (aka PID7t) */
- POWERPC_DEF("603r", CPU_POWERPC_603R, 603E)
/* PowerPC 604 */
POWERPC_DEF("604", CPU_POWERPC_604, 604)
/* PowerPC 604e (aka PID9) */
@@ -9082,6 +9079,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "603e", "603e_v4.1" },
{ "Stretch", "603e" },
{ "Vaillant", "603e7v" },
+ { "603r", "603e7t" },
{ "Goldeneye", "603r" },
{ "Sirocco", "604e" },
{ "Mach5", "604r" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 26/66] target-ppc: Extract 601/601v aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (24 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 25/66] target-ppc: Extract 603r alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 27/66] target-ppc: Extract 604e alias Alexander Graf
` (40 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 8 ++------
1 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 69455c4..03284c7 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7225,10 +7225,8 @@ enum {
#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
/* PowerPC 6xx cores */
-#define CPU_POWERPC_601 CPU_POWERPC_601_v2
CPU_POWERPC_601_v0 = 0x00010001,
CPU_POWERPC_601_v1 = 0x00010001,
-#define CPU_POWERPC_601v CPU_POWERPC_601_v2
CPU_POWERPC_601_v2 = 0x00010002,
CPU_POWERPC_602 = 0x00050100,
CPU_POWERPC_603 = 0x00030100,
@@ -8593,14 +8591,10 @@ static const ppc_def_t ppc_defs[] = {
CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400)
/* 32 bits "classic" PowerPC */
/* PowerPC 6xx family */
- /* PowerPC 601 */
- POWERPC_DEF("601", CPU_POWERPC_601, 601v)
/* PowerPC 601v0 */
POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601)
/* PowerPC 601v1 */
POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601)
- /* PowerPC 601v */
- POWERPC_DEF("601v", CPU_POWERPC_601v, 601v)
/* PowerPC 601v2 */
POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v)
/* PowerPC 602 */
@@ -9075,6 +9069,8 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "PowerQUICC-II", "MPC82xx" },
{ "e500", "e500v2_v22" },
+ { "601", "601_v2" },
+ { "601v", "601_v2" },
{ "Vanilla", "603" },
{ "603e", "603e_v4.1" },
{ "Stretch", "603e" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 27/66] target-ppc: Extract 604e alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (25 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 26/66] target-ppc: Extract 601/601v aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 28/66] target-ppc: Extract MPC85xx aliases Alexander Graf
` (39 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 03284c7..c909410 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7246,7 +7246,6 @@ enum {
CPU_POWERPC_603P = 0x00070000,
/* XXX: missing 0x00040303 (604) */
CPU_POWERPC_604 = 0x00040103,
-#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
/* XXX: missing 0x00091203 */
/* XXX: missing 0x00092110 */
/* XXX: missing 0x00092120 */
@@ -8631,8 +8630,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("603p", CPU_POWERPC_603P, 603E)
/* PowerPC 604 */
POWERPC_DEF("604", CPU_POWERPC_604, 604)
- /* PowerPC 604e (aka PID9) */
- POWERPC_DEF("604e", CPU_POWERPC_604E, 604E)
/* PowerPC 604e v1.0 */
POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E)
/* PowerPC 604e v2.2 */
@@ -9077,6 +9074,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "Vaillant", "603e7v" },
{ "603r", "603e7t" },
{ "Goldeneye", "603r" },
+ { "604e", "604e_v2.4" },
{ "Sirocco", "604e" },
{ "Mach5", "604r" },
{ "740", "740_v3.1" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 28/66] target-ppc: Extract MPC85xx aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (26 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 27/66] target-ppc: Extract 604e alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 29/66] target-ppc: Extract e500v1/e500v2 aliases Alexander Graf
` (38 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 102 +++++++-----------------------------------
1 files changed, 17 insertions(+), 85 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index c909410..9939af5 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7147,67 +7147,50 @@ enum {
CPU_POWERPC_e500mc = 0x80230020,
CPU_POWERPC_e5500 = 0x80240020,
/* MPC85xx microcontrollers */
-#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
-#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
-#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
-#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8547E_v21
#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
-#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
-#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
@@ -7509,64 +7492,47 @@ enum {
POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
-#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
@@ -8373,26 +8339,17 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF_SVR("e5500", CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500)
#endif
/* PowerPC e500 microcontrollers */
- /* MPC8533 */
- POWERPC_DEF_SVR("MPC8533",
- CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2)
/* MPC8533 v1.0 */
POWERPC_DEF_SVR("MPC8533_v10",
CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2)
/* MPC8533 v1.1 */
POWERPC_DEF_SVR("MPC8533_v11",
CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2)
- /* MPC8533E */
- POWERPC_DEF_SVR("MPC8533E",
- CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2)
/* MPC8533E v1.0 */
POWERPC_DEF_SVR("MPC8533E_v10",
CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2)
POWERPC_DEF_SVR("MPC8533E_v11",
CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2)
- /* MPC8540 */
- POWERPC_DEF_SVR("MPC8540",
- CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1)
/* MPC8540 v1.0 */
POWERPC_DEF_SVR("MPC8540_v10",
CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1)
@@ -8402,27 +8359,18 @@ static const ppc_def_t ppc_defs[] = {
/* MPC8540 v2.1 */
POWERPC_DEF_SVR("MPC8540_v21",
CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1)
- /* MPC8541 */
- POWERPC_DEF_SVR("MPC8541",
- CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1)
/* MPC8541 v1.0 */
POWERPC_DEF_SVR("MPC8541_v10",
CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1)
/* MPC8541 v1.1 */
POWERPC_DEF_SVR("MPC8541_v11",
CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1)
- /* MPC8541E */
- POWERPC_DEF_SVR("MPC8541E",
- CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1)
/* MPC8541E v1.0 */
POWERPC_DEF_SVR("MPC8541E_v10",
CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1)
/* MPC8541E v1.1 */
POWERPC_DEF_SVR("MPC8541E_v11",
CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1)
- /* MPC8543 */
- POWERPC_DEF_SVR("MPC8543",
- CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2)
/* MPC8543 v1.0 */
POWERPC_DEF_SVR("MPC8543_v10",
CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2)
@@ -8435,9 +8383,6 @@ static const ppc_def_t ppc_defs[] = {
/* MPC8543 v2.1 */
POWERPC_DEF_SVR("MPC8543_v21",
CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2)
- /* MPC8543E */
- POWERPC_DEF_SVR("MPC8543E",
- CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2)
/* MPC8543E v1.0 */
POWERPC_DEF_SVR("MPC8543E_v10",
CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2)
@@ -8450,54 +8395,36 @@ static const ppc_def_t ppc_defs[] = {
/* MPC8543E v2.1 */
POWERPC_DEF_SVR("MPC8543E_v21",
CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2)
- /* MPC8544 */
- POWERPC_DEF_SVR("MPC8544",
- CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2)
/* MPC8544 v1.0 */
POWERPC_DEF_SVR("MPC8544_v10",
CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2)
/* MPC8544 v1.1 */
POWERPC_DEF_SVR("MPC8544_v11",
CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2)
- /* MPC8544E */
- POWERPC_DEF_SVR("MPC8544E",
- CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2)
/* MPC8544E v1.0 */
POWERPC_DEF_SVR("MPC8544E_v10",
CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2)
/* MPC8544E v1.1 */
POWERPC_DEF_SVR("MPC8544E_v11",
CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2)
- /* MPC8545 */
- POWERPC_DEF_SVR("MPC8545",
- CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2)
/* MPC8545 v2.0 */
POWERPC_DEF_SVR("MPC8545_v20",
CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2)
/* MPC8545 v2.1 */
POWERPC_DEF_SVR("MPC8545_v21",
CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2)
- /* MPC8545E */
- POWERPC_DEF_SVR("MPC8545E",
- CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2)
/* MPC8545E v2.0 */
POWERPC_DEF_SVR("MPC8545E_v20",
CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2)
/* MPC8545E v2.1 */
POWERPC_DEF_SVR("MPC8545E_v21",
CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2)
- /* MPC8547E */
- POWERPC_DEF_SVR("MPC8547E",
- CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2)
/* MPC8547E v2.0 */
POWERPC_DEF_SVR("MPC8547E_v20",
CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2)
/* MPC8547E v2.1 */
POWERPC_DEF_SVR("MPC8547E_v21",
CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2)
- /* MPC8548 */
- POWERPC_DEF_SVR("MPC8548",
- CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2)
/* MPC8548 v1.0 */
POWERPC_DEF_SVR("MPC8548_v10",
CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2)
@@ -8510,9 +8437,6 @@ static const ppc_def_t ppc_defs[] = {
/* MPC8548 v2.1 */
POWERPC_DEF_SVR("MPC8548_v21",
CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2)
- /* MPC8548E */
- POWERPC_DEF_SVR("MPC8548E",
- CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2)
/* MPC8548E v1.0 */
POWERPC_DEF_SVR("MPC8548E_v10",
CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2)
@@ -8525,27 +8449,18 @@ static const ppc_def_t ppc_defs[] = {
/* MPC8548E v2.1 */
POWERPC_DEF_SVR("MPC8548E_v21",
CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2)
- /* MPC8555 */
- POWERPC_DEF_SVR("MPC8555",
- CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2)
/* MPC8555 v1.0 */
POWERPC_DEF_SVR("MPC8555_v10",
CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2)
/* MPC8555 v1.1 */
POWERPC_DEF_SVR("MPC8555_v11",
CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2)
- /* MPC8555E */
- POWERPC_DEF_SVR("MPC8555E",
- CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2)
/* MPC8555E v1.0 */
POWERPC_DEF_SVR("MPC8555E_v10",
CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2)
/* MPC8555E v1.1 */
POWERPC_DEF_SVR("MPC8555E_v11",
CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2)
- /* MPC8560 */
- POWERPC_DEF_SVR("MPC8560",
- CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2)
/* MPC8560 v1.0 */
POWERPC_DEF_SVR("MPC8560_v10",
CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2)
@@ -9066,6 +8981,23 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "PowerQUICC-II", "MPC82xx" },
{ "e500", "e500v2_v22" },
+ { "MPC8533", "MPC8533_v11" },
+ { "MPC8533E", "MPC8533E_v11" },
+ { "MPC8540", "MPC8540_v21" },
+ { "MPC8541", "MPC8541_v11" },
+ { "MPC8541E", "MPC8541E_v11" },
+ { "MPC8543", "MPC8543_v21" },
+ { "MPC8543E", "MPC8543E_v21" },
+ { "MPC8544", "MPC8544_v11" },
+ { "MPC8544E", "MPC8544E_v11" },
+ { "MPC8545", "MPC8545_v21" },
+ { "MPC8545E", "MPC8545E_v21" },
+ { "MPC8547E", "MPC8547E_v21" },
+ { "MPC8548", "MPC8548_v21" },
+ { "MPC8548E", "MPC8548E_v21" },
+ { "MPC8555", "MPC8555_v11" },
+ { "MPC8555E", "MPC8555E_v11" },
+ { "MPC8560", "MPC8560_v21" },
{ "601", "601_v2" },
{ "601v", "601_v2" },
{ "Vanilla", "603" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 29/66] target-ppc: Extract e500v1/e500v2 aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (27 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 28/66] target-ppc: Extract MPC85xx aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 30/66] target-ppc: Extract MPC83xx aliases Alexander Graf
` (37 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 8 ++------
1 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 9939af5..91473dc 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7134,8 +7134,6 @@ enum {
/* e500 family */
/* e500 cores */
#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
-#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
CPU_POWERPC_e500v1_v10 = 0x80200010,
CPU_POWERPC_e500v1_v20 = 0x80200020,
CPU_POWERPC_e500v2_v10 = 0x80210010,
@@ -8316,14 +8314,10 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF_SVR("MPC8379E",
CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300)
/* e500 family */
- /* PowerPC e500v1 core */
- POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1)
/* PowerPC e500 v1.0 core */
POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1)
/* PowerPC e500 v2.0 core */
POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1)
- /* PowerPC e500v2 core */
- POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2)
/* PowerPC e500v2 v1.0 core */
POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2)
/* PowerPC e500v2 v2.0 core */
@@ -8981,6 +8975,8 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "PowerQUICC-II", "MPC82xx" },
{ "e500", "e500v2_v22" },
+ { "e500v1", "e500_v20" },
+ { "e500v2", "e500v2_v22" },
{ "MPC8533", "MPC8533_v11" },
{ "MPC8533E", "MPC8533E_v11" },
{ "MPC8540", "MPC8540_v21" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 30/66] target-ppc: Extract MPC83xx aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (28 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 29/66] target-ppc: Extract e500v1/e500v2 aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 31/66] target-ppc: Extract e300 alias Alexander Graf
` (36 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 20 ++++----------------
1 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 91473dc..8f765ad 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7461,16 +7461,12 @@ enum {
POWERPC_SVR_8343A = 0x80570030,
POWERPC_SVR_8343E = 0x80560010,
POWERPC_SVR_8343EA = 0x80560030,
-#define POWERPC_SVR_8347 POWERPC_SVR_8347T
POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
-#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
-#define POWERPC_SVR_8347E POWERPC_SVR_8347ET
POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
-#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
POWERPC_SVR_8349 = 0x80510010,
@@ -8237,36 +8233,24 @@ static const ppc_def_t ppc_defs[] = {
/* MPC8343EA */
POWERPC_DEF_SVR("MPC8343EA",
CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300)
- /* MPC8347 */
- POWERPC_DEF_SVR("MPC8347",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300)
/* MPC8347T */
POWERPC_DEF_SVR("MPC8347T",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300)
/* MPC8347P */
POWERPC_DEF_SVR("MPC8347P",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300)
- /* MPC8347A */
- POWERPC_DEF_SVR("MPC8347A",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300)
/* MPC8347AT */
POWERPC_DEF_SVR("MPC8347AT",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300)
/* MPC8347AP */
POWERPC_DEF_SVR("MPC8347AP",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300)
- /* MPC8347E */
- POWERPC_DEF_SVR("MPC8347E",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300)
/* MPC8347ET */
POWERPC_DEF_SVR("MPC8347ET",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300)
/* MPC8343EP */
POWERPC_DEF_SVR("MPC8347EP",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300)
- /* MPC8347EA */
- POWERPC_DEF_SVR("MPC8347EA",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300)
/* MPC8347EAT */
POWERPC_DEF_SVR("MPC8347EAT",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300)
@@ -8974,6 +8958,10 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "MPC885", "MPC8xx" },
{ "PowerQUICC-II", "MPC82xx" },
+ { "MPC8347", "MPC8347T" },
+ { "MPC8347A", "MPC8347AT" },
+ { "MPC8347E", "MPC8347ET" },
+ { "MPC8347EA", "MPC8347EAT" },
{ "e500", "e500v2_v22" },
{ "e500v1", "e500_v20" },
{ "e500v2", "e500v2_v22" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 31/66] target-ppc: Extract e300 alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (29 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 30/66] target-ppc: Extract MPC83xx aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 32/66] target-ppc: Extract e200 alias Alexander Graf
` (35 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 8f765ad..d2cee80 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7119,7 +7119,6 @@ enum {
#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
/* e300 family */
/* e300 cores */
-#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
CPU_POWERPC_e300c1 = 0x00830010,
CPU_POWERPC_e300c2 = 0x00840010,
CPU_POWERPC_e300c3 = 0x00850010,
@@ -8160,8 +8159,6 @@ static const ppc_def_t ppc_defs[] = {
CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200)
#endif
/* e300 family */
- /* Generic PowerPC e300 core */
- POWERPC_DEF("e300", CPU_POWERPC_e300, e300)
/* PowerPC e300c1 core */
POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300)
/* PowerPC e300c2 core */
@@ -8958,6 +8955,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "MPC885", "MPC8xx" },
{ "PowerQUICC-II", "MPC82xx" },
+ { "e300", "e300c3" },
{ "MPC8347", "MPC8347T" },
{ "MPC8347A", "MPC8347AT" },
{ "MPC8347E", "MPC8347ET" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 32/66] target-ppc: Extract e200 alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (30 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 31/66] target-ppc: Extract e300 alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 33/66] target-ppc: Extract MPC82xx alias Alexander Graf
` (34 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d2cee80..a4eae26 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7077,7 +7077,6 @@ enum {
#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
/* e200 family */
/* e200 cores */
-#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
#if 0
CPU_POWERPC_e200z0 = xxx,
#endif
@@ -8024,8 +8023,6 @@ static const ppc_def_t ppc_defs[] = {
/* MPC8280 */
POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE)
/* e200 family */
- /* Generic PowerPC e200 core */
- POWERPC_DEF("e200", CPU_POWERPC_e200, e200)
/* Generic MPC55xx core */
#if defined (TODO)
POWERPC_DEF_SVR("MPC55xx",
@@ -8955,6 +8952,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "MPC885", "MPC8xx" },
{ "PowerQUICC-II", "MPC82xx" },
+ { "e200", "e200z6" },
{ "e300", "e300c3" },
{ "MPC8347", "MPC8347T" },
{ "MPC8347A", "MPC8347AT" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 33/66] target-ppc: Extract MPC82xx alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (31 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 32/66] target-ppc: Extract e200 alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 34/66] target-ppc: Extract MPC8247/MPC8248/MPC8270-80 aliases Alexander Graf
` (33 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index a4eae26..2ab7d16 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7046,7 +7046,6 @@ enum {
#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
/* MPC82xx microcontrollers */
-#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
@@ -7912,8 +7911,6 @@ static const ppc_def_t ppc_defs[] = {
/* Generic MPC52xx core */
POWERPC_DEF_SVR("MPC52xx",
CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE)
- /* Generic MPC82xx core */
- POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2)
/* PowerPC G2 core */
POWERPC_DEF("G2", CPU_POWERPC_G2, G2)
/* PowerPC G2 H4 core */
@@ -8951,6 +8948,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "MPC880", "MPC8xx" },
{ "MPC885", "MPC8xx" },
+ { "MPC82xx", "MPC8280" },
{ "PowerQUICC-II", "MPC82xx" },
{ "e200", "e200z6" },
{ "e300", "e300c3" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 34/66] target-ppc: Extract MPC8247/MPC8248/MPC8270-80 aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (32 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 33/66] target-ppc: Extract MPC82xx alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 35/66] target-ppc: Extract MPC82xx aliases to *_HiP4 Alexander Graf
` (32 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
This depends on the fix for "G2leGP3" PVR.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 28 +++++++---------------------
1 files changed, 7 insertions(+), 21 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 2ab7d16..8fd68ed 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7049,8 +7049,6 @@ enum {
#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
-#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
@@ -7069,11 +7067,6 @@ enum {
#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
-#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
-#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
-#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
-#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
/* e200 family */
/* e200 cores */
#if 0
@@ -7969,10 +7962,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2)
/* MPC8245 */
POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2)
- /* MPC8247 */
- POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE)
- /* MPC8248 */
- POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE)
/* MPC8250 */
POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2)
/* MPC8250 HiP3 */
@@ -8009,16 +7998,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2)
/* MPC8266 HiP4 */
POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2)
- /* MPC8270 */
- POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE)
- /* MPC8271 */
- POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE)
- /* MPC8272 */
- POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE)
- /* MPC8275 */
- POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE)
- /* MPC8280 */
- POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE)
/* e200 family */
/* Generic MPC55xx core */
#if defined (TODO)
@@ -8950,6 +8929,13 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "MPC82xx", "MPC8280" },
{ "PowerQUICC-II", "MPC82xx" },
+ { "MPC8247", "G2leGP3" },
+ { "MPC8248", "G2leGP3" },
+ { "MPC8270", "G2leGP3" },
+ { "MPC8271", "G2leGP3" },
+ { "MPC8272", "G2leGP3" },
+ { "MPC8275", "G2leGP3" },
+ { "MPC8280", "G2leGP3" },
{ "e200", "e200z6" },
{ "e300", "e300c3" },
{ "MPC8347", "MPC8347T" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 35/66] target-ppc: Extract MPC82xx aliases to *_HiP4
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (33 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 34/66] target-ppc: Extract MPC8247/MPC8248/MPC8270-80 aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 36/66] target-ppc: Extract MPC82xx_HiP{3, 4} aliases Alexander Graf
` (31 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 24 ++++++------------------
1 files changed, 6 insertions(+), 18 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 8fd68ed..6ba6d26 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7049,22 +7049,16 @@ enum {
#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
/* e200 family */
@@ -7962,38 +7956,26 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2)
/* MPC8245 */
POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2)
- /* MPC8250 */
- POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2)
/* MPC8250 HiP3 */
POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2)
/* MPC8250 HiP4 */
POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2)
- /* MPC8255 */
- POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2)
/* MPC8255 HiP3 */
POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2)
/* MPC8255 HiP4 */
POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2)
- /* MPC8260 */
- POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2)
/* MPC8260 HiP3 */
POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2)
/* MPC8260 HiP4 */
POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2)
- /* MPC8264 */
- POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2)
/* MPC8264 HiP3 */
POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2)
/* MPC8264 HiP4 */
POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2)
- /* MPC8265 */
- POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2)
/* MPC8265 HiP3 */
POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2)
/* MPC8265 HiP4 */
POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2)
- /* MPC8266 */
- POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2)
/* MPC8266 HiP3 */
POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2)
/* MPC8266 HiP4 */
@@ -8931,6 +8913,12 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "PowerQUICC-II", "MPC82xx" },
{ "MPC8247", "G2leGP3" },
{ "MPC8248", "G2leGP3" },
+ { "MPC8250", "MPC8250_HiP4" },
+ { "MPC8255", "MPC8255_HiP4" },
+ { "MPC8260", "MPC8260_HiP4" },
+ { "MPC8264", "MPC8264_HiP4" },
+ { "MPC8265", "MPC8265_HiP4" },
+ { "MPC8266", "MPC8266_HiP4" },
{ "MPC8270", "G2leGP3" },
{ "MPC8271", "G2leGP3" },
{ "MPC8272", "G2leGP3" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 36/66] target-ppc: Extract MPC82xx_HiP{3, 4} aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (34 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 35/66] target-ppc: Extract MPC82xx aliases to *_HiP4 Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 37/66] target-ppc: Extract MPC52xx alias Alexander Graf
` (30 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 56 ++++++++++--------------------------------
1 files changed, 14 insertions(+), 42 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6ba6d26..89c9e24 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7047,20 +7047,6 @@ enum {
#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
/* MPC82xx microcontrollers */
#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
-#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
-#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
-#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
-#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
-#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
-#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
-#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
-#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
/* e200 family */
/* e200 cores */
#if 0
@@ -7952,34 +7938,6 @@ static const ppc_def_t ppc_defs[] = {
/* MPC5200B v2.1 */
POWERPC_DEF_SVR("MPC5200B_v21",
CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
- /* MPC8241 */
- POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2)
- /* MPC8245 */
- POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2)
- /* MPC8250 HiP3 */
- POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2)
- /* MPC8250 HiP4 */
- POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2)
- /* MPC8255 HiP3 */
- POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2)
- /* MPC8255 HiP4 */
- POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2)
- /* MPC8260 HiP3 */
- POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2)
- /* MPC8260 HiP4 */
- POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2)
- /* MPC8264 HiP3 */
- POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2)
- /* MPC8264 HiP4 */
- POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2)
- /* MPC8265 HiP3 */
- POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2)
- /* MPC8265 HiP4 */
- POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2)
- /* MPC8266 HiP3 */
- POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2)
- /* MPC8266 HiP4 */
- POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2)
/* e200 family */
/* Generic MPC55xx core */
#if defined (TODO)
@@ -8911,14 +8869,28 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "MPC82xx", "MPC8280" },
{ "PowerQUICC-II", "MPC82xx" },
+ { "MPC8241", "G2HiP4" },
+ { "MPC8245", "G2HiP4" },
{ "MPC8247", "G2leGP3" },
{ "MPC8248", "G2leGP3" },
{ "MPC8250", "MPC8250_HiP4" },
+ { "MPC8250_HiP3", "G2HiP3" },
+ { "MPC8250_HiP4", "G2HiP4" },
{ "MPC8255", "MPC8255_HiP4" },
+ { "MPC8255_HiP3", "G2HiP3" },
+ { "MPC8255_HiP4", "G2HiP4" },
{ "MPC8260", "MPC8260_HiP4" },
+ { "MPC8260_HiP3", "G2HiP3" },
+ { "MPC8260_HiP4", "G2HiP4" },
{ "MPC8264", "MPC8264_HiP4" },
+ { "MPC8264_HiP3", "G2HiP3" },
+ { "MPC8264_HiP4", "G2HiP4" },
{ "MPC8265", "MPC8265_HiP4" },
+ { "MPC8265_HiP3", "G2HiP3" },
+ { "MPC8265_HiP4", "G2HiP4" },
{ "MPC8266", "MPC8266_HiP4" },
+ { "MPC8266_HiP3", "G2HiP3" },
+ { "MPC8266_HiP4", "G2HiP4" },
{ "MPC8270", "G2leGP3" },
{ "MPC8271", "G2leGP3" },
{ "MPC8272", "G2leGP3" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 37/66] target-ppc: Extract MPC52xx alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (35 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 36/66] target-ppc: Extract MPC82xx_HiP{3, 4} aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 38/66] target-ppc: Extract MPC5200/MPC5200B aliases Alexander Graf
` (29 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 7 ++-----
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 89c9e24..625811e 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7037,7 +7037,6 @@ enum {
CPU_POWERPC_G2LEgp3 = 0x80822013,
/* MPC52xx microcontrollers */
/* XXX: MPC 5121 ? */
-#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
@@ -7364,7 +7363,6 @@ enum {
/* System version register (used on MPC 8xxx) */
enum {
POWERPC_SVR_NONE = 0x00000000,
-#define POWERPC_SVR_52xx POWERPC_SVR_5200
#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
POWERPC_SVR_5200_v10 = 0x80110010,
POWERPC_SVR_5200_v11 = 0x80110011,
@@ -7881,9 +7879,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx)
#endif
/* MPC82xx family (aka PowerQUICC-II) */
- /* Generic MPC52xx core */
- POWERPC_DEF_SVR("MPC52xx",
- CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE)
/* PowerPC G2 core */
POWERPC_DEF("G2", CPU_POWERPC_G2, G2)
/* PowerPC G2 H4 core */
@@ -8867,6 +8862,8 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "MPC880", "MPC8xx" },
{ "MPC885", "MPC8xx" },
+ { "MPC52xx", "MPC5200" },
+
{ "MPC82xx", "MPC8280" },
{ "PowerQUICC-II", "MPC82xx" },
{ "MPC8241", "G2HiP4" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 38/66] target-ppc: Extract MPC5200/MPC5200B aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (36 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 37/66] target-ppc: Extract MPC52xx alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 39/66] target-ppc: Extract MPC8240 alias Alexander Graf
` (28 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 12 ++----------
1 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 625811e..2e41f0b 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7037,11 +7037,9 @@ enum {
CPU_POWERPC_G2LEgp3 = 0x80822013,
/* MPC52xx microcontrollers */
/* XXX: MPC 5121 ? */
-#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
-#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
/* MPC82xx microcontrollers */
@@ -7363,11 +7361,9 @@ enum {
/* System version register (used on MPC 8xxx) */
enum {
POWERPC_SVR_NONE = 0x00000000,
-#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
POWERPC_SVR_5200_v10 = 0x80110010,
POWERPC_SVR_5200_v11 = 0x80110011,
POWERPC_SVR_5200_v12 = 0x80110012,
-#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
POWERPC_SVR_5200B_v20 = 0x80110020,
POWERPC_SVR_5200B_v21 = 0x80110021,
#define POWERPC_SVR_55xx POWERPC_SVR_5567
@@ -7912,9 +7908,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF_SVR("MPC5121",
CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE)
#endif
- /* MPC5200 */
- POWERPC_DEF_SVR("MPC5200",
- CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE)
/* MPC5200 v1.0 */
POWERPC_DEF_SVR("MPC5200_v10",
CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE)
@@ -7924,9 +7917,6 @@ static const ppc_def_t ppc_defs[] = {
/* MPC5200 v1.2 */
POWERPC_DEF_SVR("MPC5200_v12",
CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE)
- /* MPC5200B */
- POWERPC_DEF_SVR("MPC5200B",
- CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE)
/* MPC5200B v2.0 */
POWERPC_DEF_SVR("MPC5200B_v20",
CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
@@ -8863,6 +8853,8 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "MPC885", "MPC8xx" },
{ "MPC52xx", "MPC5200" },
+ { "MPC5200", "MPC5200_v12" },
+ { "MPC5200B", "MPC5200B_v21" },
{ "MPC82xx", "MPC8280" },
{ "PowerQUICC-II", "MPC82xx" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 39/66] target-ppc: Extract MPC8240 alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (37 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 38/66] target-ppc: Extract MPC5200/MPC5200B aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 40/66] target-ppc: Extract 405GPe alias Alexander Graf
` (27 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 8 +++-----
1 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 2e41f0b..4e5278d 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7042,8 +7042,6 @@ enum {
#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
- /* MPC82xx microcontrollers */
-#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
/* e200 family */
/* e200 cores */
#if 0
@@ -7899,9 +7897,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE)
/* PowerPC G2LE GP3 core */
POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2LE)
- /* PowerPC MPC603 microcontrollers */
- /* MPC8240 */
- POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E)
/* PowerPC G2 microcontrollers */
#if defined(TODO)
/* MPC5121 */
@@ -8852,6 +8847,9 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "MPC880", "MPC8xx" },
{ "MPC885", "MPC8xx" },
+ /* PowerPC MPC603 microcontrollers */
+ { "MPC8240", "603" },
+
{ "MPC52xx", "MPC5200" },
{ "MPC5200", "MPC5200_v12" },
{ "MPC5200B", "MPC5200B_v21" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 40/66] target-ppc: Extract 405GPe alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (38 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 39/66] target-ppc: Extract MPC8240 alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 41/66] target-ppc: Extract 970 aliases Alexander Graf
` (26 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4e5278d..3fa131f 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6891,7 +6891,6 @@ enum {
CPU_POWERPC_405GPb = 0x40110040,
CPU_POWERPC_405GPc = 0x40110082,
CPU_POWERPC_405GPd = 0x401100C4,
-#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
CPU_POWERPC_405GPR = 0x50910951,
#if 0
CPU_POWERPC_405H = xxx,
@@ -7658,8 +7657,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405)
/* PowerPC 405 GPd */
POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405)
- /* PowerPC 405 GPe */
- POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405)
/* PowerPC 405 GPR */
POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405)
#if defined(TODO)
@@ -8805,6 +8802,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "405", "405D4" },
{ "405CR", "405CRc" },
{ "405GP", "405GPd" },
+ { "405GPe", "405CRc" },
{ "x2vp7", "x2vp4" },
{ "x2vp50", "x2vp20" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 41/66] target-ppc: Extract 970 aliases
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (39 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 40/66] target-ppc: Extract 405GPe alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 42/66] target-ppc: Extract POWER7 alias Alexander Graf
` (25 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 8 ++------
1 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3fa131f..bcb22cc 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7320,14 +7320,12 @@ enum {
CPU_POWERPC_POWER7_v21 = 0x003F0201,
CPU_POWERPC_POWER7_v23 = 0x003F0203,
CPU_POWERPC_970 = 0x00390202,
-#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
CPU_POWERPC_970FX_v10 = 0x00391100,
CPU_POWERPC_970FX_v20 = 0x003C0200,
CPU_POWERPC_970FX_v21 = 0x003C0201,
CPU_POWERPC_970FX_v30 = 0x003C0300,
CPU_POWERPC_970FX_v31 = 0x003C0301,
CPU_POWERPC_970GX = 0x00450000,
-#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
CPU_POWERPC_970MP_v10 = 0x00440100,
CPU_POWERPC_970MP_v11 = 0x00440101,
#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
@@ -8711,8 +8709,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7)
/* PowerPC 970 */
POWERPC_DEF("970", CPU_POWERPC_970, 970)
- /* PowerPC 970FX (G5) */
- POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX)
/* PowerPC 970FX v1.0 (G5) */
POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX)
/* PowerPC 970FX v2.0 (G5) */
@@ -8725,8 +8721,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX)
/* PowerPC 970GX (G5) */
POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX)
- /* PowerPC 970MP */
- POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP)
/* PowerPC 970MP v1.0 */
POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP)
/* PowerPC 970MP v1.1 */
@@ -8959,6 +8953,8 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "Boxer", "POWER3" },
{ "Dino", "POWER3" },
{ "POWER3+", "631" },
+ { "970fx", "970fx_v3.1" },
+ { "970mp", "970mp_v1.1" },
{ "Apache", "RS64" },
{ "A35", "RS64" },
{ "NorthStar", "RS64-II" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 42/66] target-ppc: Extract POWER7 alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (40 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 41/66] target-ppc: Extract 970 aliases Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 43/66] target-ppc: Get model name from type name Alexander Graf
` (24 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index bcb22cc..9d4831f 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7315,7 +7315,6 @@ enum {
CPU_POWERPC_POWER6 = 0x003E0000,
CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
CPU_POWERPC_POWER6A = 0x0F000002,
-#define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
CPU_POWERPC_POWER7_v20 = 0x003F0200,
CPU_POWERPC_POWER7_v21 = 0x003F0201,
CPU_POWERPC_POWER7_v23 = 0x003F0203,
@@ -8703,7 +8702,6 @@ static const ppc_def_t ppc_defs[] = {
POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6)
#endif
/* POWER7 */
- POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7)
POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7)
POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7)
POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7)
@@ -8953,6 +8951,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "Boxer", "POWER3" },
{ "Dino", "POWER3" },
{ "POWER3+", "631" },
+ { "POWER7", "POWER7_v2.0" },
{ "970fx", "970fx_v3.1" },
{ "970mp", "970mp_v1.1" },
{ "Apache", "RS64" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 43/66] target-ppc: Get model name from type name
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (41 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 42/66] target-ppc: Extract POWER7 alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 44/66] target-ppc: Convert CPU definitions Alexander Graf
` (23 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
We are about to drop the redundant name field along with ppc_def_t.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 13 ++++++++++---
1 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 9d4831f..7eb565d 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -9979,9 +9979,14 @@ static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
ObjectClass *oc = data;
CPUListState *s = user_data;
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ const char *typename = object_class_get_name(oc);
+ char *name;
+ name = g_strndup(typename,
+ strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
(*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
- pcc->info->name, pcc->info->pvr);
+ name, pcc->info->pvr);
+ g_free(name);
}
void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
@@ -10014,12 +10019,14 @@ static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
{
ObjectClass *oc = data;
CpuDefinitionInfoList **first = user_data;
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ const char *typename;
CpuDefinitionInfoList *entry;
CpuDefinitionInfo *info;
+ typename = object_class_get_name(oc);
info = g_malloc0(sizeof(*info));
- info->name = g_strdup(pcc->info->name);
+ info->name = g_strndup(typename,
+ strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
entry = g_malloc0(sizeof(*entry));
entry->value = info;
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 44/66] target-ppc: Convert CPU definitions
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (42 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 43/66] target-ppc: Get model name from type name Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 45/66] target-ppc: Introduce abstract CPU family types Alexander Graf
` (22 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Turn the array of model definitions into a set of self-registering QOM
types with their own class_init. Unique identifiers are obtained from
the combination of PVR, SVR and family identifiers; this requires all
alias #defines to be removed from the list. Possibly there are some more
left after this commit that are not currently being compiled.
Prepares for introducing abstract intermediate CPU types for families.
Keep the right-aligned macro line breaks within 78 chars to aid
three-way merges.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/cpu-qom.h | 17 ++++-
target-ppc/cpu.h | 20 -----
target-ppc/kvm.c | 32 +++++---
target-ppc/translate_init.c | 163 +++++++++++++++++++++----------------------
4 files changed, 115 insertions(+), 117 deletions(-)
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index 4e8ceca..2bf0ab6 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -53,8 +53,21 @@ typedef struct PowerPCCPUClass {
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
- /* TODO inline fields here */
- ppc_def_t *info;
+ uint32_t pvr;
+ uint32_t svr;
+ uint64_t insns_flags;
+ uint64_t insns_flags2;
+ uint64_t msr_mask;
+ powerpc_mmu_t mmu_model;
+ powerpc_excp_t excp_model;
+ powerpc_input_t bus_model;
+ uint32_t flags;
+ int bfd_mach;
+#if defined(TARGET_PPC64)
+ const struct ppc_segment_page_sizes *sps;
+#endif
+ void (*init_proc)(CPUPPCState *env);
+ int (*check_pow)(CPUPPCState *env);
} PowerPCCPUClass;
/**
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 20f4565..e4cf96c 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -307,7 +307,6 @@ enum powerpc_input_t {
#define PPC_INPUT(env) (env->bus_model)
/*****************************************************************************/
-typedef struct ppc_def_t ppc_def_t;
typedef struct opc_handler_t opc_handler_t;
/*****************************************************************************/
@@ -902,25 +901,6 @@ struct ppc_segment_page_sizes {
/* The whole PowerPC CPU context */
#define NB_MMU_MODES 3
-struct ppc_def_t {
- const char *name;
- uint32_t pvr;
- uint32_t svr;
- uint64_t insns_flags;
- uint64_t insns_flags2;
- uint64_t msr_mask;
- powerpc_mmu_t mmu_model;
- powerpc_excp_t excp_model;
- powerpc_input_t bus_model;
- uint32_t flags;
- int bfd_mach;
-#if defined(TARGET_PPC64)
- const struct ppc_segment_page_sizes *sps;
-#endif
- void (*init_proc)(CPUPPCState *env);
- int (*check_pow)(CPUPPCState *env);
-};
-
struct CPUPPCState {
/* First are the most commonly used resources
* during translated code execution
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 8e64416..a89c3cf 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1263,7 +1263,7 @@ static void kvmppc_host_cpu_initfn(Object *obj)
assert(kvm_enabled());
- if (pcc->info->pvr != mfpvr()) {
+ if (pcc->pvr != mfpvr()) {
fprintf(stderr, "Your host CPU is unsupported.\n"
"Please choose a supported model instead, see -cpu ?.\n");
exit(1);
@@ -1275,30 +1275,38 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
uint32_t host_pvr = mfpvr();
PowerPCCPUClass *pvr_pcc;
- ppc_def_t *spec;
uint32_t vmx = kvmppc_get_vmx();
uint32_t dfp = kvmppc_get_dfp();
- spec = g_malloc0(sizeof(*spec));
-
pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
if (pvr_pcc != NULL) {
- memcpy(spec, pvr_pcc->info, sizeof(*spec));
+ pcc->pvr = pvr_pcc->pvr;
+ pcc->svr = pvr_pcc->svr;
+ pcc->insns_flags = pvr_pcc->insns_flags;
+ pcc->insns_flags2 = pvr_pcc->insns_flags2;
+ pcc->msr_mask = pvr_pcc->msr_mask;
+ pcc->mmu_model = pvr_pcc->mmu_model;
+ pcc->excp_model = pvr_pcc->excp_model;
+ pcc->bus_model = pvr_pcc->bus_model;
+ pcc->flags = pvr_pcc->flags;
+ pcc->bfd_mach = pvr_pcc->bfd_mach;
+#ifdef TARGET_PPC64
+ pcc->sps = pvr_pcc->sps;
+#endif
+ pcc->init_proc = pvr_pcc->init_proc;
+ pcc->check_pow = pvr_pcc->check_pow;
}
- pcc->info = spec;
- /* Override the display name for -cpu ? and QMP */
- pcc->info->name = "host";
- /* Now fix up the spec with information we can query from the host */
+ /* Now fix up the class with information we can query from the host */
if (vmx != -1) {
/* Only override when we know what the host supports */
- alter_insns(&spec->insns_flags, PPC_ALTIVEC, vmx > 0);
- alter_insns(&spec->insns_flags2, PPC2_VSX, vmx > 1);
+ alter_insns(&pcc->insns_flags, PPC_ALTIVEC, vmx > 0);
+ alter_insns(&pcc->insns_flags2, PPC2_VSX, vmx > 1);
}
if (dfp != -1) {
/* Only override when we know what the host supports */
- alter_insns(&spec->insns_flags2, PPC2_DFP, dfp);
+ alter_insns(&pcc->insns_flags2, PPC2_DFP, dfp);
}
}
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 7eb565d..f707197 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7503,26 +7503,59 @@ enum {
/*****************************************************************************/
/* PowerPC CPU definitions */
+#define POWERPC_DEF_PREFIX(pvr, svr, type) \
+ glue(glue(glue(glue(pvr, _), svr), _), type)
+#if defined(TARGET_PPCEMB)
+#define POWERPC_DEF_CONDITION(type) \
+ if (glue(POWERPC_MMU_, type) != POWERPC_MMU_BOOKE) { \
+ return; \
+ }
+#else
+#define POWERPC_DEF_CONDITION(type)
+#endif
#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
- { \
- .name = _name, \
- .pvr = _pvr, \
- .svr = _svr, \
- .insns_flags = glue(POWERPC_INSNS_,_type), \
- .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
- .msr_mask = glue(POWERPC_MSRM_,_type), \
- .mmu_model = glue(POWERPC_MMU_,_type), \
- .excp_model = glue(POWERPC_EXCP_,_type), \
- .bus_model = glue(POWERPC_INPUT_,_type), \
- .bfd_mach = glue(POWERPC_BFDM_,_type), \
- .flags = glue(POWERPC_FLAG_,_type), \
- .init_proc = &glue(init_proc_,_type), \
- .check_pow = &glue(check_pow_,_type), \
- },
+ static void \
+ glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init) \
+ (ObjectClass *oc, void *data) \
+ { \
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); \
+ \
+ pcc->pvr = _pvr; \
+ pcc->svr = _svr; \
+ pcc->insns_flags = glue(POWERPC_INSNS_, _type); \
+ pcc->insns_flags2 = glue(POWERPC_INSNS2_, _type); \
+ pcc->msr_mask = glue(POWERPC_MSRM_, _type); \
+ pcc->mmu_model = glue(POWERPC_MMU_, _type); \
+ pcc->excp_model = glue(POWERPC_EXCP_, _type); \
+ pcc->bus_model = glue(POWERPC_INPUT_, _type); \
+ pcc->bfd_mach = glue(POWERPC_BFDM_, _type); \
+ pcc->flags = glue(POWERPC_FLAG_, _type); \
+ pcc->init_proc = &glue(init_proc_, _type); \
+ pcc->check_pow = &glue(check_pow_, _type); \
+ } \
+ \
+ static const TypeInfo \
+ glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info) = { \
+ .name = _name "-" TYPE_POWERPC_CPU, \
+ .parent = TYPE_POWERPC_CPU, \
+ .class_init = \
+ glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init), \
+ }; \
+ \
+ static void \
+ glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types)(void) \
+ { \
+ POWERPC_DEF_CONDITION(_type) \
+ type_register_static( \
+ &glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info)); \
+ } \
+ \
+ type_init( \
+ glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types))
+
#define POWERPC_DEF(_name, _pvr, _type) \
POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
-static const ppc_def_t ppc_defs[] = {
/* Embedded PowerPC */
/* PowerPC 401 family */
/* Generic PowerPC 401 */
@@ -8782,7 +8815,6 @@ static const ppc_def_t ppc_defs[] = {
/* PA PA6T */
POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T)
#endif
-};
typedef struct PowerPCCPUAlias {
const char *alias;
@@ -8981,8 +9013,10 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
/*****************************************************************************/
/* Generic CPU instantiation routine */
-static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
+static void init_ppc_proc(PowerPCCPU *cpu)
{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ CPUPPCState *env = &cpu->env;
#if !defined(CONFIG_USER_ONLY)
int i;
@@ -9010,23 +9044,23 @@ static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
#endif
SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
- def->pvr);
+ pcc->pvr);
/* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
- if (def->svr != POWERPC_SVR_NONE) {
- if (def->svr & POWERPC_SVR_E500) {
+ if (pcc->svr != POWERPC_SVR_NONE) {
+ if (pcc->svr & POWERPC_SVR_E500) {
spr_register(env, SPR_E500_SVR, "SVR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
- def->svr & ~POWERPC_SVR_E500);
+ pcc->svr & ~POWERPC_SVR_E500);
} else {
spr_register(env, SPR_SVR, "SVR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
- def->svr);
+ pcc->svr);
}
}
/* PowerPC implementation specific initialisations (SPRs, timers, ...) */
- (*def->init_proc)(env);
+ (*pcc->init_proc)(env);
#if !defined(CONFIG_USER_ONLY)
env->excp_prefix = env->hreset_excp_prefix;
#endif
@@ -9377,13 +9411,12 @@ static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
{
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
CPUPPCState *env = &cpu->env;
- const ppc_def_t *def = pcc->info;
opcode_t *opc;
fill_new_table(env->opcodes, 0x40);
for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
- if (((opc->handler.type & def->insns_flags) != 0) ||
- ((opc->handler.type2 & def->insns_flags2) != 0)) {
+ if (((opc->handler.type & pcc->insns_flags) != 0) ||
+ ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
if (register_insn(env->opcodes, opc) < 0) {
error_setg(errp, "ERROR initializing PowerPC instruction "
"0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
@@ -9615,7 +9648,6 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
PowerPCCPU *cpu = POWERPC_CPU(dev);
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- ppc_def_t *def = pcc->info;
Error *local_err = NULL;
#if !defined(CONFIG_USER_ONLY)
int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
@@ -9646,17 +9678,17 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
error_propagate(errp, local_err);
return;
}
- init_ppc_proc(env, def);
+ init_ppc_proc(cpu);
- if (def->insns_flags & PPC_FLOAT) {
+ if (pcc->insns_flags & PPC_FLOAT) {
gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
33, "power-fpu.xml", 0);
}
- if (def->insns_flags & PPC_ALTIVEC) {
+ if (pcc->insns_flags & PPC_ALTIVEC) {
gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
34, "power-altivec.xml", 0);
}
- if (def->insns_flags & PPC_SPE) {
+ if (pcc->insns_flags & PPC_SPE) {
gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
34, "power-spe.xml", 0);
}
@@ -9782,7 +9814,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
}
printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
" MMU model : %s\n",
- def->name, def->pvr, def->msr_mask, mmu_model);
+ pcc->name, pcc->pvr, pcc->msr_mask, mmu_model);
#if !defined(CONFIG_USER_ONLY)
if (env->tlb != NULL) {
printf(" %d %s TLB in %d ways\n",
@@ -9840,7 +9872,7 @@ static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
return -1;
}
- return pcc->info->pvr == pvr ? 0 : -1;
+ return pcc->pvr == pvr ? 0 : -1;
}
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
@@ -9964,9 +9996,9 @@ static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
return -1;
} else {
/* Avoid an integer overflow during subtraction */
- if (pcc_a->info->pvr < pcc_b->info->pvr) {
+ if (pcc_a->pvr < pcc_b->pvr) {
return -1;
- } else if (pcc_a->info->pvr > pcc_b->info->pvr) {
+ } else if (pcc_a->pvr > pcc_b->pvr) {
return 1;
} else {
return 0;
@@ -9985,7 +10017,7 @@ static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
name = g_strndup(typename,
strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
(*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
- name, pcc->info->pvr);
+ name, pcc->pvr);
g_free(name);
}
@@ -10046,27 +10078,6 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
return cpu_list;
}
-static void ppc_cpu_def_class_init(ObjectClass *oc, void *data)
-{
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
- ppc_def_t *info = data;
-
- pcc->info = info;
-}
-
-static void ppc_cpu_register_model(const ppc_def_t *def)
-{
- TypeInfo type_info = {
- .parent = TYPE_POWERPC_CPU,
- .class_init = ppc_cpu_def_class_init,
- .class_data = (void *)def,
- };
-
- type_info.name = g_strdup_printf("%s-" TYPE_POWERPC_CPU, def->name),
- type_register(&type_info);
- g_free((gpointer)type_info.name);
-}
-
/* CPUClass::reset() */
static void ppc_cpu_reset(CPUState *s)
{
@@ -10138,24 +10149,23 @@ static void ppc_cpu_initfn(Object *obj)
PowerPCCPU *cpu = POWERPC_CPU(obj);
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
CPUPPCState *env = &cpu->env;
- ppc_def_t *def = pcc->info;
cs->env_ptr = env;
cpu_exec_init(env);
- env->msr_mask = def->msr_mask;
- env->mmu_model = def->mmu_model;
- env->excp_model = def->excp_model;
- env->bus_model = def->bus_model;
- env->insns_flags = def->insns_flags;
- env->insns_flags2 = def->insns_flags2;
- env->flags = def->flags;
- env->bfd_mach = def->bfd_mach;
- env->check_pow = def->check_pow;
+ env->msr_mask = pcc->msr_mask;
+ env->mmu_model = pcc->mmu_model;
+ env->excp_model = pcc->excp_model;
+ env->bus_model = pcc->bus_model;
+ env->insns_flags = pcc->insns_flags;
+ env->insns_flags2 = pcc->insns_flags2;
+ env->flags = pcc->flags;
+ env->bfd_mach = pcc->bfd_mach;
+ env->check_pow = pcc->check_pow;
#if defined(TARGET_PPC64)
- if (def->sps) {
- env->sps = *def->sps;
+ if (pcc->sps) {
+ env->sps = *pcc->sps;
} else if (env->mmu_model & POWERPC_MMU_64) {
/* Use default sets of page sizes */
static const struct ppc_segment_page_sizes defsps = {
@@ -10206,20 +10216,7 @@ static const TypeInfo ppc_cpu_type_info = {
static void ppc_cpu_register_types(void)
{
- int i;
-
type_register_static(&ppc_cpu_type_info);
-
- for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
- const ppc_def_t *def = &ppc_defs[i];
-#if defined(TARGET_PPCEMB)
- /* When using the ppcemb target, we only support 440 style cores */
- if (def->mmu_model != POWERPC_MMU_BOOKE) {
- continue;
- }
-#endif
- ppc_cpu_register_model(def);
- }
}
type_init(ppc_cpu_register_types)
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 45/66] target-ppc: Introduce abstract CPU family types
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (43 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 44/66] target-ppc: Convert CPU definitions Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 46/66] target-ppc: Set instruction flags on CPU family classes Alexander Graf
` (21 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Instead of assigning *_<family> constants, set .parent to a family type.
Introduce a POWERPC_FAMILY() macro to keep type registration close to
its implementation. This macro will need tweaking later.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 501 +++++++++++++++++++++++++++++++++++++------
1 files changed, 432 insertions(+), 69 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index f707197..c300aa8 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3252,6 +3252,28 @@ static int check_pow_hid0_74xx (CPUPPCState *env)
/*****************************************************************************/
/* PowerPC implementations definitions */
+#define POWERPC_FAMILY(_name) \
+ static void \
+ glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
+ \
+ static const TypeInfo \
+ glue(glue(ppc_, _name), _cpu_family_type_info) = { \
+ .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
+ .parent = TYPE_POWERPC_CPU, \
+ .abstract = true, \
+ .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
+ }; \
+ \
+ static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
+ { \
+ type_register_static( \
+ &glue(glue(ppc_, _name), _cpu_family_type_info)); \
+ } \
+ \
+ type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
+ \
+ static void glue(glue(ppc_, _name), _cpu_family_class_init)
+
/* PowerPC 401 */
#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
PPC_WRTEE | PPC_DCR | \
@@ -3267,7 +3289,6 @@ static int check_pow_hid0_74xx (CPUPPCState *env)
#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_401 check_pow_nocheck
static void init_proc_401 (CPUPPCState *env)
{
@@ -3284,6 +3305,14 @@ static void init_proc_401 (CPUPPCState *env)
SET_WDT_PERIOD(16, 20, 24, 28);
}
+POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_401;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 401x2 */
#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_DCR | PPC_WRTEE | \
@@ -3300,7 +3329,6 @@ static void init_proc_401 (CPUPPCState *env)
#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_401x2 check_pow_nocheck
static void init_proc_401x2 (CPUPPCState *env)
{
@@ -3325,6 +3353,14 @@ static void init_proc_401x2 (CPUPPCState *env)
SET_WDT_PERIOD(16, 20, 24, 28);
}
+POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_401x2;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 401x3 */
#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_DCR | PPC_WRTEE | \
@@ -3341,9 +3377,7 @@ static void init_proc_401x2 (CPUPPCState *env)
#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_401x3 check_pow_nocheck
-__attribute__ (( unused ))
static void init_proc_401x3 (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -3361,6 +3395,14 @@ static void init_proc_401x3 (CPUPPCState *env)
SET_WDT_PERIOD(16, 20, 24, 28);
}
+POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_401x3;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* IOP480 */
#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
PPC_DCR | PPC_WRTEE | \
@@ -3377,7 +3419,6 @@ static void init_proc_401x3 (CPUPPCState *env)
#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_IOP480 check_pow_nocheck
static void init_proc_IOP480 (CPUPPCState *env)
{
@@ -3402,6 +3443,14 @@ static void init_proc_IOP480 (CPUPPCState *env)
SET_WDT_PERIOD(16, 20, 24, 28);
}
+POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_IOP480;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 403 */
#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
PPC_DCR | PPC_WRTEE | \
@@ -3417,7 +3466,6 @@ static void init_proc_IOP480 (CPUPPCState *env)
#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_403 check_pow_nocheck
static void init_proc_403 (CPUPPCState *env)
{
@@ -3435,6 +3483,14 @@ static void init_proc_403 (CPUPPCState *env)
SET_WDT_PERIOD(16, 20, 24, 28);
}
+POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_403;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 403 GCX */
#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
PPC_DCR | PPC_WRTEE | \
@@ -3451,7 +3507,6 @@ static void init_proc_403 (CPUPPCState *env)
#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_403GCX check_pow_nocheck
static void init_proc_403GCX (CPUPPCState *env)
{
@@ -3488,6 +3543,14 @@ static void init_proc_403GCX (CPUPPCState *env)
SET_WDT_PERIOD(16, 20, 24, 28);
}
+POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_403GCX;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 405 */
#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_DCR | PPC_WRTEE | \
@@ -3504,7 +3567,6 @@ static void init_proc_403GCX (CPUPPCState *env)
#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-#define check_pow_405 check_pow_nocheck
static void init_proc_405 (CPUPPCState *env)
{
@@ -3540,6 +3602,14 @@ static void init_proc_405 (CPUPPCState *env)
SET_WDT_PERIOD(16, 20, 24, 28);
}
+POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_405;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 440 EP */
#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
@@ -3559,7 +3629,6 @@ static void init_proc_405 (CPUPPCState *env)
#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-#define check_pow_440EP check_pow_nocheck
static void init_proc_440EP (CPUPPCState *env)
{
@@ -3627,6 +3696,14 @@ static void init_proc_440EP (CPUPPCState *env)
SET_WDT_PERIOD(20, 24, 28, 32);
}
+POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_440EP;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 440 GP */
#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
@@ -3643,9 +3720,7 @@ static void init_proc_440EP (CPUPPCState *env)
#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-#define check_pow_440GP check_pow_nocheck
-__attribute__ (( unused ))
static void init_proc_440GP (CPUPPCState *env)
{
/* Time base */
@@ -3694,6 +3769,14 @@ static void init_proc_440GP (CPUPPCState *env)
SET_WDT_PERIOD(20, 24, 28, 32);
}
+POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_440GP;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 440x4 */
#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
PPC_DCR | PPC_WRTEE | \
@@ -3710,9 +3793,7 @@ static void init_proc_440GP (CPUPPCState *env)
#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-#define check_pow_440x4 check_pow_nocheck
-__attribute__ (( unused ))
static void init_proc_440x4 (CPUPPCState *env)
{
/* Time base */
@@ -3761,6 +3842,14 @@ static void init_proc_440x4 (CPUPPCState *env)
SET_WDT_PERIOD(20, 24, 28, 32);
}
+POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_440x4;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 440x5 */
#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
@@ -3777,7 +3866,6 @@ static void init_proc_440x4 (CPUPPCState *env)
#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-#define check_pow_440x5 check_pow_nocheck
static void init_proc_440x5 (CPUPPCState *env)
{
@@ -3845,6 +3933,14 @@ static void init_proc_440x5 (CPUPPCState *env)
SET_WDT_PERIOD(20, 24, 28, 32);
}
+POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_440x5;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 460 (guessed) */
#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
PPC_DCR | PPC_DCRX | PPC_DCRUX | \
@@ -3862,9 +3958,7 @@ static void init_proc_440x5 (CPUPPCState *env)
#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-#define check_pow_460 check_pow_nocheck
-__attribute__ (( unused ))
static void init_proc_460 (CPUPPCState *env)
{
/* Time base */
@@ -3936,6 +4030,14 @@ static void init_proc_460 (CPUPPCState *env)
SET_WDT_PERIOD(20, 24, 28, 32);
}
+POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_460;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 460F (guessed) */
#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
@@ -3956,9 +4058,7 @@ static void init_proc_460 (CPUPPCState *env)
#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-#define check_pow_460F check_pow_nocheck
-__attribute__ (( unused ))
static void init_proc_460F (CPUPPCState *env)
{
/* Time base */
@@ -4030,6 +4130,14 @@ static void init_proc_460F (CPUPPCState *env)
SET_WDT_PERIOD(20, 24, 28, 32);
}
+POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_460F;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* Freescale 5xx cores (aka RCPU) */
#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
PPC_MEM_EIEIO | PPC_MEM_SYNC | \
@@ -4043,9 +4151,7 @@ static void init_proc_460F (CPUPPCState *env)
#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_MPC5xx check_pow_none
-__attribute__ (( unused ))
static void init_proc_MPC5xx (CPUPPCState *env)
{
/* Time base */
@@ -4058,6 +4164,14 @@ static void init_proc_MPC5xx (CPUPPCState *env)
/* XXX: TODO: allocate internal IRQ controller */
}
+POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_MPC5xx;
+ pcc->check_pow = check_pow_none;
+}
+
/* Freescale 8xx cores (aka PowerQUICC) */
#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
PPC_MEM_EIEIO | PPC_MEM_SYNC | \
@@ -4070,9 +4184,7 @@ static void init_proc_MPC5xx (CPUPPCState *env)
#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_MPC8xx check_pow_none
-__attribute__ (( unused ))
static void init_proc_MPC8xx (CPUPPCState *env)
{
/* Time base */
@@ -4085,6 +4197,14 @@ static void init_proc_MPC8xx (CPUPPCState *env)
/* XXX: TODO: allocate internal IRQ controller */
}
+POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_MPC8xx;
+ pcc->check_pow = check_pow_none;
+}
+
/* Freescale 82xx cores (aka PowerQUICC-II) */
/* PowerPC G2 */
#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
@@ -4102,7 +4222,6 @@ static void init_proc_MPC8xx (CPUPPCState *env)
#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
-#define check_pow_G2 check_pow_hid0
static void init_proc_G2 (CPUPPCState *env)
{
@@ -4144,6 +4263,14 @@ static void init_proc_G2 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_G2;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC G2LE */
#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -4160,7 +4287,6 @@ static void init_proc_G2 (CPUPPCState *env)
#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
-#define check_pow_G2LE check_pow_hid0
static void init_proc_G2LE (CPUPPCState *env)
{
@@ -4202,6 +4328,14 @@ static void init_proc_G2LE (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_G2LE;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* e200 core */
/* XXX: unimplemented instructions:
* dcblc
@@ -4228,9 +4362,7 @@ static void init_proc_G2LE (CPUPPCState *env)
#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_e200 check_pow_hid0
-__attribute__ (( unused ))
static void init_proc_e200 (CPUPPCState *env)
{
/* Time base */
@@ -4338,6 +4470,14 @@ static void init_proc_e200 (CPUPPCState *env)
/* XXX: TODO: allocate internal IRQ controller */
}
+POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_e200;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* e300 core */
#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -4354,9 +4494,7 @@ static void init_proc_e200 (CPUPPCState *env)
#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
-#define check_pow_e300 check_pow_hid0
-__attribute__ (( unused ))
static void init_proc_e300 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -4390,6 +4528,14 @@ static void init_proc_e300 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_e300;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* e500v1 core */
#define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
PPC_SPE | PPC_SPE_SINGLE | \
@@ -4406,8 +4552,6 @@ static void init_proc_e300 (CPUPPCState *env)
#define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_e500v1 check_pow_hid0
-#define init_proc_e500v1 init_proc_e500v1
/* e500v2 core */
#define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
@@ -4425,8 +4569,6 @@ static void init_proc_e300 (CPUPPCState *env)
#define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_e500v2 check_pow_hid0
-#define init_proc_e500v2 init_proc_e500v2
/* e500mc core */
#define POWERPC_INSNS_e500mc (PPC_INSNS_BASE | PPC_ISEL | \
@@ -4446,8 +4588,6 @@ static void init_proc_e300 (CPUPPCState *env)
#define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500)
#define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_e500mc check_pow_none
-#define init_proc_e500mc init_proc_e500mc
/* e5500 core */
#define POWERPC_INSNS_e5500 (PPC_INSNS_BASE | PPC_ISEL | \
@@ -4468,8 +4608,6 @@ static void init_proc_e300 (CPUPPCState *env)
#define POWERPC_BFDM_e5500 (bfd_mach_ppc_e500)
#define POWERPC_FLAG_e5500 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_e5500 check_pow_none
-#define init_proc_e5500 init_proc_e5500
#if !defined(CONFIG_USER_ONLY)
static void spr_write_mas73(void *opaque, int sprn, int gprn)
@@ -4685,21 +4823,53 @@ static void init_proc_e500v1(CPUPPCState *env)
init_proc_e500(env, fsl_e500v1);
}
+POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_e500v1;
+ pcc->check_pow = check_pow_hid0;
+}
+
static void init_proc_e500v2(CPUPPCState *env)
{
init_proc_e500(env, fsl_e500v2);
}
+POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_e500v2;
+ pcc->check_pow = check_pow_hid0;
+}
+
static void init_proc_e500mc(CPUPPCState *env)
{
init_proc_e500(env, fsl_e500mc);
}
+POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_e500mc;
+ pcc->check_pow = check_pow_none;
+}
+
#ifdef TARGET_PPC64
static void init_proc_e5500(CPUPPCState *env)
{
init_proc_e500(env, fsl_e5500);
}
+
+POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_e5500;
+ pcc->check_pow = check_pow_none;
+}
#endif
/* Non-embedded PowerPC */
@@ -4725,7 +4895,6 @@ static void init_proc_e5500(CPUPPCState *env)
#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
-#define check_pow_601 check_pow_none
static void init_proc_601 (CPUPPCState *env)
{
@@ -4764,6 +4933,14 @@ static void init_proc_601 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_601;
+ pcc->check_pow = check_pow_none;
+}
+
/* PowerPC 601v */
#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
PPC_FLOAT | \
@@ -4778,7 +4955,6 @@ static void init_proc_601 (CPUPPCState *env)
#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
-#define check_pow_601v check_pow_none
static void init_proc_601v (CPUPPCState *env)
{
@@ -4790,6 +4966,14 @@ static void init_proc_601v (CPUPPCState *env)
0x00000000);
}
+POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_601v;
+ pcc->check_pow = check_pow_none;
+}
+
/* PowerPC 602 */
#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -4807,7 +4991,6 @@ static void init_proc_601v (CPUPPCState *env)
#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
-#define check_pow_602 check_pow_hid0
static void init_proc_602 (CPUPPCState *env)
{
@@ -4836,6 +5019,14 @@ static void init_proc_602 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_602;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC 603 */
#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -4852,7 +5043,6 @@ static void init_proc_602 (CPUPPCState *env)
#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
-#define check_pow_603 check_pow_hid0
static void init_proc_603 (CPUPPCState *env)
{
@@ -4881,6 +5071,14 @@ static void init_proc_603 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_603;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC 603e */
#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -4897,7 +5095,6 @@ static void init_proc_603 (CPUPPCState *env)
#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
-#define check_pow_603E check_pow_hid0
static void init_proc_603E (CPUPPCState *env)
{
@@ -4931,6 +5128,14 @@ static void init_proc_603E (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_603E;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC 604 */
#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -4947,7 +5152,6 @@ static void init_proc_603E (CPUPPCState *env)
#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_604 check_pow_nocheck
static void init_proc_604 (CPUPPCState *env)
{
@@ -4970,6 +5174,14 @@ static void init_proc_604 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_604;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 604E */
#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -4986,7 +5198,6 @@ static void init_proc_604 (CPUPPCState *env)
#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_604E check_pow_nocheck
static void init_proc_604E (CPUPPCState *env)
{
@@ -5029,6 +5240,14 @@ static void init_proc_604E (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_604E;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 740 */
#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -5045,7 +5264,6 @@ static void init_proc_604E (CPUPPCState *env)
#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_740 check_pow_hid0
static void init_proc_740 (CPUPPCState *env)
{
@@ -5075,6 +5293,14 @@ static void init_proc_740 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_740;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC 750 */
#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -5091,7 +5317,6 @@ static void init_proc_740 (CPUPPCState *env)
#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_750 check_pow_hid0
static void init_proc_750 (CPUPPCState *env)
{
@@ -5129,6 +5354,14 @@ static void init_proc_750 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_750;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC 750 CL */
/* XXX: not implemented:
* cache lock instructions:
@@ -5183,7 +5416,6 @@ static void init_proc_750 (CPUPPCState *env)
#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_750cl check_pow_hid0
static void init_proc_750cl (CPUPPCState *env)
{
@@ -5306,6 +5538,14 @@ static void init_proc_750cl (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_750cl;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC 750CX */
#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -5322,7 +5562,6 @@ static void init_proc_750cl (CPUPPCState *env)
#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_750cx check_pow_hid0
static void init_proc_750cx (CPUPPCState *env)
{
@@ -5364,6 +5603,14 @@ static void init_proc_750cx (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_750cx;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC 750FX */
#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -5380,7 +5627,6 @@ static void init_proc_750cx (CPUPPCState *env)
#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_750fx check_pow_hid0
static void init_proc_750fx (CPUPPCState *env)
{
@@ -5427,6 +5673,14 @@ static void init_proc_750fx (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_750fx;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC 750GX */
#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -5443,7 +5697,6 @@ static void init_proc_750fx (CPUPPCState *env)
#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_750gx check_pow_hid0
static void init_proc_750gx (CPUPPCState *env)
{
@@ -5490,6 +5743,14 @@ static void init_proc_750gx (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_750gx;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC 745 */
#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -5506,7 +5767,6 @@ static void init_proc_750gx (CPUPPCState *env)
#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_745 check_pow_hid0
static void init_proc_745 (CPUPPCState *env)
{
@@ -5544,6 +5804,14 @@ static void init_proc_745 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_745;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC 755 */
#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -5560,7 +5828,6 @@ static void init_proc_745 (CPUPPCState *env)
#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_755 check_pow_hid0
static void init_proc_755 (CPUPPCState *env)
{
@@ -5609,6 +5876,14 @@ static void init_proc_755 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_755;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC 7400 (aka G4) */
#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -5630,7 +5905,6 @@ static void init_proc_755 (CPUPPCState *env)
#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_7400 check_pow_hid0
static void init_proc_7400 (CPUPPCState *env)
{
@@ -5662,6 +5936,14 @@ static void init_proc_7400 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_7400;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC 7410 (aka G4) */
#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -5683,7 +5965,6 @@ static void init_proc_7400 (CPUPPCState *env)
#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_7410 check_pow_hid0
static void init_proc_7410 (CPUPPCState *env)
{
@@ -5721,6 +6002,14 @@ static void init_proc_7410 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_7410;
+ pcc->check_pow = check_pow_hid0;
+}
+
/* PowerPC 7440 (aka G4) */
#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -5742,9 +6031,7 @@ static void init_proc_7410 (CPUPPCState *env)
#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_7440 check_pow_hid0_74xx
-__attribute__ (( unused ))
static void init_proc_7440 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5807,6 +6094,14 @@ static void init_proc_7440 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_7440;
+ pcc->check_pow = check_pow_hid0_74xx;
+}
+
/* PowerPC 7450 (aka G4) */
#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -5828,9 +6123,7 @@ static void init_proc_7440 (CPUPPCState *env)
#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_7450 check_pow_hid0_74xx
-__attribute__ (( unused ))
static void init_proc_7450 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5919,6 +6212,14 @@ static void init_proc_7450 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_7450;
+ pcc->check_pow = check_pow_hid0_74xx;
+}
+
/* PowerPC 7445 (aka G4) */
#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -5940,9 +6241,7 @@ static void init_proc_7450 (CPUPPCState *env)
#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_7445 check_pow_hid0_74xx
-__attribute__ (( unused ))
static void init_proc_7445 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6034,6 +6333,14 @@ static void init_proc_7445 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_7445;
+ pcc->check_pow = check_pow_hid0_74xx;
+}
+
/* PowerPC 7455 (aka G4) */
#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -6055,9 +6362,7 @@ static void init_proc_7445 (CPUPPCState *env)
#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_7455 check_pow_hid0_74xx
-__attribute__ (( unused ))
static void init_proc_7455 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6151,6 +6456,14 @@ static void init_proc_7455 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_7455;
+ pcc->check_pow = check_pow_hid0_74xx;
+}
+
/* PowerPC 7457 (aka G4) */
#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -6172,9 +6485,7 @@ static void init_proc_7455 (CPUPPCState *env)
#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_7457 check_pow_hid0_74xx
-__attribute__ (( unused ))
static void init_proc_7457 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6292,6 +6603,14 @@ static void init_proc_7457 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
+POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_7457;
+ pcc->check_pow = check_pow_hid0_74xx;
+}
+
#if defined (TARGET_PPC64)
/* PowerPC 970 */
#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
@@ -6389,6 +6708,14 @@ static void init_proc_970 (CPUPPCState *env)
vscr_init(env, 0x00010000);
}
+POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_970;
+ pcc->check_pow = check_pow_970;
+}
+
/* PowerPC 970FX (aka G5) */
#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -6491,6 +6818,14 @@ static void init_proc_970FX (CPUPPCState *env)
vscr_init(env, 0x00010000);
}
+POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_970FX;
+ pcc->check_pow = check_pow_970FX;
+}
+
/* PowerPC 970 GX */
#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -6581,6 +6916,14 @@ static void init_proc_970GX (CPUPPCState *env)
vscr_init(env, 0x00010000);
}
+POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_970GX;
+ pcc->check_pow = check_pow_970GX;
+}
+
/* PowerPC 970 MP */
#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -6671,6 +7014,14 @@ static void init_proc_970MP (CPUPPCState *env)
vscr_init(env, 0x00010000);
}
+POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_970MP;
+ pcc->check_pow = check_pow_970MP;
+}
+
/* POWER7 */
#define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -6691,7 +7042,6 @@ static void init_proc_970MP (CPUPPCState *env)
#define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
-#define check_pow_POWER7 check_pow_nocheck
static void init_proc_POWER7 (CPUPPCState *env)
{
@@ -6755,6 +7105,14 @@ static void init_proc_POWER7 (CPUPPCState *env)
vscr_init(env, 0x00010000);
}
+POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_POWER7;
+ pcc->check_pow = check_pow_nocheck;
+}
+
/* PowerPC 620 */
#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
@@ -6773,9 +7131,7 @@ static void init_proc_POWER7 (CPUPPCState *env)
#define POWERPC_BFDM_620 (bfd_mach_ppc64)
#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_620 check_pow_nocheck /* Check this */
-__attribute__ (( unused ))
static void init_proc_620 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6796,6 +7152,15 @@ static void init_proc_620 (CPUPPCState *env)
/* Allocate hardware IRQ controller */
ppc6xx_irq_init(env);
}
+
+POWERPC_FAMILY(620)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->init_proc = init_proc_620;
+ pcc->check_pow = check_pow_nocheck; /* Check this */
+}
+
#endif /* defined (TARGET_PPC64) */
/*****************************************************************************/
@@ -7530,14 +7895,12 @@ enum {
pcc->bus_model = glue(POWERPC_INPUT_, _type); \
pcc->bfd_mach = glue(POWERPC_BFDM_, _type); \
pcc->flags = glue(POWERPC_FLAG_, _type); \
- pcc->init_proc = &glue(init_proc_, _type); \
- pcc->check_pow = &glue(check_pow_, _type); \
} \
\
static const TypeInfo \
glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info) = { \
.name = _name "-" TYPE_POWERPC_CPU, \
- .parent = TYPE_POWERPC_CPU, \
+ .parent = stringify(_type) "-family-" TYPE_POWERPC_CPU, \
.class_init = \
glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init), \
}; \
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 46/66] target-ppc: Set instruction flags on CPU family classes
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (44 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 45/66] target-ppc: Introduce abstract CPU family types Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 47/66] target-ppc: Register all types for TARGET_PPCEMB Alexander Graf
` (20 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 994 ++++++++++++++++++++++---------------------
1 files changed, 499 insertions(+), 495 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index c300aa8..06df161 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3275,13 +3275,6 @@ static int check_pow_hid0_74xx (CPUPPCState *env)
static void glue(glue(ppc_, _name), _cpu_family_class_init)
/* PowerPC 401 */
-#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
- PPC_WRTEE | PPC_DCR | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
- PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_4xx_COMMON | PPC_40x_EXCP)
-#define POWERPC_INSNS2_401 (PPC_NONE)
#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
@@ -3311,17 +3304,16 @@ POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_401;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_WRTEE | PPC_DCR |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_4xx_COMMON | PPC_40x_EXCP;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 401x2 */
-#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_DCR | PPC_WRTEE | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_4xx_COMMON | PPC_40x_EXCP)
-#define POWERPC_INSNS2_401x2 (PPC_NONE)
#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
@@ -3359,17 +3351,17 @@ POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_401x2;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
+ PPC_4xx_COMMON | PPC_40x_EXCP;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 401x3 */
-#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_DCR | PPC_WRTEE | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_4xx_COMMON | PPC_40x_EXCP)
-#define POWERPC_INSNS2_401x3 (PPC_NONE)
#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
@@ -3401,17 +3393,17 @@ POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_401x3;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
+ PPC_4xx_COMMON | PPC_40x_EXCP;
+ pcc->insns_flags2 = PPC_NONE;
}
/* IOP480 */
-#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
- PPC_DCR | PPC_WRTEE | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_4xx_COMMON | PPC_40x_EXCP)
-#define POWERPC_INSNS2_IOP480 (PPC_NONE)
#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
@@ -3449,16 +3441,17 @@ POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_IOP480;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
+ PPC_4xx_COMMON | PPC_40x_EXCP;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 403 */
-#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
- PPC_DCR | PPC_WRTEE | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
- PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_4xx_COMMON | PPC_40x_EXCP)
-#define POWERPC_INSNS2_403 (PPC_NONE)
#define POWERPC_MSRM_403 (0x000000000007D00DULL)
#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
@@ -3489,17 +3482,16 @@ POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_403;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_4xx_COMMON | PPC_40x_EXCP;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 403 GCX */
-#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
- PPC_DCR | PPC_WRTEE | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
- PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_4xx_COMMON | PPC_40x_EXCP)
-#define POWERPC_INSNS2_403GCX (PPC_NONE)
#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
@@ -3549,17 +3541,17 @@ POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_403GCX;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
+ PPC_4xx_COMMON | PPC_40x_EXCP;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 405 */
-#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_DCR | PPC_WRTEE | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
-#define POWERPC_INSNS2_405 (PPC_NONE)
#define POWERPC_MSRM_405 (0x000000000006E630ULL)
#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
@@ -3608,20 +3600,17 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_405;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
+ PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 440 EP */
-#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
- PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_TLBSYNC | PPC_MFTB | \
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
- PPC_440_SPEC)
-#define POWERPC_INSNS2_440EP (PPC_NONE)
#define POWERPC_MSRM_440EP (0x000000000006FF30ULL)
#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
@@ -3702,17 +3691,20 @@ POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_440EP;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_DCR | PPC_WRTEE | PPC_RFMCI |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_MFTB |
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
+ PPC_440_SPEC;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 440 GP */
-#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
- PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
- PPC_440_SPEC)
-#define POWERPC_INSNS2_440GP (PPC_NONE)
#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
@@ -3775,17 +3767,17 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_440GP;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
+ PPC_440_SPEC;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 440x4 */
-#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
- PPC_DCR | PPC_WRTEE | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_TLBSYNC | PPC_MFTB | \
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
- PPC_440_SPEC)
-#define POWERPC_INSNS2_440x4 (PPC_NONE)
#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
@@ -3848,17 +3840,17 @@ POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_440x4;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_MFTB |
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
+ PPC_440_SPEC;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 440x5 */
-#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
- PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_TLBSYNC | PPC_MFTB | \
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
- PPC_440_SPEC)
-#define POWERPC_INSNS2_440x5 (PPC_NONE)
#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
@@ -3939,18 +3931,17 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_440x5;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_DCR | PPC_WRTEE | PPC_RFMCI |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_MFTB |
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
+ PPC_440_SPEC;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 460 (guessed) */
-#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
- PPC_DCR | PPC_DCRX | PPC_DCRUX | \
- PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_TLBSYNC | PPC_TLBIVA | \
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
- PPC_440_SPEC)
-#define POWERPC_INSNS2_460 (PPC_NONE)
#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
@@ -4036,21 +4027,18 @@ POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_460;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_DCR | PPC_DCRX | PPC_DCRUX |
+ PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_TLBIVA |
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
+ PPC_440_SPEC;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 460F (guessed) */
-#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
- PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | PPC_MFTB | \
- PPC_DCR | PPC_DCRX | PPC_DCRUX | \
- PPC_WRTEE | PPC_MFAPIDI | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_TLBSYNC | PPC_TLBIVA | \
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
- PPC_440_SPEC)
-#define POWERPC_INSNS2_460F (PPC_NONE)
#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
@@ -4136,14 +4124,21 @@ POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_460F;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX | PPC_MFTB |
+ PPC_DCR | PPC_DCRX | PPC_DCRUX |
+ PPC_WRTEE | PPC_MFAPIDI |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_TLBIVA |
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
+ PPC_440_SPEC;
+ pcc->insns_flags2 = PPC_NONE;
}
/* Freescale 5xx cores (aka RCPU) */
-#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
- PPC_MEM_EIEIO | PPC_MEM_SYNC | \
- PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
- PPC_MFTB)
-#define POWERPC_INSNS2_MPC5xx (PPC_NONE)
#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
@@ -4170,13 +4165,14 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_MPC5xx;
pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_MEM_EIEIO | PPC_MEM_SYNC |
+ PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
+ PPC_MFTB;
+ pcc->insns_flags2 = PPC_NONE;
}
/* Freescale 8xx cores (aka PowerQUICC) */
-#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
- PPC_MEM_EIEIO | PPC_MEM_SYNC | \
- PPC_CACHE_ICBI | PPC_MFTB)
-#define POWERPC_INSNS2_MPC8xx (PPC_NONE)
#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
@@ -4203,18 +4199,14 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_MPC8xx;
pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_MEM_EIEIO | PPC_MEM_SYNC |
+ PPC_CACHE_ICBI | PPC_MFTB;
+ pcc->insns_flags2 = PPC_NONE;
}
/* Freescale 82xx cores (aka PowerQUICC-II) */
/* PowerPC G2 */
-#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_G2 (PPC_NONE)
#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
@@ -4269,17 +4261,17 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_G2;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC G2LE */
-#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_G2LE (PPC_NONE)
#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
@@ -4334,26 +4326,17 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_G2LE;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* e200 core */
-/* XXX: unimplemented instructions:
- * dcblc
- * dcbtlst
- * dcbtstls
- * icblc
- * icbtls
- * tlbivax
- * all SPE multiply-accumulate instructions
- */
-#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
- PPC_SPE | PPC_SPE_SINGLE | \
- PPC_WRTEE | PPC_RFDI | \
- PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
- PPC_BOOKE)
-#define POWERPC_INSNS2_e200 (PPC_NONE)
#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
@@ -4476,17 +4459,26 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_e200;
pcc->check_pow = check_pow_hid0;
+ /* XXX: unimplemented instructions:
+ * dcblc
+ * dcbtlst
+ * dcbtstls
+ * icblc
+ * icbtls
+ * tlbivax
+ * all SPE multiply-accumulate instructions
+ */
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
+ PPC_SPE | PPC_SPE_SINGLE |
+ PPC_WRTEE | PPC_RFDI |
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX |
+ PPC_BOOKE;
+ pcc->insns_flags2 = PPC_NONE;
}
/* e300 core */
-#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_e300 (PPC_NONE)
#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
@@ -4534,16 +4526,17 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_e300;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* e500v1 core */
-#define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
- PPC_SPE | PPC_SPE_SINGLE | \
- PPC_WRTEE | PPC_RFDI | \
- PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
-#define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
#define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
@@ -4554,13 +4547,6 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK)
/* e500v2 core */
-#define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
- PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
- PPC_WRTEE | PPC_RFDI | \
- PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
-#define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
#define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
@@ -4571,15 +4557,6 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK)
/* e500mc core */
-#define POWERPC_INSNS_e500mc (PPC_INSNS_BASE | PPC_ISEL | \
- PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
- PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_FLOAT | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
- PPC_FLOAT_STFIWX | PPC_WAIT | \
- PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
-#define POWERPC_INSNS2_e500mc (PPC2_BOOKE206 | PPC2_PRCNTL)
#define POWERPC_MSRM_e500mc (0x000000001402FB36ULL)
#define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)
#define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE)
@@ -4590,16 +4567,6 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
/* e5500 core */
-#define POWERPC_INSNS_e5500 (PPC_INSNS_BASE | PPC_ISEL | \
- PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
- PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_FLOAT | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
- PPC_FLOAT_STFIWX | PPC_WAIT | \
- PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | \
- PPC_64B | PPC_POPCNTB | PPC_POPCNTWD)
-#define POWERPC_INSNS2_e5500 (PPC2_BOOKE206 | PPC2_PRCNTL)
#define POWERPC_MSRM_e5500 (0x000000009402FB36ULL)
#define POWERPC_MMU_e5500 (POWERPC_MMU_BOOKE206)
#define POWERPC_EXCP_e5500 (POWERPC_EXCP_BOOKE)
@@ -4829,6 +4796,13 @@ POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_e500v1;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
+ PPC_SPE | PPC_SPE_SINGLE |
+ PPC_WRTEE | PPC_RFDI |
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
+ pcc->insns_flags2 = PPC2_BOOKE206;
}
static void init_proc_e500v2(CPUPPCState *env)
@@ -4842,6 +4816,13 @@ POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_e500v2;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
+ PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
+ PPC_WRTEE | PPC_RFDI |
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
+ pcc->insns_flags2 = PPC2_BOOKE206;
}
static void init_proc_e500mc(CPUPPCState *env)
@@ -4855,6 +4836,15 @@ POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_e500mc;
pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
+ PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_FLOAT | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
+ PPC_FLOAT_STFIWX | PPC_WAIT |
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
+ pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
}
#ifdef TARGET_PPC64
@@ -4869,6 +4859,16 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_e5500;
pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
+ PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_FLOAT | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
+ PPC_FLOAT_STFIWX | PPC_WAIT |
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
+ PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
+ pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
}
#endif
@@ -4876,18 +4876,18 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
/* POWER : same as 601, without mfmsr, mfsr */
#if defined(TODO)
-#define POWERPC_INSNS_POWER (XXX_TODO)
/* POWER RSC (from RAD6000) */
#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
+
+POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ pcc->insns_flags = XXX_TODO;
+}
#endif /* TODO */
/* PowerPC 601 */
-#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
- PPC_FLOAT | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_601 (PPC_NONE)
#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
#define POWERPC_MSRR_601 (0x0000000000001040ULL)
//#define POWERPC_MMU_601 (POWERPC_MMU_601)
@@ -4939,15 +4939,15 @@ POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_601;
pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
+ PPC_FLOAT |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 601v */
-#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
- PPC_FLOAT | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_601v (PPC_NONE)
#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
#define POWERPC_MSRR_601v (0x0000000000001040ULL)
#define POWERPC_MMU_601v (POWERPC_MMU_601)
@@ -4972,17 +4972,15 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_601v;
pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
+ PPC_FLOAT |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 602 */
-#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
- PPC_SEGMENT | PPC_602_SPEC)
-#define POWERPC_INSNS2_602 (PPC_NONE)
#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
/* XXX: 602 MMU is quite specific. Should add a special case */
#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
@@ -5025,17 +5023,17 @@ POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_602;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_602_SPEC;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 603 */
-#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_603 (PPC_NONE)
#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
@@ -5077,17 +5075,17 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_603;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 603e */
-#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_603E (PPC_NONE)
#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
@@ -5134,17 +5132,17 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_603E;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 604 */
-#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_604 (PPC_NONE)
#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
#define POWERPC_MMU_604 (POWERPC_MMU_32B)
//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
@@ -5180,17 +5178,17 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_604;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 604E */
-#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_604E (PPC_NONE)
#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
#define POWERPC_MMU_604E (POWERPC_MMU_32B)
#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
@@ -5246,17 +5244,17 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_604E;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 740 */
-#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_740 (PPC_NONE)
#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
#define POWERPC_MMU_740 (POWERPC_MMU_32B)
#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
@@ -5299,17 +5297,17 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_740;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 750 */
-#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_750 (PPC_NONE)
#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
#define POWERPC_MMU_750 (POWERPC_MMU_32B)
#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
@@ -5360,55 +5358,17 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_750;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 750 CL */
-/* XXX: not implemented:
- * cache lock instructions:
- * dcbz_l
- * floating point paired instructions
- * psq_lux
- * psq_lx
- * psq_stux
- * psq_stx
- * ps_abs
- * ps_add
- * ps_cmpo0
- * ps_cmpo1
- * ps_cmpu0
- * ps_cmpu1
- * ps_div
- * ps_madd
- * ps_madds0
- * ps_madds1
- * ps_merge00
- * ps_merge01
- * ps_merge10
- * ps_merge11
- * ps_mr
- * ps_msub
- * ps_mul
- * ps_muls0
- * ps_muls1
- * ps_nabs
- * ps_neg
- * ps_nmadd
- * ps_nmsub
- * ps_res
- * ps_rsqrte
- * ps_sel
- * ps_sub
- * ps_sum0
- * ps_sum1
- */
-#define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_750cl (PPC_NONE)
#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
@@ -5544,17 +5504,55 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_750cl;
pcc->check_pow = check_pow_hid0;
+ /* XXX: not implemented:
+ * cache lock instructions:
+ * dcbz_l
+ * floating point paired instructions
+ * psq_lux
+ * psq_lx
+ * psq_stux
+ * psq_stx
+ * ps_abs
+ * ps_add
+ * ps_cmpo0
+ * ps_cmpo1
+ * ps_cmpu0
+ * ps_cmpu1
+ * ps_div
+ * ps_madd
+ * ps_madds0
+ * ps_madds1
+ * ps_merge00
+ * ps_merge01
+ * ps_merge10
+ * ps_merge11
+ * ps_mr
+ * ps_msub
+ * ps_mul
+ * ps_muls0
+ * ps_muls1
+ * ps_nabs
+ * ps_neg
+ * ps_nmadd
+ * ps_nmsub
+ * ps_res
+ * ps_rsqrte
+ * ps_sel
+ * ps_sub
+ * ps_sum0
+ * ps_sum1
+ */
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 750CX */
-#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_750cx (PPC_NONE)
#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
@@ -5609,17 +5607,17 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_750cx;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 750FX */
-#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_750fx (PPC_NONE)
#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
@@ -5679,17 +5677,17 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_750fx;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 750GX */
-#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_750gx (PPC_NONE)
#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
@@ -5749,17 +5747,17 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_750gx;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 745 */
-#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_745 (PPC_NONE)
#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
@@ -5810,17 +5808,17 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_745;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 755 */
-#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
- PPC_SEGMENT | PPC_EXTERN)
-#define POWERPC_INSNS2_755 (PPC_NONE)
#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
@@ -5882,21 +5880,17 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_755;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 7400 (aka G4) */
-#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_MEM_TLBIA | \
- PPC_SEGMENT | PPC_EXTERN | \
- PPC_ALTIVEC)
-#define POWERPC_INSNS2_7400 (PPC_NONE)
#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
@@ -5942,21 +5936,21 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_7400;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 7410 (aka G4) */
-#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_MEM_TLBIA | \
- PPC_SEGMENT | PPC_EXTERN | \
- PPC_ALTIVEC)
-#define POWERPC_INSNS2_7410 (PPC_NONE)
#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
@@ -6008,21 +6002,21 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_7410;
pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 7440 (aka G4) */
-#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_MEM_TLBIA | PPC_74xx_TLB | \
- PPC_SEGMENT | PPC_EXTERN | \
- PPC_ALTIVEC)
-#define POWERPC_INSNS2_7440 (PPC_NONE)
#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
@@ -6100,21 +6094,21 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_7440;
pcc->check_pow = check_pow_hid0_74xx;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 7450 (aka G4) */
-#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_MEM_TLBIA | PPC_74xx_TLB | \
- PPC_SEGMENT | PPC_EXTERN | \
- PPC_ALTIVEC)
-#define POWERPC_INSNS2_7450 (PPC_NONE)
#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
@@ -6218,21 +6212,21 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_7450;
pcc->check_pow = check_pow_hid0_74xx;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 7445 (aka G4) */
-#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_MEM_TLBIA | PPC_74xx_TLB | \
- PPC_SEGMENT | PPC_EXTERN | \
- PPC_ALTIVEC)
-#define POWERPC_INSNS2_7445 (PPC_NONE)
#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
@@ -6339,21 +6333,21 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_7445;
pcc->check_pow = check_pow_hid0_74xx;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 7455 (aka G4) */
-#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_MEM_TLBIA | PPC_74xx_TLB | \
- PPC_SEGMENT | PPC_EXTERN | \
- PPC_ALTIVEC)
-#define POWERPC_INSNS2_7455 (PPC_NONE)
#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
@@ -6462,21 +6456,21 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_7455;
pcc->check_pow = check_pow_hid0_74xx;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 7457 (aka G4) */
-#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_MEM_TLBIA | PPC_74xx_TLB | \
- PPC_SEGMENT | PPC_EXTERN | \
- PPC_ALTIVEC)
-#define POWERPC_INSNS2_7457 (PPC_NONE)
#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
@@ -6609,20 +6603,22 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_7457;
pcc->check_pow = check_pow_hid0_74xx;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->insns_flags2 = PPC_NONE;
}
#if defined (TARGET_PPC64)
/* PowerPC 970 */
-#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_64B | PPC_ALTIVEC | \
- PPC_SEGMENT_64B | PPC_SLBI)
-#define POWERPC_INSNS2_970 (PPC_NONE)
#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
#define POWERPC_MMU_970 (POWERPC_MMU_64B)
//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
@@ -6714,19 +6710,19 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_970;
pcc->check_pow = check_pow_970;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_64B | PPC_ALTIVEC |
+ PPC_SEGMENT_64B | PPC_SLBI;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 970FX (aka G5) */
-#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_64B | PPC_ALTIVEC | \
- PPC_SEGMENT_64B | PPC_SLBI)
-#define POWERPC_INSNS2_970FX (PPC_NONE)
#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
@@ -6824,19 +6820,19 @@ POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_970FX;
pcc->check_pow = check_pow_970FX;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_64B | PPC_ALTIVEC |
+ PPC_SEGMENT_64B | PPC_SLBI;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 970 GX */
-#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_64B | PPC_ALTIVEC | \
- PPC_SEGMENT_64B | PPC_SLBI)
-#define POWERPC_INSNS2_970GX (PPC_NONE)
#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
@@ -6922,19 +6918,19 @@ POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_970GX;
pcc->check_pow = check_pow_970GX;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_64B | PPC_ALTIVEC |
+ PPC_SEGMENT_64B | PPC_SLBI;
+ pcc->insns_flags2 = PPC_NONE;
}
/* PowerPC 970 MP */
-#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_64B | PPC_ALTIVEC | \
- PPC_SEGMENT_64B | PPC_SLBI)
-#define POWERPC_INSNS2_970MP (PPC_NONE)
#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
@@ -7020,20 +7016,19 @@ POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_970MP;
pcc->check_pow = check_pow_970MP;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_64B | PPC_ALTIVEC |
+ PPC_SEGMENT_64B | PPC_SLBI;
+ pcc->insns_flags2 = PPC_NONE;
}
/* POWER7 */
-#define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_64B | PPC_ALTIVEC | \
- PPC_SEGMENT_64B | PPC_SLBI | \
- PPC_POPCNTB | PPC_POPCNTWD)
-#define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP | PPC2_DBRX)
#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
@@ -7111,19 +7106,20 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_POWER7;
pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_64B | PPC_ALTIVEC |
+ PPC_SEGMENT_64B | PPC_SLBI |
+ PPC_POPCNTB | PPC_POPCNTWD;
+ pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
}
/* PowerPC 620 */
-#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_SEGMENT | PPC_EXTERN | \
- PPC_64B | PPC_SLBI)
-#define POWERPC_INSNS2_620 (PPC_NONE)
#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
//#define POWERPC_MMU_620 (POWERPC_MMU_620)
#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
@@ -7159,6 +7155,16 @@ POWERPC_FAMILY(620)(ObjectClass *oc, void *data)
pcc->init_proc = init_proc_620;
pcc->check_pow = check_pow_nocheck; /* Check this */
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_64B | PPC_SLBI;
+ pcc->insns_flags2 = PPC_NONE;
}
#endif /* defined (TARGET_PPC64) */
@@ -7887,8 +7893,6 @@ enum {
\
pcc->pvr = _pvr; \
pcc->svr = _svr; \
- pcc->insns_flags = glue(POWERPC_INSNS_, _type); \
- pcc->insns_flags2 = glue(POWERPC_INSNS2_, _type); \
pcc->msr_mask = glue(POWERPC_MSRM_, _type); \
pcc->mmu_model = glue(POWERPC_MMU_, _type); \
pcc->excp_model = glue(POWERPC_EXCP_, _type); \
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 47/66] target-ppc: Register all types for TARGET_PPCEMB
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (45 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 46/66] target-ppc: Set instruction flags on CPU family classes Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 48/66] target-ppc: Set remaining fields on CPU family classes Alexander Graf
` (19 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Don't attempt to suppress registration of CPU types, since the criteria
is actually a property of the class and should thus become a field.
Since we can't check a field set in a class_init function before
registering the type that leads to execution of that function, guard the
-cpu class lookup instead and suppress exposing these classes in -cpu ?
and in QMP.
In case someone tries to hot-add an incompatible CPU via device_add,
error out in realize.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 43 ++++++++++++++++++++++++++++++++++---------
1 files changed, 34 insertions(+), 9 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 06df161..ca56028 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7876,14 +7876,6 @@ enum {
/* PowerPC CPU definitions */
#define POWERPC_DEF_PREFIX(pvr, svr, type) \
glue(glue(glue(glue(pvr, _), svr), _), type)
-#if defined(TARGET_PPCEMB)
-#define POWERPC_DEF_CONDITION(type) \
- if (glue(POWERPC_MMU_, type) != POWERPC_MMU_BOOKE) { \
- return; \
- }
-#else
-#define POWERPC_DEF_CONDITION(type)
-#endif
#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
static void \
glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init) \
@@ -7912,7 +7904,6 @@ enum {
static void \
glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types)(void) \
{ \
- POWERPC_DEF_CONDITION(_type) \
type_register_static( \
&glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info)); \
} \
@@ -10040,6 +10031,15 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
}
}
+#if defined(TARGET_PPCEMB)
+ if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
+ error_setg(errp, "CPU does not possess a BookE MMU. "
+ "Please use qemu-system-ppc or qemu-system-ppc64 instead "
+ "or choose another CPU model.");
+ return;
+ }
+#endif
+
create_ppc_opcodes(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
@@ -10239,6 +10239,12 @@ static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
return -1;
}
+#if defined(TARGET_PPCEMB)
+ if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
+ return -1;
+ }
+#endif
+
return pcc->pvr == pvr ? 0 : -1;
}
@@ -10261,8 +10267,14 @@ static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
{
ObjectClass *oc = (ObjectClass *)a;
const char *name = b;
+#if defined(TARGET_PPCEMB)
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+#endif
if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
+#if defined(TARGET_PPCEMB)
+ pcc->mmu_model == POWERPC_MMU_BOOKE &&
+#endif
strcmp(object_class_get_name(oc) + strlen(name),
"-" TYPE_POWERPC_CPU) == 0) {
return 0;
@@ -10381,6 +10393,12 @@ static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
const char *typename = object_class_get_name(oc);
char *name;
+#if defined(TARGET_PPCEMB)
+ if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
+ return;
+ }
+#endif
+
name = g_strndup(typename,
strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
(*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
@@ -10421,6 +10439,13 @@ static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
const char *typename;
CpuDefinitionInfoList *entry;
CpuDefinitionInfo *info;
+#if defined(TARGET_PPCEMB)
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
+ return;
+ }
+#endif
typename = object_class_get_name(oc);
info = g_malloc0(sizeof(*info));
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 48/66] target-ppc: Set remaining fields on CPU family classes
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (46 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 47/66] target-ppc: Register all types for TARGET_PPCEMB Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 49/66] target-ppc: Turn descriptive CPU family comments into device descriptions Alexander Graf
` (18 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Now POWERPC_DEF_SVR() no longer sets family-specific fields itself.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 805 ++++++++++++++++++++-----------------------
1 files changed, 375 insertions(+), 430 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index ca56028..eea9adf 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3275,14 +3275,6 @@ static int check_pow_hid0_74xx (CPUPPCState *env)
static void glue(glue(ppc_, _name), _cpu_family_class_init)
/* PowerPC 401 */
-#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
-#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
-#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
-#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
-#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_401 (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -3311,17 +3303,16 @@ POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_4xx_COMMON | PPC_40x_EXCP;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x00000000000FD201ULL;
+ pcc->mmu_model = POWERPC_MMU_REAL;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_401;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 401x2 */
-#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
-#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
-#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
-#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
-#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_401x2 (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -3359,17 +3350,16 @@ POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
PPC_4xx_COMMON | PPC_40x_EXCP;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x00000000001FD231ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_401;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 401x3 */
-#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
-#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
-#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
-#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
-#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_401x3 (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -3401,17 +3391,16 @@ POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
PPC_4xx_COMMON | PPC_40x_EXCP;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x00000000001FD631ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_401;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
}
/* IOP480 */
-#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
-#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
-#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
-#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
-#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_IOP480 (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -3449,17 +3438,16 @@ POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
PPC_4xx_COMMON | PPC_40x_EXCP;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x00000000001FD231ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_401;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 403 */
-#define POWERPC_MSRM_403 (0x000000000007D00DULL)
-#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
-#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
-#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
-#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_403 (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -3489,17 +3477,16 @@ POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_4xx_COMMON | PPC_40x_EXCP;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000007D00DULL;
+ pcc->mmu_model = POWERPC_MMU_REAL;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_401;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 403 GCX */
-#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
-#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
-#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
-#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
-#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
-#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_403GCX (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -3549,17 +3536,16 @@ POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
PPC_4xx_COMMON | PPC_40x_EXCP;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000007D00DULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_401;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 405 */
-#define POWERPC_MSRM_405 (0x000000000006E630ULL)
-#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
-#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
-#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
-#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_405 (CPUPPCState *env)
{
/* Time base */
@@ -3608,17 +3594,16 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000006E630ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_405;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 440 EP */
-#define POWERPC_MSRM_440EP (0x000000000006FF30ULL)
-#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
-#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
-#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
-#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
-#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_440EP (CPUPPCState *env)
{
/* Time base */
@@ -3702,17 +3687,16 @@ POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
PPC_440_SPEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000006FF30ULL;
+ pcc->mmu_model = POWERPC_MMU_BOOKE;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 440 GP */
-#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
-#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
-#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
-#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
-#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
-#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_440GP (CPUPPCState *env)
{
/* Time base */
@@ -3775,17 +3759,16 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
PPC_440_SPEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000006FF30ULL;
+ pcc->mmu_model = POWERPC_MMU_BOOKE;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 440x4 */
-#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
-#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
-#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
-#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
-#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_440x4 (CPUPPCState *env)
{
/* Time base */
@@ -3848,17 +3831,16 @@ POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
PPC_440_SPEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000006FF30ULL;
+ pcc->mmu_model = POWERPC_MMU_BOOKE;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 440x5 */
-#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
-#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
-#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
-#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
-#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_440x5 (CPUPPCState *env)
{
/* Time base */
@@ -3939,17 +3921,16 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
PPC_440_SPEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000006FF30ULL;
+ pcc->mmu_model = POWERPC_MMU_BOOKE;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 460 (guessed) */
-#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
-#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
-#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
-#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
-#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
-#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_460 (CPUPPCState *env)
{
/* Time base */
@@ -4036,17 +4017,16 @@ POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
PPC_440_SPEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000006FF30ULL;
+ pcc->mmu_model = POWERPC_MMU_BOOKE;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 460F (guessed) */
-#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
-#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
-#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
-#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
-#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
-#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_460F (CPUPPCState *env)
{
/* Time base */
@@ -4136,17 +4116,16 @@ POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
PPC_440_SPEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000006FF30ULL;
+ pcc->mmu_model = POWERPC_MMU_BOOKE;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
/* Freescale 5xx cores (aka RCPU) */
-#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
-#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
-#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
-#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
-#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
-#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_MPC5xx (CPUPPCState *env)
{
/* Time base */
@@ -4170,17 +4149,16 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
PPC_MFTB;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000001FF43ULL;
+ pcc->mmu_model = POWERPC_MMU_REAL;
+ pcc->excp_model = POWERPC_EXCP_603;
+ pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
+ pcc->bfd_mach = bfd_mach_ppc_505;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_BUS_CLK;
}
/* Freescale 8xx cores (aka PowerQUICC) */
-#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
-#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
-#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
-#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
-#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
-#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_MPC8xx (CPUPPCState *env)
{
/* Time base */
@@ -4203,18 +4181,17 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
PPC_MEM_EIEIO | PPC_MEM_SYNC |
PPC_CACHE_ICBI | PPC_MFTB;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000001F673ULL;
+ pcc->mmu_model = POWERPC_MMU_MPC8xx;
+ pcc->excp_model = POWERPC_EXCP_603;
+ pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
+ pcc->bfd_mach = bfd_mach_ppc_860;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_BUS_CLK;
}
/* Freescale 82xx cores (aka PowerQUICC-II) */
/* PowerPC G2 */
-#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
-#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
-//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
-#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
-#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_G2 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -4269,17 +4246,16 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000006FFF2ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_G2;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_ec603e;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC G2LE */
-#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
-#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
-#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
-#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
-#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_G2LE (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -4334,18 +4310,16 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000007FFF3ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_G2;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_ec603e;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
/* e200 core */
-#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
-#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
-#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
-#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
-#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
-#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
- POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_e200 (CPUPPCState *env)
{
/* Time base */
@@ -4476,17 +4450,17 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
PPC_MEM_TLBSYNC | PPC_TLBIVAX |
PPC_BOOKE;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000606FF30ULL;
+ pcc->mmu_model = POWERPC_MMU_BOOKE206;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_860;
+ pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
+ POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
}
/* e300 core */
-#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
-#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
-#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
-#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
-#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_e300 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -4534,47 +4508,19 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000007FFF3ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_603;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_603;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
/* e500v1 core */
-#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
-#define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
-#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
-#define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
-#define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
-#define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
- POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
- POWERPC_FLAG_BUS_CLK)
-
/* e500v2 core */
-#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
-#define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
-#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
-#define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
-#define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
-#define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
- POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
- POWERPC_FLAG_BUS_CLK)
-
/* e500mc core */
-#define POWERPC_MSRM_e500mc (0x000000001402FB36ULL)
-#define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)
-#define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE)
-#define POWERPC_INPUT_e500mc (PPC_FLAGS_INPUT_BookE)
-/* Fixme: figure out the correct flag for e500mc */
-#define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500)
-#define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-
/* e5500 core */
-#define POWERPC_MSRM_e5500 (0x000000009402FB36ULL)
-#define POWERPC_MMU_e5500 (POWERPC_MMU_BOOKE206)
-#define POWERPC_EXCP_e5500 (POWERPC_EXCP_BOOKE)
-#define POWERPC_INPUT_e5500 (PPC_FLAGS_INPUT_BookE)
-/* Fixme: figure out the correct flag for e5500 */
-#define POWERPC_BFDM_e5500 (bfd_mach_ppc_e500)
-#define POWERPC_FLAG_e5500 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
#if !defined(CONFIG_USER_ONLY)
static void spr_write_mas73(void *opaque, int sprn, int gprn)
@@ -4803,6 +4749,14 @@ POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
pcc->insns_flags2 = PPC2_BOOKE206;
+ pcc->msr_mask = 0x000000000606FF30ULL;
+ pcc->mmu_model = POWERPC_MMU_BOOKE206;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_860;
+ pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
+ POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
}
static void init_proc_e500v2(CPUPPCState *env)
@@ -4823,6 +4777,14 @@ POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
pcc->insns_flags2 = PPC2_BOOKE206;
+ pcc->msr_mask = 0x000000000606FF30ULL;
+ pcc->mmu_model = POWERPC_MMU_BOOKE206;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_860;
+ pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
+ POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
}
static void init_proc_e500mc(CPUPPCState *env)
@@ -4845,6 +4807,14 @@ POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
PPC_FLOAT_STFIWX | PPC_WAIT |
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
+ pcc->msr_mask = 0x000000001402FB36ULL;
+ pcc->mmu_model = POWERPC_MMU_BOOKE206;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ /* FIXME: figure out the correct flag for e500mc */
+ pcc->bfd_mach = bfd_mach_ppc_e500;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
#ifdef TARGET_PPC64
@@ -4869,6 +4839,14 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
+ pcc->msr_mask = 0x000000009402FB36ULL;
+ pcc->mmu_model = POWERPC_MMU_BOOKE206;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ /* FIXME: figure out the correct flag for e5500 */
+ pcc->bfd_mach = bfd_mach_ppc_e500;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
#endif
@@ -4876,25 +4854,18 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
/* POWER : same as 601, without mfmsr, mfsr */
#if defined(TODO)
-/* POWER RSC (from RAD6000) */
-#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
-
POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
{
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
pcc->insns_flags = XXX_TODO;
+ /* POWER RSC (from RAD6000) */
+ pcc->msr_mask = 0x00000000FEF0ULL;
}
#endif /* TODO */
/* PowerPC 601 */
-#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
#define POWERPC_MSRR_601 (0x0000000000001040ULL)
-//#define POWERPC_MMU_601 (POWERPC_MMU_601)
-//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
-#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
-#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
static void init_proc_601 (CPUPPCState *env)
{
@@ -4945,16 +4916,16 @@ POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000000FD70ULL;
+ pcc->mmu_model = POWERPC_MMU_601;
+ pcc->excp_model = POWERPC_EXCP_601;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_601;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
}
/* PowerPC 601v */
-#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
#define POWERPC_MSRR_601v (0x0000000000001040ULL)
-#define POWERPC_MMU_601v (POWERPC_MMU_601)
-#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
-#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
-#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
static void init_proc_601v (CPUPPCState *env)
{
@@ -4978,18 +4949,15 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000000FD70ULL;
+ pcc->mmu_model = POWERPC_MMU_601;
+ pcc->excp_model = POWERPC_EXCP_601;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_601;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
}
/* PowerPC 602 */
-#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
-/* XXX: 602 MMU is quite specific. Should add a special case */
-#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
-//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
-#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
-#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_602 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5031,17 +4999,17 @@ POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_602_SPEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x0000000000C7FF73ULL;
+ /* XXX: 602 MMU is quite specific. Should add a special case */
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_602;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_602;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 603 */
-#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
-#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
-//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
-#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
-#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_603 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5083,17 +5051,16 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000007FF73ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_603;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_603;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 603e */
-#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
-#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
-//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
-#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
-#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_603E (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5140,17 +5107,16 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000007FF73ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_603E;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_ec603e;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 604 */
-#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
-#define POWERPC_MMU_604 (POWERPC_MMU_32B)
-//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
-#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
-#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_604 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5186,17 +5152,16 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000005FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_32B;
+ pcc->excp_model = POWERPC_EXCP_604;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_604;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 604E */
-#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
-#define POWERPC_MMU_604E (POWERPC_MMU_32B)
-#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
-#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
-#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_604E (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5252,17 +5217,16 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000005FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_32B;
+ pcc->excp_model = POWERPC_EXCP_604;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_604;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 740 */
-#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
-#define POWERPC_MMU_740 (POWERPC_MMU_32B)
-#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
-#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
-#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_740 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5305,17 +5269,16 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000005FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_32B;
+ pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 750 */
-#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
-#define POWERPC_MMU_750 (POWERPC_MMU_32B)
-#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
-#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
-#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_750 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5366,17 +5329,16 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000005FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_32B;
+ pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 750 CL */
-#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
-#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
-#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
-#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
-#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_750cl (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5550,17 +5512,16 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000005FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_32B;
+ pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 750CX */
-#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
-#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
-#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
-#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
-#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_750cx (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5615,17 +5576,16 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000005FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_32B;
+ pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 750FX */
-#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
-#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
-#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
-#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
-#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_750fx (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5685,17 +5645,16 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000005FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_32B;
+ pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 750GX */
-#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
-#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
-#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
-#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
-#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_750gx (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5755,17 +5714,16 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000005FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_32B;
+ pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 745 */
-#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
-#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
-#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
-#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
-#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_745 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5816,17 +5774,16 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000005FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_7x5;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 755 */
-#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
-#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
-#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
-#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
-#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_755 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5888,18 +5845,16 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000005FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_7x5;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 7400 (aka G4) */
-#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
-#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
-#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
-#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
-#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_7400 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5948,18 +5903,17 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000205FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_32B;
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 7410 (aka G4) */
-#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
-#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
-#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
-#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
-#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_7410 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6014,18 +5968,17 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000205FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_32B;
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 7440 (aka G4) */
-#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
-#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
-#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
-#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
-#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_7440 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6106,18 +6059,17 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000205FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 7450 (aka G4) */
-#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
-#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
-#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
-#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
-#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_7450 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6224,18 +6176,17 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000205FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 7445 (aka G4) */
-#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
-#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
-#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
-#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
-#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_7445 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6345,18 +6296,17 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000205FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 7455 (aka G4) */
-#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
-#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
-#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
-#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
-#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_7455 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6468,18 +6418,17 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000205FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 7457 (aka G4) */
-#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
-#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
-#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
-#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
-#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
- POWERPC_FLAG_BUS_CLK)
-
static void init_proc_7457 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6615,19 +6564,18 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x000000000205FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
}
#if defined (TARGET_PPC64)
/* PowerPC 970 */
-#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
-#define POWERPC_MMU_970 (POWERPC_MMU_64B)
-//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
-#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
-#define POWERPC_BFDM_970 (bfd_mach_ppc64)
-#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
- POWERPC_FLAG_BUS_CLK)
-
#if defined(CONFIG_USER_ONLY)
#define POWERPC970_HID5_INIT 0x00000080
#else
@@ -6720,18 +6668,17 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x900000000204FF36ULL;
+ pcc->mmu_model = POWERPC_MMU_64B;
+ pcc->excp_model = POWERPC_EXCP_970;
+ pcc->bus_model = PPC_FLAGS_INPUT_970;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 970FX (aka G5) */
-#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
-#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
-#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
-#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
-#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
-#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
- POWERPC_FLAG_BUS_CLK)
-
static int check_pow_970FX (CPUPPCState *env)
{
if (env->spr[SPR_HID0] & 0x00600000)
@@ -6830,18 +6777,17 @@ POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x800000000204FF36ULL;
+ pcc->mmu_model = POWERPC_MMU_64B;
+ pcc->excp_model = POWERPC_EXCP_970;
+ pcc->bus_model = PPC_FLAGS_INPUT_970;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 970 GX */
-#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
-#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
-#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
-#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
-#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
-#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
- POWERPC_FLAG_BUS_CLK)
-
static int check_pow_970GX (CPUPPCState *env)
{
if (env->spr[SPR_HID0] & 0x00600000)
@@ -6928,18 +6874,17 @@ POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x800000000204FF36ULL;
+ pcc->mmu_model = POWERPC_MMU_64B;
+ pcc->excp_model = POWERPC_EXCP_970;
+ pcc->bus_model = PPC_FLAGS_INPUT_970;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
}
/* PowerPC 970 MP */
-#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
-#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
-#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
-#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
-#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
-#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
- POWERPC_FLAG_BUS_CLK)
-
static int check_pow_970MP (CPUPPCState *env)
{
if (env->spr[SPR_HID0] & 0x01C00000)
@@ -7026,18 +6971,17 @@ POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x900000000204FF36ULL;
+ pcc->mmu_model = POWERPC_MMU_64B;
+ pcc->excp_model = POWERPC_EXCP_970;
+ pcc->bus_model = PPC_FLAGS_INPUT_970;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
}
/* POWER7 */
-#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
-#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
-#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
-#define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
-#define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
-#define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
- POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
-
static void init_proc_POWER7 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -7117,17 +7061,17 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
+ pcc->msr_mask = 0x800000000204FF36ULL;
+ pcc->mmu_model = POWERPC_MMU_2_06;
+ pcc->excp_model = POWERPC_EXCP_POWER7;
+ pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
}
/* PowerPC 620 */
-#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
-//#define POWERPC_MMU_620 (POWERPC_MMU_620)
-#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
-#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_620 (bfd_mach_ppc64)
-#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-
static void init_proc_620 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -7165,6 +7109,13 @@ POWERPC_FAMILY(620)(ObjectClass *oc, void *data)
PPC_SEGMENT | PPC_EXTERN |
PPC_64B | PPC_SLBI;
pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = 0x800000000005FF77ULL;
+ pcc->mmu_model = POWERPC_MMU_620;
+ pcc->excp_model = POWERPC_EXCP_970;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
#endif /* defined (TARGET_PPC64) */
@@ -7885,12 +7836,6 @@ enum {
\
pcc->pvr = _pvr; \
pcc->svr = _svr; \
- pcc->msr_mask = glue(POWERPC_MSRM_, _type); \
- pcc->mmu_model = glue(POWERPC_MMU_, _type); \
- pcc->excp_model = glue(POWERPC_EXCP_, _type); \
- pcc->bus_model = glue(POWERPC_INPUT_, _type); \
- pcc->bfd_mach = glue(POWERPC_BFDM_, _type); \
- pcc->flags = glue(POWERPC_FLAG_, _type); \
} \
\
static const TypeInfo \
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 49/66] target-ppc: Turn descriptive CPU family comments into device descriptions
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (47 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 48/66] target-ppc: Set remaining fields on CPU family classes Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 50/66] target-ppc: Turn descriptive CPU model " Alexander Graf
` (17 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
This gets rid of some more overly long comments that have lost most of
their purpose now that in most cases there's only two functions left per
CPU family.
The class field is inherited by the actual CPU models, so override it.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 159 +++++++++++++++++++++++++++++--------------
1 files changed, 107 insertions(+), 52 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index eea9adf..3ec7c1e 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3274,7 +3274,6 @@ static int check_pow_hid0_74xx (CPUPPCState *env)
\
static void glue(glue(ppc_, _name), _cpu_family_class_init)
-/* PowerPC 401 */
static void init_proc_401 (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -3292,8 +3291,10 @@ static void init_proc_401 (CPUPPCState *env)
POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 401";
pcc->init_proc = init_proc_401;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
@@ -3312,7 +3313,6 @@ POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 401x2 */
static void init_proc_401x2 (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -3338,8 +3338,10 @@ static void init_proc_401x2 (CPUPPCState *env)
POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 401x2";
pcc->init_proc = init_proc_401x2;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -3359,7 +3361,6 @@ POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 401x3 */
static void init_proc_401x3 (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -3379,8 +3380,10 @@ static void init_proc_401x3 (CPUPPCState *env)
POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 401x3";
pcc->init_proc = init_proc_401x3;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -3400,7 +3403,6 @@ POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* IOP480 */
static void init_proc_IOP480 (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -3426,8 +3428,10 @@ static void init_proc_IOP480 (CPUPPCState *env)
POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "IOP480";
pcc->init_proc = init_proc_IOP480;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
@@ -3447,7 +3451,6 @@ POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 403 */
static void init_proc_403 (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -3466,8 +3469,10 @@ static void init_proc_403 (CPUPPCState *env)
POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 403";
pcc->init_proc = init_proc_403;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
@@ -3486,7 +3491,6 @@ POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 403 GCX */
static void init_proc_403GCX (CPUPPCState *env)
{
gen_spr_40x(env);
@@ -3524,8 +3528,10 @@ static void init_proc_403GCX (CPUPPCState *env)
POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 403 GCX";
pcc->init_proc = init_proc_403GCX;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
@@ -3545,7 +3551,6 @@ POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 405 */
static void init_proc_405 (CPUPPCState *env)
{
/* Time base */
@@ -3582,8 +3587,10 @@ static void init_proc_405 (CPUPPCState *env)
POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 405";
pcc->init_proc = init_proc_405;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -3603,7 +3610,6 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 440 EP */
static void init_proc_440EP (CPUPPCState *env)
{
/* Time base */
@@ -3672,8 +3678,10 @@ static void init_proc_440EP (CPUPPCState *env)
POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 440 EP";
pcc->init_proc = init_proc_440EP;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
@@ -3696,7 +3704,6 @@ POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 440 GP */
static void init_proc_440GP (CPUPPCState *env)
{
/* Time base */
@@ -3747,8 +3754,10 @@ static void init_proc_440GP (CPUPPCState *env)
POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 440 GP";
pcc->init_proc = init_proc_440GP;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
@@ -3768,7 +3777,6 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 440x4 */
static void init_proc_440x4 (CPUPPCState *env)
{
/* Time base */
@@ -3819,8 +3827,10 @@ static void init_proc_440x4 (CPUPPCState *env)
POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 440x4";
pcc->init_proc = init_proc_440x4;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
@@ -3840,7 +3850,6 @@ POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 440x5 */
static void init_proc_440x5 (CPUPPCState *env)
{
/* Time base */
@@ -3909,8 +3918,10 @@ static void init_proc_440x5 (CPUPPCState *env)
POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 440x5";
pcc->init_proc = init_proc_440x5;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
@@ -3930,7 +3941,6 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 460 (guessed) */
static void init_proc_460 (CPUPPCState *env)
{
/* Time base */
@@ -4004,8 +4014,10 @@ static void init_proc_460 (CPUPPCState *env)
POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 460 (guessed)";
pcc->init_proc = init_proc_460;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
@@ -4026,7 +4038,6 @@ POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 460F (guessed) */
static void init_proc_460F (CPUPPCState *env)
{
/* Time base */
@@ -4100,8 +4111,10 @@ static void init_proc_460F (CPUPPCState *env)
POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 460F (guessed)";
pcc->init_proc = init_proc_460F;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
@@ -4125,7 +4138,6 @@ POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
-/* Freescale 5xx cores (aka RCPU) */
static void init_proc_MPC5xx (CPUPPCState *env)
{
/* Time base */
@@ -4140,8 +4152,10 @@ static void init_proc_MPC5xx (CPUPPCState *env)
POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "Freescale 5xx cores (aka RCPU)";
pcc->init_proc = init_proc_MPC5xx;
pcc->check_pow = check_pow_none;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
@@ -4158,7 +4172,6 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* Freescale 8xx cores (aka PowerQUICC) */
static void init_proc_MPC8xx (CPUPPCState *env)
{
/* Time base */
@@ -4173,8 +4186,10 @@ static void init_proc_MPC8xx (CPUPPCState *env)
POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
pcc->init_proc = init_proc_MPC8xx;
pcc->check_pow = check_pow_none;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
@@ -4191,7 +4206,7 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
}
/* Freescale 82xx cores (aka PowerQUICC-II) */
-/* PowerPC G2 */
+
static void init_proc_G2 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -4234,8 +4249,10 @@ static void init_proc_G2 (CPUPPCState *env)
POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC G2";
pcc->init_proc = init_proc_G2;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -4255,7 +4272,6 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC G2LE */
static void init_proc_G2LE (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -4298,8 +4314,10 @@ static void init_proc_G2LE (CPUPPCState *env)
POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC G2LE";
pcc->init_proc = init_proc_G2LE;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -4319,7 +4337,6 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
-/* e200 core */
static void init_proc_e200 (CPUPPCState *env)
{
/* Time base */
@@ -4429,8 +4446,10 @@ static void init_proc_e200 (CPUPPCState *env)
POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "e200 core";
pcc->init_proc = init_proc_e200;
pcc->check_pow = check_pow_hid0;
/* XXX: unimplemented instructions:
@@ -4460,7 +4479,6 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* e300 core */
static void init_proc_e300 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -4496,8 +4514,10 @@ static void init_proc_e300 (CPUPPCState *env)
POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "e300 core";
pcc->init_proc = init_proc_e300;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -4517,11 +4537,6 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
-/* e500v1 core */
-/* e500v2 core */
-/* e500mc core */
-/* e5500 core */
-
#if !defined(CONFIG_USER_ONLY)
static void spr_write_mas73(void *opaque, int sprn, int gprn)
{
@@ -4738,8 +4753,10 @@ static void init_proc_e500v1(CPUPPCState *env)
POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "e500v1 core";
pcc->init_proc = init_proc_e500v1;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
@@ -4766,8 +4783,10 @@ static void init_proc_e500v2(CPUPPCState *env)
POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "e500v2 core";
pcc->init_proc = init_proc_e500v2;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
@@ -4794,8 +4813,10 @@ static void init_proc_e500mc(CPUPPCState *env)
POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "e500mc core";
pcc->init_proc = init_proc_e500mc;
pcc->check_pow = check_pow_none;
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
@@ -4825,8 +4846,10 @@ static void init_proc_e5500(CPUPPCState *env)
POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "e5500 core";
pcc->init_proc = init_proc_e5500;
pcc->check_pow = check_pow_none;
pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
@@ -4856,15 +4879,16 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
#if defined(TODO)
POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "POWER";
pcc->insns_flags = XXX_TODO;
/* POWER RSC (from RAD6000) */
pcc->msr_mask = 0x00000000FEF0ULL;
}
#endif /* TODO */
-/* PowerPC 601 */
#define POWERPC_MSRR_601 (0x0000000000001040ULL)
static void init_proc_601 (CPUPPCState *env)
@@ -4906,8 +4930,10 @@ static void init_proc_601 (CPUPPCState *env)
POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 601";
pcc->init_proc = init_proc_601;
pcc->check_pow = check_pow_none;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
@@ -4924,7 +4950,6 @@ POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
}
-/* PowerPC 601v */
#define POWERPC_MSRR_601v (0x0000000000001040ULL)
static void init_proc_601v (CPUPPCState *env)
@@ -4939,8 +4964,10 @@ static void init_proc_601v (CPUPPCState *env)
POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 601v";
pcc->init_proc = init_proc_601v;
pcc->check_pow = check_pow_none;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
@@ -4957,7 +4984,6 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
}
-/* PowerPC 602 */
static void init_proc_602 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -4987,8 +5013,10 @@ static void init_proc_602 (CPUPPCState *env)
POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 602";
pcc->init_proc = init_proc_602;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5009,7 +5037,6 @@ POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 603 */
static void init_proc_603 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5039,8 +5066,10 @@ static void init_proc_603 (CPUPPCState *env)
POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 603";
pcc->init_proc = init_proc_603;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5060,7 +5089,6 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 603e */
static void init_proc_603E (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5095,8 +5123,10 @@ static void init_proc_603E (CPUPPCState *env)
POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 603e";
pcc->init_proc = init_proc_603E;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5116,7 +5146,6 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 604 */
static void init_proc_604 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5140,8 +5169,10 @@ static void init_proc_604 (CPUPPCState *env)
POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 604";
pcc->init_proc = init_proc_604;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5161,7 +5192,6 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 604E */
static void init_proc_604E (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5205,8 +5235,10 @@ static void init_proc_604E (CPUPPCState *env)
POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 604E";
pcc->init_proc = init_proc_604E;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5226,7 +5258,6 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 740 */
static void init_proc_740 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5257,8 +5288,10 @@ static void init_proc_740 (CPUPPCState *env)
POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 740";
pcc->init_proc = init_proc_740;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5278,7 +5311,6 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 750 */
static void init_proc_750 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5317,8 +5349,10 @@ static void init_proc_750 (CPUPPCState *env)
POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 750";
pcc->init_proc = init_proc_750;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5338,7 +5372,6 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 750 CL */
static void init_proc_750cl (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5462,8 +5495,10 @@ static void init_proc_750cl (CPUPPCState *env)
POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 750 CL";
pcc->init_proc = init_proc_750cl;
pcc->check_pow = check_pow_hid0;
/* XXX: not implemented:
@@ -5521,7 +5556,6 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 750CX */
static void init_proc_750cx (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5564,8 +5598,10 @@ static void init_proc_750cx (CPUPPCState *env)
POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 750CX";
pcc->init_proc = init_proc_750cx;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5585,7 +5621,6 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 750FX */
static void init_proc_750fx (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5633,8 +5668,10 @@ static void init_proc_750fx (CPUPPCState *env)
POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 750FX";
pcc->init_proc = init_proc_750fx;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5654,7 +5691,6 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 750GX */
static void init_proc_750gx (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5702,8 +5738,10 @@ static void init_proc_750gx (CPUPPCState *env)
POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 750GX";
pcc->init_proc = init_proc_750gx;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5723,7 +5761,6 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 745 */
static void init_proc_745 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5762,8 +5799,10 @@ static void init_proc_745 (CPUPPCState *env)
POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 745";
pcc->init_proc = init_proc_745;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5783,7 +5822,6 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 755 */
static void init_proc_755 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5833,8 +5871,10 @@ static void init_proc_755 (CPUPPCState *env)
POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 755";
pcc->init_proc = init_proc_755;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5854,7 +5894,6 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 7400 (aka G4) */
static void init_proc_7400 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5887,8 +5926,10 @@ static void init_proc_7400 (CPUPPCState *env)
POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 7400 (aka G4)";
pcc->init_proc = init_proc_7400;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5913,7 +5954,6 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 7410 (aka G4) */
static void init_proc_7410 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -5952,8 +5992,10 @@ static void init_proc_7410 (CPUPPCState *env)
POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 7410 (aka G4)";
pcc->init_proc = init_proc_7410;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -5978,7 +6020,6 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 7440 (aka G4) */
static void init_proc_7440 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6043,8 +6084,10 @@ static void init_proc_7440 (CPUPPCState *env)
POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 7440 (aka G4)";
pcc->init_proc = init_proc_7440;
pcc->check_pow = check_pow_hid0_74xx;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -6069,7 +6112,6 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 7450 (aka G4) */
static void init_proc_7450 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6160,8 +6202,10 @@ static void init_proc_7450 (CPUPPCState *env)
POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 7450 (aka G4)";
pcc->init_proc = init_proc_7450;
pcc->check_pow = check_pow_hid0_74xx;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -6186,7 +6230,6 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 7445 (aka G4) */
static void init_proc_7445 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6280,8 +6323,10 @@ static void init_proc_7445 (CPUPPCState *env)
POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 7445 (aka G4)";
pcc->init_proc = init_proc_7445;
pcc->check_pow = check_pow_hid0_74xx;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -6306,7 +6351,6 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 7455 (aka G4) */
static void init_proc_7455 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6402,8 +6446,10 @@ static void init_proc_7455 (CPUPPCState *env)
POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 7455 (aka G4)";
pcc->init_proc = init_proc_7455;
pcc->check_pow = check_pow_hid0_74xx;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -6428,7 +6474,6 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 7457 (aka G4) */
static void init_proc_7457 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -6548,8 +6593,10 @@ static void init_proc_7457 (CPUPPCState *env)
POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 7457 (aka G4)";
pcc->init_proc = init_proc_7457;
pcc->check_pow = check_pow_hid0_74xx;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -6575,7 +6622,6 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
}
#if defined (TARGET_PPC64)
-/* PowerPC 970 */
#if defined(CONFIG_USER_ONLY)
#define POWERPC970_HID5_INIT 0x00000080
#else
@@ -6654,8 +6700,10 @@ static void init_proc_970 (CPUPPCState *env)
POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 970";
pcc->init_proc = init_proc_970;
pcc->check_pow = check_pow_970;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -6678,7 +6726,6 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 970FX (aka G5) */
static int check_pow_970FX (CPUPPCState *env)
{
if (env->spr[SPR_HID0] & 0x00600000)
@@ -6763,8 +6810,10 @@ static void init_proc_970FX (CPUPPCState *env)
POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 970FX (aka G5)";
pcc->init_proc = init_proc_970FX;
pcc->check_pow = check_pow_970FX;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -6787,7 +6836,6 @@ POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 970 GX */
static int check_pow_970GX (CPUPPCState *env)
{
if (env->spr[SPR_HID0] & 0x00600000)
@@ -6860,8 +6908,10 @@ static void init_proc_970GX (CPUPPCState *env)
POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 970 GX";
pcc->init_proc = init_proc_970GX;
pcc->check_pow = check_pow_970GX;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -6884,7 +6934,6 @@ POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* PowerPC 970 MP */
static int check_pow_970MP (CPUPPCState *env)
{
if (env->spr[SPR_HID0] & 0x01C00000)
@@ -6957,8 +7006,10 @@ static void init_proc_970MP (CPUPPCState *env)
POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 970 MP";
pcc->init_proc = init_proc_970MP;
pcc->check_pow = check_pow_970MP;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -6981,7 +7032,6 @@ POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-/* POWER7 */
static void init_proc_POWER7 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -7046,8 +7096,10 @@ static void init_proc_POWER7 (CPUPPCState *env)
POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "POWER7";
pcc->init_proc = init_proc_POWER7;
pcc->check_pow = check_pow_nocheck;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -7071,7 +7123,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
}
-/* PowerPC 620 */
static void init_proc_620 (CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -7095,8 +7146,10 @@ static void init_proc_620 (CPUPPCState *env)
POWERPC_FAMILY(620)(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ dc->desc = "PowerPC 620";
pcc->init_proc = init_proc_620;
pcc->check_pow = check_pow_nocheck; /* Check this */
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
@@ -7832,10 +7885,12 @@ enum {
glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init) \
(ObjectClass *oc, void *data) \
{ \
+ DeviceClass *dc = DEVICE_CLASS(oc); \
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); \
\
pcc->pvr = _pvr; \
pcc->svr = _svr; \
+ dc->desc = NULL; \
} \
\
static const TypeInfo \
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 50/66] target-ppc: Turn descriptive CPU model comments into device descriptions
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (48 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 49/66] target-ppc: Turn descriptive CPU family comments into device descriptions Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 51/66] target-ppc: Update Coding Style for CPU models Alexander Graf
` (16 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Fix microcontroller typo while at it.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 1614 ++++++++++++++++++++-----------------------
1 files changed, 754 insertions(+), 860 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3ec7c1e..bd5230c 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7876,11 +7876,11 @@ enum {
POWERPC_SVR_8641D = 0x80900121,
};
-/*****************************************************************************/
-/* PowerPC CPU definitions */
+/***************************************************************************/
+/* PowerPC CPU definitions */
#define POWERPC_DEF_PREFIX(pvr, svr, type) \
glue(glue(glue(glue(pvr, _), svr), _), type)
-#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
+#define POWERPC_DEF_SVR(_name, _desc, _pvr, _svr, _type) \
static void \
glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init) \
(ObjectClass *oc, void *data) \
@@ -7890,7 +7890,7 @@ enum {
\
pcc->pvr = _pvr; \
pcc->svr = _svr; \
- dc->desc = NULL; \
+ dc->desc = _desc; \
} \
\
static const TypeInfo \
@@ -7911,1267 +7911,1161 @@ enum {
type_init( \
glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types))
-#define POWERPC_DEF(_name, _pvr, _type) \
-POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
+#define POWERPC_DEF(_name, _pvr, _type, _desc) \
+ POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type)
/* Embedded PowerPC */
/* PowerPC 401 family */
- /* Generic PowerPC 401 */
- POWERPC_DEF("401", CPU_POWERPC_401, 401)
+ POWERPC_DEF("401", CPU_POWERPC_401, 401,
+ "Generic PowerPC 401")
/* PowerPC 401 cores */
- /* PowerPC 401A1 */
- POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401)
- /* PowerPC 401B2 */
- POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2)
+ POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401,
+ "PowerPC 401A1")
+ POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2,
+ "PowerPC 401B2")
#if defined (TODO)
- /* PowerPC 401B3 */
- POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3)
-#endif
- /* PowerPC 401C2 */
- POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2)
- /* PowerPC 401D2 */
- POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2)
- /* PowerPC 401E2 */
- POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2)
- /* PowerPC 401F2 */
- POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2)
- /* PowerPC 401G2 */
+ POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3,
+ "PowerPC 401B3")
+#endif
+ POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2,
+ "PowerPC 401C2")
+ POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2,
+ "PowerPC 401D2")
+ POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2,
+ "PowerPC 401E2")
+ POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2,
+ "PowerPC 401F2")
/* XXX: to be checked */
- POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2)
+ POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2,
+ "PowerPC 401G2")
/* PowerPC 401 microcontrolers */
#if defined (TODO)
- /* PowerPC 401GF */
- POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401)
+ POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401,
+ "PowerPC 401GF")
#endif
- /* IOP480 (401 microcontroler) */
- POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480)
- /* IBM Processor for Network Resources */
- POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401)
+ POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480,
+ "IOP480 (401 microcontroller)")
+ POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401,
+ "IBM Processor for Network Resources")
#if defined (TODO)
- POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401)
+ POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401,
+ NULL)
#endif
/* PowerPC 403 family */
/* PowerPC 403 microcontrolers */
- /* PowerPC 403 GA */
- POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403)
- /* PowerPC 403 GB */
- POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403)
- /* PowerPC 403 GC */
- POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403)
- /* PowerPC 403 GCX */
- POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX)
+ POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403,
+ "PowerPC 403 GA")
+ POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403,
+ "PowerPC 403 GB")
+ POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403,
+ "PowerPC 403 GC")
+ POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX,
+ "PowerPC 403 GCX")
#if defined (TODO)
- /* PowerPC 403 GP */
- POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403)
+ POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403,
+ "PowerPC 403 GP")
#endif
/* PowerPC 405 family */
/* PowerPC 405 cores */
#if defined (TODO)
- /* PowerPC 405 A3 */
- POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405)
+ POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405,
+ "PowerPC 405 A3")
#endif
#if defined (TODO)
- /* PowerPC 405 A4 */
- POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405)
+ POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405,
+ "PowerPC 405 A4")
#endif
#if defined (TODO)
- /* PowerPC 405 B3 */
- POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405)
+ POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405,
+ "PowerPC 405 B3")
#endif
#if defined (TODO)
- /* PowerPC 405 B4 */
- POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405)
+ POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405,
+ "PowerPC 405 B4")
#endif
#if defined (TODO)
- /* PowerPC 405 C3 */
- POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405)
+ POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405,
+ "PowerPC 405 C3")
#endif
#if defined (TODO)
- /* PowerPC 405 C4 */
- POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405)
+ POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405,
+ "PowerPC 405 C4")
#endif
- /* PowerPC 405 D2 */
- POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405)
+ POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405,
+ "PowerPC 405 D2")
#if defined (TODO)
- /* PowerPC 405 D3 */
- POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405)
+ POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405,
+ "PowerPC 405 D3")
#endif
- /* PowerPC 405 D4 */
- POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405)
+ POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405,
+ "PowerPC 405 D4")
#if defined (TODO)
- /* PowerPC 405 D5 */
- POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405)
+ POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405,
+ "PowerPC 405 D5")
#endif
#if defined (TODO)
- /* PowerPC 405 E4 */
- POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405)
+ POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405,
+ "PowerPC 405 E4")
#endif
#if defined (TODO)
- /* PowerPC 405 F4 */
- POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405)
+ POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405,
+ "PowerPC 405 F4")
#endif
#if defined (TODO)
- /* PowerPC 405 F5 */
- POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405)
+ POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405,
+ "PowerPC 405 F5")
#endif
#if defined (TODO)
- /* PowerPC 405 F6 */
- POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405)
+ POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405,
+ "PowerPC 405 F6")
#endif
/* PowerPC 405 microcontrolers */
- /* PowerPC 405 CRa */
- POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405)
- /* PowerPC 405 CRb */
- POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405)
- /* PowerPC 405 CRc */
- POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405)
- /* PowerPC 405 EP */
- POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405)
+ POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405,
+ "PowerPC 405 CRa")
+ POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405,
+ "PowerPC 405 CRb")
+ POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405,
+ "PowerPC 405 CRc")
+ POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405,
+ "PowerPC 405 EP")
#if defined(TODO)
- /* PowerPC 405 EXr */
- POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405)
+ POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405,
+ "PowerPC 405 EXr")
#endif
- /* PowerPC 405 EZ */
- POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405)
+ POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405,
+ "PowerPC 405 EZ")
#if defined(TODO)
- /* PowerPC 405 FX */
- POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405)
-#endif
- /* PowerPC 405 GPa */
- POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405)
- /* PowerPC 405 GPb */
- POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405)
- /* PowerPC 405 GPc */
- POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405)
- /* PowerPC 405 GPd */
- POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405)
- /* PowerPC 405 GPR */
- POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405)
+ POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405,
+ "PowerPC 405 FX")
+#endif
+ POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405,
+ "PowerPC 405 GPa")
+ POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405,
+ "PowerPC 405 GPb")
+ POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405,
+ "PowerPC 405 GPc")
+ POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405,
+ "PowerPC 405 GPd")
+ POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405,
+ "PowerPC 405 GPR")
#if defined(TODO)
- /* PowerPC 405 H */
- POWERPC_DEF("405H", CPU_POWERPC_405H, 405)
+ POWERPC_DEF("405H", CPU_POWERPC_405H, 405,
+ "PowerPC 405 H")
#endif
#if defined(TODO)
- /* PowerPC 405 L */
- POWERPC_DEF("405L", CPU_POWERPC_405L, 405)
+ POWERPC_DEF("405L", CPU_POWERPC_405L, 405,
+ "PowerPC 405 L")
#endif
- /* PowerPC 405 LP */
- POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405)
+ POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405,
+ "PowerPC 405 LP")
#if defined(TODO)
- /* PowerPC 405 PM */
- POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405)
+ POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405,
+ "PowerPC 405 PM")
#endif
#if defined(TODO)
- /* PowerPC 405 PS */
- POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405)
+ POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405,
+ "PowerPC 405 PS")
#endif
#if defined(TODO)
- /* PowerPC 405 S */
- POWERPC_DEF("405S", CPU_POWERPC_405S, 405)
-#endif
- /* Npe405 H */
- POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405)
- /* Npe405 H2 */
- POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405)
- /* Npe405 L */
- POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405)
- /* Npe4GS3 */
- POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405)
+ POWERPC_DEF("405S", CPU_POWERPC_405S, 405,
+ "PowerPC 405 S")
+#endif
+ POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405,
+ "Npe405 H")
+ POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405,
+ "Npe405 H2")
+ POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405,
+ "Npe405 L")
+ POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405,
+ "Npe4GS3")
#if defined (TODO)
- POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405)
+ POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405,
+ NULL)
#endif
#if defined (TODO)
- POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405)
+ POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405,
+ NULL)
#endif
#if defined (TODO)
- /* PowerPC LC77700 (Sanyo) */
- POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405)
+ POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405,
+ "PowerPC LC77700 (Sanyo)")
#endif
/* PowerPC 401/403/405 based set-top-box microcontrolers */
#if defined (TODO)
- /* STB010000 */
- POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2)
+ POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2,
+ "STB010000")
#endif
#if defined (TODO)
- /* STB01010 */
- POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2)
+ POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2,
+ "STB01010")
#endif
#if defined (TODO)
- /* STB0210 */
- POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3)
+ POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3,
+ "STB0210")
#endif
- /* STB03xx */
- POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405)
+ POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405,
+ "STB03xx")
#if defined (TODO)
- /* STB043x */
- POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405)
+ POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405,
+ "STB043x")
#endif
#if defined (TODO)
- /* STB045x */
- POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405)
+ POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405,
+ "STB045x")
#endif
- /* STB04xx */
- POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405)
- /* STB25xx */
- POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405)
+ POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405,
+ "STB04xx")
+ POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405,
+ "STB25xx")
#if defined (TODO)
- /* STB130 */
- POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405)
+ POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405,
+ "STB130")
#endif
/* Xilinx PowerPC 405 cores */
- POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405)
- POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405)
+ POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405,
+ NULL)
+ POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405,
+ NULL)
#if defined (TODO)
- /* Zarlink ZL10310 */
- POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405)
+ POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405,
+ "Zarlink ZL10310")
#endif
#if defined (TODO)
- /* Zarlink ZL10311 */
- POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405)
+ POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405,
+ "Zarlink ZL10311")
#endif
#if defined (TODO)
- /* Zarlink ZL10320 */
- POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405)
+ POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405,
+ "Zarlink ZL10320")
#endif
#if defined (TODO)
- /* Zarlink ZL10321 */
- POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405)
+ POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405,
+ "Zarlink ZL10321")
#endif
/* PowerPC 440 family */
#if defined(TODO_USER_ONLY)
- /* Generic PowerPC 440 */
- POWERPC_DEF("440", CPU_POWERPC_440, 440GP)
+ POWERPC_DEF("440", CPU_POWERPC_440, 440GP,
+ "Generic PowerPC 440")
#endif
/* PowerPC 440 cores */
#if defined (TODO)
- /* PowerPC 440 A4 */
- POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4)
+ POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4,
+ "PowerPC 440 A4")
#endif
- /* PowerPC 440 Xilinx 5 */
- POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5)
+ POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5,
+ "PowerPC 440 Xilinx 5")
#if defined (TODO)
- /* PowerPC 440 A5 */
- POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5)
+ POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5,
+ "PowerPC 440 A5")
#endif
#if defined (TODO)
- /* PowerPC 440 B4 */
- POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4)
+ POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4,
+ "PowerPC 440 B4")
#endif
#if defined (TODO)
- /* PowerPC 440 G4 */
- POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4)
+ POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4,
+ "PowerPC 440 G4")
#endif
#if defined (TODO)
- /* PowerPC 440 F5 */
- POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5)
+ POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5,
+ "PowerPC 440 F5")
#endif
#if defined (TODO)
- /* PowerPC 440 G5 */
- POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5)
+ POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5,
+ "PowerPC 440 G5")
#endif
#if defined (TODO)
- /* PowerPC 440H4 */
- POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4)
+ POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4,
+ "PowerPC 440H4")
#endif
#if defined (TODO)
- /* PowerPC 440H6 */
- POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5)
+ POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5,
+ "PowerPC 440H6")
#endif
/* PowerPC 440 microcontrolers */
- /* PowerPC 440 EPa */
- POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP)
- /* PowerPC 440 EPb */
- POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP)
- /* PowerPC 440 EPX */
- POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP)
+ POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP,
+ "PowerPC 440 EPa")
+ POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP,
+ "PowerPC 440 EPb")
+ POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP,
+ "PowerPC 440 EPX")
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 GPb */
- POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP)
+ POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP,
+ "PowerPC 440 GPb")
#endif
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 GPc */
- POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP)
+ POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP,
+ "PowerPC 440 GPc")
#endif
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 GRa */
- POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5)
+ POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5,
+ "PowerPC 440 GRa")
#endif
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 GRX */
- POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5)
+ POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5,
+ "PowerPC 440 GRX")
#endif
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 GXa */
- POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP)
+ POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP,
+ "PowerPC 440 GXa")
#endif
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 GXb */
- POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP)
+ POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP,
+ "PowerPC 440 GXb")
#endif
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 GXc */
- POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP)
+ POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP,
+ "PowerPC 440 GXc")
#endif
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 GXf */
- POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP)
+ POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP,
+ "PowerPC 440 GXf")
#endif
#if defined(TODO)
- /* PowerPC 440 S */
- POWERPC_DEF("440S", CPU_POWERPC_440S, 440)
+ POWERPC_DEF("440S", CPU_POWERPC_440S, 440,
+ "PowerPC 440 S")
#endif
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 SP */
- POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP)
+ POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP,
+ "PowerPC 440 SP")
#endif
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 SP2 */
- POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP)
+ POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP,
+ "PowerPC 440 SP2")
#endif
#if defined(TODO_USER_ONLY)
- /* PowerPC 440 SPE */
- POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP)
+ POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP,
+ "PowerPC 440 SPE")
#endif
/* PowerPC 460 family */
#if defined (TODO)
- /* Generic PowerPC 464 */
- POWERPC_DEF("464", CPU_POWERPC_464, 460)
+ POWERPC_DEF("464", CPU_POWERPC_464, 460,
+ "Generic PowerPC 464")
#endif
/* PowerPC 464 microcontrolers */
#if defined (TODO)
- /* PowerPC 464H90 */
- POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460)
+ POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460,
+ "PowerPC 464H90")
#endif
#if defined (TODO)
- /* PowerPC 464H90F */
- POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F)
+ POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F,
+ "PowerPC 464H90F")
#endif
/* Freescale embedded PowerPC cores */
/* MPC5xx family (aka RCPU) */
#if defined(TODO_USER_ONLY)
- /* Generic MPC5xx core */
- POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx)
+ POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx,
+ "Generic MPC5xx core")
#endif
/* MPC8xx family (aka PowerQUICC) */
#if defined(TODO_USER_ONLY)
- /* Generic MPC8xx core */
- POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx)
+ POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx,
+ "Generic MPC8xx core")
#endif
/* MPC82xx family (aka PowerQUICC-II) */
- /* PowerPC G2 core */
- POWERPC_DEF("G2", CPU_POWERPC_G2, G2)
- /* PowerPC G2 H4 core */
- POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2)
- /* PowerPC G2 GP core */
- POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2)
- /* PowerPC G2 LS core */
- POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2)
- /* PowerPC G2 HiP3 core */
- POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2)
- /* PowerPC G2 HiP4 core */
- POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2)
- /* PowerPC MPC603 core */
- POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E)
- /* PowerPC G2le core (same as G2 plus little-endian mode support) */
- POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE)
- /* PowerPC G2LE GP core */
- POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE)
- /* PowerPC G2LE LS core */
- POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE)
- /* PowerPC G2LE GP1 core */
- POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE)
- /* PowerPC G2LE GP3 core */
- POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2LE)
+ POWERPC_DEF("G2", CPU_POWERPC_G2, G2,
+ "PowerPC G2 core")
+ POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2,
+ "PowerPC G2 H4 core")
+ POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2,
+ "PowerPC G2 GP core")
+ POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2,
+ "PowerPC G2 LS core")
+ POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2,
+ "PowerPC G2 HiP3 core")
+ POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2,
+ "PowerPC G2 HiP4 core")
+ POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E,
+ "PowerPC MPC603 core")
+ POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE,
+ "PowerPC G2le core (same as G2 plus little-endian mode support)")
+ POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE,
+ "PowerPC G2LE GP core")
+ POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE,
+ "PowerPC G2LE LS core")
+ POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE,
+ "PowerPC G2LE GP1 core")
+ POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2LE,
+ "PowerPC G2LE GP3 core")
/* PowerPC G2 microcontrollers */
#if defined(TODO)
- /* MPC5121 */
- POWERPC_DEF_SVR("MPC5121",
+ POWERPC_DEF_SVR("MPC5121", "MPC5121",
CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE)
#endif
- /* MPC5200 v1.0 */
- POWERPC_DEF_SVR("MPC5200_v10",
+ POWERPC_DEF_SVR("MPC5200_v10", "MPC5200 v1.0",
CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE)
- /* MPC5200 v1.1 */
- POWERPC_DEF_SVR("MPC5200_v11",
+ POWERPC_DEF_SVR("MPC5200_v11", "MPC5200 v1.1",
CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE)
- /* MPC5200 v1.2 */
- POWERPC_DEF_SVR("MPC5200_v12",
+ POWERPC_DEF_SVR("MPC5200_v12", "MPC5200 v1.2",
CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE)
- /* MPC5200B v2.0 */
- POWERPC_DEF_SVR("MPC5200B_v20",
+ POWERPC_DEF_SVR("MPC5200B_v20", "MPC5200B v2.0",
CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
- /* MPC5200B v2.1 */
- POWERPC_DEF_SVR("MPC5200B_v21",
+ POWERPC_DEF_SVR("MPC5200B_v21", "MPC5200B v2.1",
CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
/* e200 family */
- /* Generic MPC55xx core */
#if defined (TODO)
- POWERPC_DEF_SVR("MPC55xx",
+ POWERPC_DEF_SVR("MPC55xx", "Generic MPC55xx core",
CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200)
#endif
#if defined (TODO)
- /* PowerPC e200z0 core */
- POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200)
+ POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200,
+ "PowerPC e200z0 core")
#endif
#if defined (TODO)
- /* PowerPC e200z1 core */
- POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200)
+ POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200,
+ "PowerPC e200z1 core")
#endif
#if defined (TODO)
- /* PowerPC e200z3 core */
- POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200)
+ POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200,
+ "PowerPC e200z3 core")
#endif
- /* PowerPC e200z5 core */
- POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200)
- /* PowerPC e200z6 core */
- POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200)
+ POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200,
+ "PowerPC e200z5 core")
+ POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200,
+ "PowerPC e200z6 core")
/* PowerPC e200 microcontrollers */
#if defined (TODO)
- /* MPC5514E */
- POWERPC_DEF_SVR("MPC5514E",
+ POWERPC_DEF_SVR("MPC5514E", "MPC5514E",
CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200)
#endif
#if defined (TODO)
- /* MPC5514E v0 */
- POWERPC_DEF_SVR("MPC5514E_v0",
+ POWERPC_DEF_SVR("MPC5514E_v0", "MPC5514E v0",
CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200)
#endif
#if defined (TODO)
- /* MPC5514E v1 */
- POWERPC_DEF_SVR("MPC5514E_v1",
+ POWERPC_DEF_SVR("MPC5514E_v1", "MPC5514E v1",
CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200)
#endif
#if defined (TODO)
- /* MPC5514G */
- POWERPC_DEF_SVR("MPC5514G",
+ POWERPC_DEF_SVR("MPC5514G", "MPC5514G",
CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200)
#endif
#if defined (TODO)
- /* MPC5514G v0 */
- POWERPC_DEF_SVR("MPC5514G_v0",
+ POWERPC_DEF_SVR("MPC5514G_v0", "MPC5514G v0",
CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200)
#endif
#if defined (TODO)
- /* MPC5514G v1 */
- POWERPC_DEF_SVR("MPC5514G_v1",
+ POWERPC_DEF_SVR("MPC5514G_v1", "MPC5514G v1",
CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200)
#endif
#if defined (TODO)
- /* MPC5515S */
- POWERPC_DEF_SVR("MPC5515S",
+ POWERPC_DEF_SVR("MPC5515S", "MPC5515S",
CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200)
#endif
#if defined (TODO)
- /* MPC5516E */
- POWERPC_DEF_SVR("MPC5516E",
+ POWERPC_DEF_SVR("MPC5516E", "MPC5516E",
CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200)
#endif
#if defined (TODO)
- /* MPC5516E v0 */
- POWERPC_DEF_SVR("MPC5516E_v0",
+ POWERPC_DEF_SVR("MPC5516E_v0", "MPC5516E v0",
CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200)
#endif
#if defined (TODO)
- /* MPC5516E v1 */
- POWERPC_DEF_SVR("MPC5516E_v1",
+ POWERPC_DEF_SVR("MPC5516E_v1", "MPC5516E v1",
CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200)
#endif
#if defined (TODO)
- /* MPC5516G */
- POWERPC_DEF_SVR("MPC5516G",
+ POWERPC_DEF_SVR("MPC5516G", "MPC5516G",
CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200)
#endif
#if defined (TODO)
- /* MPC5516G v0 */
- POWERPC_DEF_SVR("MPC5516G_v0",
+ POWERPC_DEF_SVR("MPC5516G_v0", "MPC5516G v0",
CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200)
#endif
#if defined (TODO)
- /* MPC5516G v1 */
- POWERPC_DEF_SVR("MPC5516G_v1",
+ POWERPC_DEF_SVR("MPC5516G_v1", "MPC5516G v1",
CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200)
#endif
#if defined (TODO)
- /* MPC5516S */
- POWERPC_DEF_SVR("MPC5516S",
+ POWERPC_DEF_SVR("MPC5516S", "MPC5516S",
CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200)
#endif
#if defined (TODO)
- /* MPC5533 */
- POWERPC_DEF_SVR("MPC5533",
+ POWERPC_DEF_SVR("MPC5533", "MPC5533",
CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200)
#endif
#if defined (TODO)
- /* MPC5534 */
- POWERPC_DEF_SVR("MPC5534",
+ POWERPC_DEF_SVR("MPC5534", "MPC5534",
CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200)
#endif
#if defined (TODO)
- /* MPC5553 */
- POWERPC_DEF_SVR("MPC5553",
+ POWERPC_DEF_SVR("MPC5553", "MPC5553",
CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200)
#endif
#if defined (TODO)
- /* MPC5554 */
- POWERPC_DEF_SVR("MPC5554",
+ POWERPC_DEF_SVR("MPC5554", "MPC5554",
CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200)
#endif
#if defined (TODO)
- /* MPC5561 */
- POWERPC_DEF_SVR("MPC5561",
+ POWERPC_DEF_SVR("MPC5561", "MPC5561",
CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200)
#endif
#if defined (TODO)
- /* MPC5565 */
- POWERPC_DEF_SVR("MPC5565",
+ POWERPC_DEF_SVR("MPC5565", "MPC5565",
CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200)
#endif
#if defined (TODO)
- /* MPC5566 */
- POWERPC_DEF_SVR("MPC5566",
+ POWERPC_DEF_SVR("MPC5566", "MPC5566",
CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200)
#endif
#if defined (TODO)
- /* MPC5567 */
- POWERPC_DEF_SVR("MPC5567",
+ POWERPC_DEF_SVR("MPC5567", "MPC5567",
CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200)
#endif
/* e300 family */
- /* PowerPC e300c1 core */
- POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300)
- /* PowerPC e300c2 core */
- POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300)
- /* PowerPC e300c3 core */
- POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300)
- /* PowerPC e300c4 core */
- POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300)
+ POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300,
+ "PowerPC e300c1 core")
+ POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300,
+ "PowerPC e300c2 core")
+ POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300,
+ "PowerPC e300c3 core")
+ POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300,
+ "PowerPC e300c4 core")
/* PowerPC e300 microcontrollers */
#if defined (TODO)
- /* MPC8313 */
- POWERPC_DEF_SVR("MPC8313",
+ POWERPC_DEF_SVR("MPC8313", "MPC8313",
CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300)
#endif
#if defined (TODO)
- /* MPC8313E */
- POWERPC_DEF_SVR("MPC8313E",
+ POWERPC_DEF_SVR("MPC8313E", "MPC8313E",
CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300)
#endif
#if defined (TODO)
- /* MPC8314 */
- POWERPC_DEF_SVR("MPC8314",
+ POWERPC_DEF_SVR("MPC8314", "MPC8314",
CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300)
#endif
#if defined (TODO)
- /* MPC8314E */
- POWERPC_DEF_SVR("MPC8314E",
+ POWERPC_DEF_SVR("MPC8314E", "MPC8314E",
CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300)
#endif
#if defined (TODO)
- /* MPC8315 */
- POWERPC_DEF_SVR("MPC8315",
+ POWERPC_DEF_SVR("MPC8315", "MPC8315",
CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300)
#endif
#if defined (TODO)
- /* MPC8315E */
- POWERPC_DEF_SVR("MPC8315E",
+ POWERPC_DEF_SVR("MPC8315E", "MPC8315E",
CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300)
#endif
#if defined (TODO)
- /* MPC8321 */
- POWERPC_DEF_SVR("MPC8321",
+ POWERPC_DEF_SVR("MPC8321", "MPC8321",
CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300)
#endif
#if defined (TODO)
- /* MPC8321E */
- POWERPC_DEF_SVR("MPC8321E",
+ POWERPC_DEF_SVR("MPC8321E", "MPC8321E",
CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300)
#endif
#if defined (TODO)
- /* MPC8323 */
- POWERPC_DEF_SVR("MPC8323",
+ POWERPC_DEF_SVR("MPC8323", "MPC8323",
CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300)
#endif
#if defined (TODO)
- /* MPC8323E */
- POWERPC_DEF_SVR("MPC8323E",
+ POWERPC_DEF_SVR("MPC8323E", "MPC8323E",
CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300)
#endif
- /* MPC8343 */
- POWERPC_DEF_SVR("MPC8343",
+ POWERPC_DEF_SVR("MPC8343", "MPC8343",
CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300)
- /* MPC8343A */
- POWERPC_DEF_SVR("MPC8343A",
+ POWERPC_DEF_SVR("MPC8343A", "MPC8343A",
CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300)
- /* MPC8343E */
- POWERPC_DEF_SVR("MPC8343E",
+ POWERPC_DEF_SVR("MPC8343E", "MPC8343E",
CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300)
- /* MPC8343EA */
- POWERPC_DEF_SVR("MPC8343EA",
+ POWERPC_DEF_SVR("MPC8343EA", "MPC8343EA",
CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300)
- /* MPC8347T */
- POWERPC_DEF_SVR("MPC8347T",
+ POWERPC_DEF_SVR("MPC8347T", "MPC8347T",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300)
- /* MPC8347P */
- POWERPC_DEF_SVR("MPC8347P",
+ POWERPC_DEF_SVR("MPC8347P", "MPC8347P",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300)
- /* MPC8347AT */
- POWERPC_DEF_SVR("MPC8347AT",
+ POWERPC_DEF_SVR("MPC8347AT", "MPC8347AT",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300)
- /* MPC8347AP */
- POWERPC_DEF_SVR("MPC8347AP",
+ POWERPC_DEF_SVR("MPC8347AP", "MPC8347AP",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300)
- /* MPC8347ET */
- POWERPC_DEF_SVR("MPC8347ET",
+ POWERPC_DEF_SVR("MPC8347ET", "MPC8347ET",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300)
- /* MPC8343EP */
- POWERPC_DEF_SVR("MPC8347EP",
+ POWERPC_DEF_SVR("MPC8347EP", "MPC8343EP",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300)
- /* MPC8347EAT */
- POWERPC_DEF_SVR("MPC8347EAT",
+ POWERPC_DEF_SVR("MPC8347EAT", "MPC8347EAT",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300)
- /* MPC8343EAP */
- POWERPC_DEF_SVR("MPC8347EAP",
+ POWERPC_DEF_SVR("MPC8347EAP", "MPC8343EAP",
CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300)
- /* MPC8349 */
- POWERPC_DEF_SVR("MPC8349",
+ POWERPC_DEF_SVR("MPC8349", "MPC8349",
CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300)
- /* MPC8349A */
- POWERPC_DEF_SVR("MPC8349A",
+ POWERPC_DEF_SVR("MPC8349A", "MPC8349A",
CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300)
- /* MPC8349E */
- POWERPC_DEF_SVR("MPC8349E",
+ POWERPC_DEF_SVR("MPC8349E", "MPC8349E",
CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300)
- /* MPC8349EA */
- POWERPC_DEF_SVR("MPC8349EA",
+ POWERPC_DEF_SVR("MPC8349EA", "MPC8349EA",
CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300)
#if defined (TODO)
- /* MPC8358E */
- POWERPC_DEF_SVR("MPC8358E",
+ POWERPC_DEF_SVR("MPC8358E", "MPC8358E",
CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300)
#endif
#if defined (TODO)
- /* MPC8360E */
- POWERPC_DEF_SVR("MPC8360E",
+ POWERPC_DEF_SVR("MPC8360E", "MPC8360E",
CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300)
#endif
- /* MPC8377 */
- POWERPC_DEF_SVR("MPC8377",
+ POWERPC_DEF_SVR("MPC8377", "MPC8377",
CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300)
- /* MPC8377E */
- POWERPC_DEF_SVR("MPC8377E",
+ POWERPC_DEF_SVR("MPC8377E", "MPC8377E",
CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300)
- /* MPC8378 */
- POWERPC_DEF_SVR("MPC8378",
+ POWERPC_DEF_SVR("MPC8378", "MPC8378",
CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300)
- /* MPC8378E */
- POWERPC_DEF_SVR("MPC8378E",
+ POWERPC_DEF_SVR("MPC8378E", "MPC8378E",
CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300)
- /* MPC8379 */
- POWERPC_DEF_SVR("MPC8379",
+ POWERPC_DEF_SVR("MPC8379", "MPC8379",
CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300)
- /* MPC8379E */
- POWERPC_DEF_SVR("MPC8379E",
+ POWERPC_DEF_SVR("MPC8379E", "MPC8379E",
CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300)
/* e500 family */
- /* PowerPC e500 v1.0 core */
- POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1)
- /* PowerPC e500 v2.0 core */
- POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1)
- /* PowerPC e500v2 v1.0 core */
- POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2)
- /* PowerPC e500v2 v2.0 core */
- POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2)
- /* PowerPC e500v2 v2.1 core */
- POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2)
- /* PowerPC e500v2 v2.2 core */
- POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2)
- /* PowerPC e500v2 v3.0 core */
- POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2)
- POWERPC_DEF_SVR("e500mc", CPU_POWERPC_e500mc, POWERPC_SVR_E500, e500mc)
+ POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1,
+ "PowerPC e500 v1.0 core")
+ POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1,
+ "PowerPC e500 v2.0 core")
+ POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2,
+ "PowerPC e500v2 v1.0 core")
+ POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2,
+ "PowerPC e500v2 v2.0 core")
+ POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2,
+ "PowerPC e500v2 v2.1 core")
+ POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2,
+ "PowerPC e500v2 v2.2 core")
+ POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2,
+ "PowerPC e500v2 v3.0 core")
+ POWERPC_DEF_SVR("e500mc", "e500mc",
+ CPU_POWERPC_e500mc, POWERPC_SVR_E500, e500mc)
#ifdef TARGET_PPC64
- POWERPC_DEF_SVR("e5500", CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500)
+ POWERPC_DEF_SVR("e5500", "e5500",
+ CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500)
#endif
/* PowerPC e500 microcontrollers */
- /* MPC8533 v1.0 */
- POWERPC_DEF_SVR("MPC8533_v10",
+ POWERPC_DEF_SVR("MPC8533_v10", "MPC8533 v1.0",
CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2)
- /* MPC8533 v1.1 */
- POWERPC_DEF_SVR("MPC8533_v11",
+ POWERPC_DEF_SVR("MPC8533_v11", "MPC8533 v1.1",
CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2)
- /* MPC8533E v1.0 */
- POWERPC_DEF_SVR("MPC8533E_v10",
+ POWERPC_DEF_SVR("MPC8533E_v10", "MPC8533E v1.0",
CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2)
- POWERPC_DEF_SVR("MPC8533E_v11",
+ POWERPC_DEF_SVR("MPC8533E_v11", "MPC8533E v1.1",
CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2)
- /* MPC8540 v1.0 */
- POWERPC_DEF_SVR("MPC8540_v10",
+ POWERPC_DEF_SVR("MPC8540_v10", "MPC8540 v1.0",
CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1)
- /* MPC8540 v2.0 */
- POWERPC_DEF_SVR("MPC8540_v20",
+ POWERPC_DEF_SVR("MPC8540_v20", "MPC8540 v2.0",
CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1)
- /* MPC8540 v2.1 */
- POWERPC_DEF_SVR("MPC8540_v21",
+ POWERPC_DEF_SVR("MPC8540_v21", "MPC8540 v2.1",
CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1)
- /* MPC8541 v1.0 */
- POWERPC_DEF_SVR("MPC8541_v10",
+ POWERPC_DEF_SVR("MPC8541_v10", "MPC8541 v1.0",
CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1)
- /* MPC8541 v1.1 */
- POWERPC_DEF_SVR("MPC8541_v11",
+ POWERPC_DEF_SVR("MPC8541_v11", "MPC8541 v1.1",
CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1)
- /* MPC8541E v1.0 */
- POWERPC_DEF_SVR("MPC8541E_v10",
+ POWERPC_DEF_SVR("MPC8541E_v10", "MPC8541E v1.0",
CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1)
- /* MPC8541E v1.1 */
- POWERPC_DEF_SVR("MPC8541E_v11",
+ POWERPC_DEF_SVR("MPC8541E_v11", "MPC8541E v1.1",
CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1)
- /* MPC8543 v1.0 */
- POWERPC_DEF_SVR("MPC8543_v10",
+ POWERPC_DEF_SVR("MPC8543_v10", "MPC8543 v1.0",
CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2)
- /* MPC8543 v1.1 */
- POWERPC_DEF_SVR("MPC8543_v11",
+ POWERPC_DEF_SVR("MPC8543_v11", "MPC8543 v1.1",
CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2)
- /* MPC8543 v2.0 */
- POWERPC_DEF_SVR("MPC8543_v20",
+ POWERPC_DEF_SVR("MPC8543_v20", "MPC8543 v2.0",
CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2)
- /* MPC8543 v2.1 */
- POWERPC_DEF_SVR("MPC8543_v21",
+ POWERPC_DEF_SVR("MPC8543_v21", "MPC8543 v2.1",
CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2)
- /* MPC8543E v1.0 */
- POWERPC_DEF_SVR("MPC8543E_v10",
+ POWERPC_DEF_SVR("MPC8543E_v10", "MPC8543E v1.0",
CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2)
- /* MPC8543E v1.1 */
- POWERPC_DEF_SVR("MPC8543E_v11",
+ POWERPC_DEF_SVR("MPC8543E_v11", "MPC8543E v1.1",
CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2)
- /* MPC8543E v2.0 */
- POWERPC_DEF_SVR("MPC8543E_v20",
+ POWERPC_DEF_SVR("MPC8543E_v20", "MPC8543E v2.0",
CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2)
- /* MPC8543E v2.1 */
- POWERPC_DEF_SVR("MPC8543E_v21",
+ POWERPC_DEF_SVR("MPC8543E_v21", "MPC8543E v2.1",
CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2)
- /* MPC8544 v1.0 */
- POWERPC_DEF_SVR("MPC8544_v10",
+ POWERPC_DEF_SVR("MPC8544_v10", "MPC8544 v1.0",
CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2)
- /* MPC8544 v1.1 */
- POWERPC_DEF_SVR("MPC8544_v11",
+ POWERPC_DEF_SVR("MPC8544_v11", "MPC8544 v1.1",
CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2)
- /* MPC8544E v1.0 */
- POWERPC_DEF_SVR("MPC8544E_v10",
+ POWERPC_DEF_SVR("MPC8544E_v10", "MPC8544E v1.0",
CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2)
- /* MPC8544E v1.1 */
- POWERPC_DEF_SVR("MPC8544E_v11",
+ POWERPC_DEF_SVR("MPC8544E_v11", "MPC8544E v1.1",
CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2)
- /* MPC8545 v2.0 */
- POWERPC_DEF_SVR("MPC8545_v20",
+ POWERPC_DEF_SVR("MPC8545_v20", "MPC8545 v2.0",
CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2)
- /* MPC8545 v2.1 */
- POWERPC_DEF_SVR("MPC8545_v21",
+ POWERPC_DEF_SVR("MPC8545_v21", "MPC8545 v2.1",
CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2)
- /* MPC8545E v2.0 */
- POWERPC_DEF_SVR("MPC8545E_v20",
+ POWERPC_DEF_SVR("MPC8545E_v20", "MPC8545E v2.0",
CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2)
- /* MPC8545E v2.1 */
- POWERPC_DEF_SVR("MPC8545E_v21",
+ POWERPC_DEF_SVR("MPC8545E_v21", "MPC8545E v2.1",
CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2)
- /* MPC8547E v2.0 */
- POWERPC_DEF_SVR("MPC8547E_v20",
+ POWERPC_DEF_SVR("MPC8547E_v20", "MPC8547E v2.0",
CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2)
- /* MPC8547E v2.1 */
- POWERPC_DEF_SVR("MPC8547E_v21",
+ POWERPC_DEF_SVR("MPC8547E_v21", "MPC8547E v2.1",
CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2)
- /* MPC8548 v1.0 */
- POWERPC_DEF_SVR("MPC8548_v10",
+ POWERPC_DEF_SVR("MPC8548_v10", "MPC8548 v1.0",
CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2)
- /* MPC8548 v1.1 */
- POWERPC_DEF_SVR("MPC8548_v11",
+ POWERPC_DEF_SVR("MPC8548_v11", "MPC8548 v1.1",
CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2)
- /* MPC8548 v2.0 */
- POWERPC_DEF_SVR("MPC8548_v20",
+ POWERPC_DEF_SVR("MPC8548_v20", "MPC8548 v2.0",
CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2)
- /* MPC8548 v2.1 */
- POWERPC_DEF_SVR("MPC8548_v21",
+ POWERPC_DEF_SVR("MPC8548_v21", "MPC8548 v2.1",
CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2)
- /* MPC8548E v1.0 */
- POWERPC_DEF_SVR("MPC8548E_v10",
+ POWERPC_DEF_SVR("MPC8548E_v10", "MPC8548E v1.0",
CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2)
- /* MPC8548E v1.1 */
- POWERPC_DEF_SVR("MPC8548E_v11",
+ POWERPC_DEF_SVR("MPC8548E_v11", "MPC8548E v1.1",
CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2)
- /* MPC8548E v2.0 */
- POWERPC_DEF_SVR("MPC8548E_v20",
+ POWERPC_DEF_SVR("MPC8548E_v20", "MPC8548E v2.0",
CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2)
- /* MPC8548E v2.1 */
- POWERPC_DEF_SVR("MPC8548E_v21",
+ POWERPC_DEF_SVR("MPC8548E_v21", "MPC8548E v2.1",
CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2)
- /* MPC8555 v1.0 */
- POWERPC_DEF_SVR("MPC8555_v10",
+ POWERPC_DEF_SVR("MPC8555_v10", "MPC8555 v1.0",
CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2)
- /* MPC8555 v1.1 */
- POWERPC_DEF_SVR("MPC8555_v11",
+ POWERPC_DEF_SVR("MPC8555_v11", "MPC8555 v1.1",
CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2)
- /* MPC8555E v1.0 */
- POWERPC_DEF_SVR("MPC8555E_v10",
+ POWERPC_DEF_SVR("MPC8555E_v10", "MPC8555E v1.0",
CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2)
- /* MPC8555E v1.1 */
- POWERPC_DEF_SVR("MPC8555E_v11",
+ POWERPC_DEF_SVR("MPC8555E_v11", "MPC8555E v1.1",
CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2)
- /* MPC8560 v1.0 */
- POWERPC_DEF_SVR("MPC8560_v10",
+ POWERPC_DEF_SVR("MPC8560_v10", "MPC8560 v1.0",
CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2)
- /* MPC8560 v2.0 */
- POWERPC_DEF_SVR("MPC8560_v20",
+ POWERPC_DEF_SVR("MPC8560_v20", "MPC8560 v2.0",
CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2)
- /* MPC8560 v2.1 */
- POWERPC_DEF_SVR("MPC8560_v21",
+ POWERPC_DEF_SVR("MPC8560_v21", "MPC8560 v2.1",
CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2)
- /* MPC8567 */
- POWERPC_DEF_SVR("MPC8567",
+ POWERPC_DEF_SVR("MPC8567", "MPC8567",
CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2)
- /* MPC8567E */
- POWERPC_DEF_SVR("MPC8567E",
+ POWERPC_DEF_SVR("MPC8567E", "MPC8567E",
CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2)
- /* MPC8568 */
- POWERPC_DEF_SVR("MPC8568",
+ POWERPC_DEF_SVR("MPC8568", "MPC8568",
CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2)
- /* MPC8568E */
- POWERPC_DEF_SVR("MPC8568E",
+ POWERPC_DEF_SVR("MPC8568E", "MPC8568E",
CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2)
- /* MPC8572 */
- POWERPC_DEF_SVR("MPC8572",
+ POWERPC_DEF_SVR("MPC8572", "MPC8572",
CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2)
- /* MPC8572E */
- POWERPC_DEF_SVR("MPC8572E",
+ POWERPC_DEF_SVR("MPC8572E", "MPC8572E",
CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2)
/* e600 family */
- /* PowerPC e600 core */
- POWERPC_DEF("e600", CPU_POWERPC_e600, 7400)
+ POWERPC_DEF("e600", CPU_POWERPC_e600, 7400,
+ "PowerPC e600 core")
/* PowerPC e600 microcontrollers */
#if defined (TODO)
- /* MPC8610 */
- POWERPC_DEF_SVR("MPC8610",
+ POWERPC_DEF_SVR("MPC8610", "MPC8610",
CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400)
#endif
- /* MPC8641 */
- POWERPC_DEF_SVR("MPC8641",
+ POWERPC_DEF_SVR("MPC8641", "MPC8641",
CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400)
- /* MPC8641D */
- POWERPC_DEF_SVR("MPC8641D",
+ POWERPC_DEF_SVR("MPC8641D", "MPC8641D",
CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400)
/* 32 bits "classic" PowerPC */
/* PowerPC 6xx family */
- /* PowerPC 601v0 */
- POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601)
- /* PowerPC 601v1 */
- POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601)
- /* PowerPC 601v2 */
- POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v)
- /* PowerPC 602 */
- POWERPC_DEF("602", CPU_POWERPC_602, 602)
- /* PowerPC 603 */
- POWERPC_DEF("603", CPU_POWERPC_603, 603)
- /* PowerPC 603e v1.1 */
- POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E)
- /* PowerPC 603e v1.2 */
- POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E)
- /* PowerPC 603e v1.3 */
- POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E)
- /* PowerPC 603e v1.4 */
- POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E)
- /* PowerPC 603e v2.2 */
- POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E)
- /* PowerPC 603e v3 */
- POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E)
- /* PowerPC 603e v4 */
- POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E)
- /* PowerPC 603e v4.1 */
- POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E)
- /* PowerPC 603e (aka PID7) */
- POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E)
- /* PowerPC 603e7t */
- POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E)
- /* PowerPC 603e7v */
- POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E)
- /* PowerPC 603e7v1 */
- POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E)
- /* PowerPC 603e7v2 */
- POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E)
- /* PowerPC 603p (aka PID7v) */
- POWERPC_DEF("603p", CPU_POWERPC_603P, 603E)
- /* PowerPC 604 */
- POWERPC_DEF("604", CPU_POWERPC_604, 604)
- /* PowerPC 604e v1.0 */
- POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E)
- /* PowerPC 604e v2.2 */
- POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E)
- /* PowerPC 604e v2.4 */
- POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E)
- /* PowerPC 604r (aka PIDA) */
- POWERPC_DEF("604r", CPU_POWERPC_604R, 604E)
+ POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601,
+ "PowerPC 601v0")
+ POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601,
+ "PowerPC 601v1")
+ POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v,
+ "PowerPC 601v2")
+ POWERPC_DEF("602", CPU_POWERPC_602, 602,
+ "PowerPC 602")
+ POWERPC_DEF("603", CPU_POWERPC_603, 603,
+ "PowerPC 603")
+ POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E,
+ "PowerPC 603e v1.1")
+ POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E,
+ "PowerPC 603e v1.2")
+ POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E,
+ "PowerPC 603e v1.3")
+ POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E,
+ "PowerPC 603e v1.4")
+ POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E,
+ "PowerPC 603e v2.2")
+ POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E,
+ "PowerPC 603e v3")
+ POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E,
+ "PowerPC 603e v4")
+ POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E,
+ "PowerPC 603e v4.1")
+ POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E,
+ "PowerPC 603e (aka PID7)")
+ POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E,
+ "PowerPC 603e7t")
+ POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E,
+ "PowerPC 603e7v")
+ POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E,
+ "PowerPC 603e7v1")
+ POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E,
+ "PowerPC 603e7v2")
+ POWERPC_DEF("603p", CPU_POWERPC_603P, 603E,
+ "PowerPC 603p (aka PID7v)")
+ POWERPC_DEF("604", CPU_POWERPC_604, 604,
+ "PowerPC 604")
+ POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E,
+ "PowerPC 604e v1.0")
+ POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E,
+ "PowerPC 604e v2.2")
+ POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E,
+ "PowerPC 604e v2.4")
+ POWERPC_DEF("604r", CPU_POWERPC_604R, 604E,
+ "PowerPC 604r (aka PIDA)")
#if defined(TODO)
- /* PowerPC 604ev */
- POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E)
+ POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E,
+ "PowerPC 604ev")
#endif
/* PowerPC 7xx family */
- /* PowerPC 740 v1.0 (G3) */
- POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740)
- /* PowerPC 750 v1.0 (G3) */
- POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750)
- /* PowerPC 740 v2.0 (G3) */
- POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740)
- /* PowerPC 750 v2.0 (G3) */
- POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750)
- /* PowerPC 740 v2.1 (G3) */
- POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740)
- /* PowerPC 750 v2.1 (G3) */
- POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750)
- /* PowerPC 740 v2.2 (G3) */
- POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740)
- /* PowerPC 750 v2.2 (G3) */
- POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750)
- /* PowerPC 740 v3.0 (G3) */
- POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740)
- /* PowerPC 750 v3.0 (G3) */
- POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750)
- /* PowerPC 740 v3.1 (G3) */
- POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740)
- /* PowerPC 750 v3.1 (G3) */
- POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750)
- /* PowerPC 740E (G3) */
- POWERPC_DEF("740e", CPU_POWERPC_740E, 740)
- /* PowerPC 750E (G3) */
- POWERPC_DEF("750e", CPU_POWERPC_750E, 750)
- /* PowerPC 740P (G3) */
- POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740)
- /* PowerPC 750P (G3) */
- POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750)
- /* PowerPC 750CL v1.0 */
- POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl)
- /* PowerPC 750CL v2.0 */
- POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl)
- /* PowerPC 750CX v1.0 (G3 embedded) */
- POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx)
- /* PowerPC 750CX v2.1 (G3 embedded) */
- POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx)
- /* PowerPC 750CX v2.1 (G3 embedded) */
- POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx)
- /* PowerPC 750CX v2.2 (G3 embedded) */
- POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx)
- /* PowerPC 750CXe v2.1 (G3 embedded) */
- POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx)
- /* PowerPC 750CXe v2.2 (G3 embedded) */
- POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx)
- /* PowerPC 750CXe v2.3 (G3 embedded) */
- POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx)
- /* PowerPC 750CXe v2.4 (G3 embedded) */
- POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx)
- /* PowerPC 750CXe v2.4b (G3 embedded) */
- POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx)
- /* PowerPC 750CXe v3.0 (G3 embedded) */
- POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx)
- /* PowerPC 750CXe v3.1 (G3 embedded) */
- POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx)
- /* PowerPC 750CXe v3.1b (G3 embedded) */
- POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx)
- /* PowerPC 750CXr (G3 embedded) */
- POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx)
- /* PowerPC 750FL (G3 embedded) */
- POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx)
- /* PowerPC 750FX v1.0 (G3 embedded) */
- POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx)
- /* PowerPC 750FX v2.0 (G3 embedded) */
- POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx)
- /* PowerPC 750FX v2.1 (G3 embedded) */
- POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx)
- /* PowerPC 750FX v2.2 (G3 embedded) */
- POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx)
- /* PowerPC 750FX v2.3 (G3 embedded) */
- POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx)
- /* PowerPC 750GL (G3 embedded) */
- POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx)
- /* PowerPC 750GX v1.0 (G3 embedded) */
- POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx)
- /* PowerPC 750GX v1.1 (G3 embedded) */
- POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx)
- /* PowerPC 750GX v1.2 (G3 embedded) */
- POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx)
- /* PowerPC 750L v2.0 (G3 embedded) */
- POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750)
- /* PowerPC 750L v2.1 (G3 embedded) */
- POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750)
- /* PowerPC 750L v2.2 (G3 embedded) */
- POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750)
- /* PowerPC 750L v3.0 (G3 embedded) */
- POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750)
- /* PowerPC 750L v3.2 (G3 embedded) */
- POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750)
- /* PowerPC 745 v1.0 */
- POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745)
- /* PowerPC 755 v1.0 */
- POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755)
- /* PowerPC 745 v1.1 */
- POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745)
- /* PowerPC 755 v1.1 */
- POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755)
- /* PowerPC 745 v2.0 */
- POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745)
- /* PowerPC 755 v2.0 */
- POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755)
- /* PowerPC 745 v2.1 */
- POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745)
- /* PowerPC 755 v2.1 */
- POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755)
- /* PowerPC 745 v2.2 */
- POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745)
- /* PowerPC 755 v2.2 */
- POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755)
- /* PowerPC 745 v2.3 */
- POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745)
- /* PowerPC 755 v2.3 */
- POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755)
- /* PowerPC 745 v2.4 */
- POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745)
- /* PowerPC 755 v2.4 */
- POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755)
- /* PowerPC 745 v2.5 */
- POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745)
- /* PowerPC 755 v2.5 */
- POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755)
- /* PowerPC 745 v2.6 */
- POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745)
- /* PowerPC 755 v2.6 */
- POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755)
- /* PowerPC 745 v2.7 */
- POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745)
- /* PowerPC 755 v2.7 */
- POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755)
- /* PowerPC 745 v2.8 */
- POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745)
- /* PowerPC 755 v2.8 */
- POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755)
+ POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740,
+ "PowerPC 740 v1.0 (G3)")
+ POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750,
+ "PowerPC 750 v1.0 (G3)")
+ POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740,
+ "PowerPC 740 v2.0 (G3)")
+ POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750,
+ "PowerPC 750 v2.0 (G3)")
+ POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740,
+ "PowerPC 740 v2.1 (G3)")
+ POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750,
+ "PowerPC 750 v2.1 (G3)")
+ POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740,
+ "PowerPC 740 v2.2 (G3)")
+ POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750,
+ "PowerPC 750 v2.2 (G3)")
+ POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740,
+ "PowerPC 740 v3.0 (G3)")
+ POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750,
+ "PowerPC 750 v3.0 (G3)")
+ POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740,
+ "PowerPC 740 v3.1 (G3)")
+ POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750,
+ "PowerPC 750 v3.1 (G3)")
+ POWERPC_DEF("740e", CPU_POWERPC_740E, 740,
+ "PowerPC 740E (G3)")
+ POWERPC_DEF("750e", CPU_POWERPC_750E, 750,
+ "PowerPC 750E (G3)")
+ POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740,
+ "PowerPC 740P (G3)")
+ POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750,
+ "PowerPC 750P (G3)")
+ POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl,
+ "PowerPC 750CL v1.0")
+ POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl,
+ "PowerPC 750CL v2.0")
+ POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx,
+ "PowerPC 750CX v1.0 (G3 embedded)")
+ POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx,
+ "PowerPC 750CX v2.1 (G3 embedded)")
+ POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx,
+ "PowerPC 750CX v2.1 (G3 embedded)")
+ POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx,
+ "PowerPC 750CX v2.2 (G3 embedded)")
+ POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx,
+ "PowerPC 750CXe v2.1 (G3 embedded)")
+ POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx,
+ "PowerPC 750CXe v2.2 (G3 embedded)")
+ POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx,
+ "PowerPC 750CXe v2.3 (G3 embedded)")
+ POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx,
+ "PowerPC 750CXe v2.4 (G3 embedded)")
+ POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx,
+ "PowerPC 750CXe v2.4b (G3 embedded)")
+ POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx,
+ "PowerPC 750CXe v3.0 (G3 embedded)")
+ POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx,
+ "PowerPC 750CXe v3.1 (G3 embedded)")
+ POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx,
+ "PowerPC 750CXe v3.1b (G3 embedded)")
+ POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx,
+ "PowerPC 750CXr (G3 embedded)")
+ POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx,
+ "PowerPC 750FL (G3 embedded)")
+ POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx,
+ "PowerPC 750FX v1.0 (G3 embedded)")
+ POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx,
+ "PowerPC 750FX v2.0 (G3 embedded)")
+ POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx,
+ "PowerPC 750FX v2.1 (G3 embedded)")
+ POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx,
+ "PowerPC 750FX v2.2 (G3 embedded)")
+ POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx,
+ "PowerPC 750FX v2.3 (G3 embedded)")
+ POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx,
+ "PowerPC 750GL (G3 embedded)")
+ POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx,
+ "PowerPC 750GX v1.0 (G3 embedded)")
+ POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx,
+ "PowerPC 750GX v1.1 (G3 embedded)")
+ POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx,
+ "PowerPC 750GX v1.2 (G3 embedded)")
+ POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750,
+ "PowerPC 750L v2.0 (G3 embedded)")
+ POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750,
+ "PowerPC 750L v2.1 (G3 embedded)")
+ POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750,
+ "PowerPC 750L v2.2 (G3 embedded)")
+ POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750,
+ "PowerPC 750L v3.0 (G3 embedded)")
+ POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750,
+ "PowerPC 750L v3.2 (G3 embedded)")
+ POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745,
+ "PowerPC 745 v1.0")
+ POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755,
+ "PowerPC 755 v1.0")
+ POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745,
+ "PowerPC 745 v1.1")
+ POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755,
+ "PowerPC 755 v1.1")
+ POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745,
+ "PowerPC 745 v2.0")
+ POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755,
+ "PowerPC 755 v2.0")
+ POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745,
+ "PowerPC 745 v2.1")
+ POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755,
+ "PowerPC 755 v2.1")
+ POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745,
+ "PowerPC 745 v2.2")
+ POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755,
+ "PowerPC 755 v2.2")
+ POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745,
+ "PowerPC 745 v2.3")
+ POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755,
+ "PowerPC 755 v2.3")
+ POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745,
+ "PowerPC 745 v2.4")
+ POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755,
+ "PowerPC 755 v2.4")
+ POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745,
+ "PowerPC 745 v2.5")
+ POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755,
+ "PowerPC 755 v2.5")
+ POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745,
+ "PowerPC 745 v2.6")
+ POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755,
+ "PowerPC 755 v2.6")
+ POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745,
+ "PowerPC 745 v2.7")
+ POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755,
+ "PowerPC 755 v2.7")
+ POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745,
+ "PowerPC 745 v2.8")
+ POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755,
+ "PowerPC 755 v2.8")
#if defined (TODO)
- /* PowerPC 745P (G3) */
- POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745)
- /* PowerPC 755P (G3) */
- POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755)
+ POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745,
+ "PowerPC 745P (G3)")
+ POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755,
+ "PowerPC 755P (G3)")
#endif
/* PowerPC 74xx family */
- /* PowerPC 7400 v1.0 (G4) */
- POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400)
- /* PowerPC 7400 v1.1 (G4) */
- POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400)
- /* PowerPC 7400 v2.0 (G4) */
- POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400)
- /* PowerPC 7400 v2.1 (G4) */
- POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400)
- /* PowerPC 7400 v2.2 (G4) */
- POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400)
- /* PowerPC 7400 v2.6 (G4) */
- POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400)
- /* PowerPC 7400 v2.7 (G4) */
- POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400)
- /* PowerPC 7400 v2.8 (G4) */
- POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400)
- /* PowerPC 7400 v2.9 (G4) */
- POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400)
- /* PowerPC 7410 v1.0 (G4) */
- POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410)
- /* PowerPC 7410 v1.1 (G4) */
- POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410)
- /* PowerPC 7410 v1.2 (G4) */
- POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410)
- /* PowerPC 7410 v1.3 (G4) */
- POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410)
- /* PowerPC 7410 v1.4 (G4) */
- POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410)
- /* PowerPC 7448 v1.0 (G4) */
- POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400)
- /* PowerPC 7448 v1.1 (G4) */
- POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400)
- /* PowerPC 7448 v2.0 (G4) */
- POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400)
- /* PowerPC 7448 v2.1 (G4) */
- POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400)
- /* PowerPC 7450 v1.0 (G4) */
- POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450)
- /* PowerPC 7450 v1.1 (G4) */
- POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450)
- /* PowerPC 7450 v1.2 (G4) */
- POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450)
- /* PowerPC 7450 v2.0 (G4) */
- POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450)
- /* PowerPC 7450 v2.1 (G4) */
- POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450)
- /* PowerPC 7441 v2.1 (G4) */
- POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440)
- /* PowerPC 7441 v2.3 (G4) */
- POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440)
- /* PowerPC 7451 v2.3 (G4) */
- POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450)
- /* PowerPC 7441 v2.10 (G4) */
- POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440)
- /* PowerPC 7451 v2.10 (G4) */
- POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450)
- /* PowerPC 7445 v1.0 (G4) */
- POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445)
- /* PowerPC 7455 v1.0 (G4) */
- POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455)
- /* PowerPC 7445 v2.1 (G4) */
- POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445)
- /* PowerPC 7455 v2.1 (G4) */
- POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455)
- /* PowerPC 7445 v3.2 (G4) */
- POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445)
- /* PowerPC 7455 v3.2 (G4) */
- POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455)
- /* PowerPC 7445 v3.3 (G4) */
- POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445)
- /* PowerPC 7455 v3.3 (G4) */
- POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455)
- /* PowerPC 7445 v3.4 (G4) */
- POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445)
- /* PowerPC 7455 v3.4 (G4) */
- POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455)
- /* PowerPC 7447 v1.0 (G4) */
- POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445)
- /* PowerPC 7457 v1.0 (G4) */
- POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455)
- /* PowerPC 7447 v1.1 (G4) */
- POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445)
- /* PowerPC 7457 v1.1 (G4) */
- POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455)
- /* PowerPC 7457 v1.2 (G4) */
- POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455)
- /* PowerPC 7447A v1.0 (G4) */
- POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445)
- /* PowerPC 7457A v1.0 (G4) */
- POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455)
- /* PowerPC 7447A v1.1 (G4) */
- POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445)
- /* PowerPC 7457A v1.1 (G4) */
- POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455)
- /* PowerPC 7447A v1.2 (G4) */
- POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445)
- /* PowerPC 7457A v1.2 (G4) */
- POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455)
+ POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400,
+ "PowerPC 7400 v1.0 (G4)")
+ POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400,
+ "PowerPC 7400 v1.1 (G4)")
+ POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400,
+ "PowerPC 7400 v2.0 (G4)")
+ POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400,
+ "PowerPC 7400 v2.1 (G4)")
+ POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400,
+ "PowerPC 7400 v2.2 (G4)")
+ POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400,
+ "PowerPC 7400 v2.6 (G4)")
+ POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400,
+ "PowerPC 7400 v2.7 (G4)")
+ POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400,
+ "PowerPC 7400 v2.8 (G4)")
+ POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400,
+ "PowerPC 7400 v2.9 (G4)")
+ POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410,
+ "PowerPC 7410 v1.0 (G4)")
+ POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410,
+ "PowerPC 7410 v1.1 (G4)")
+ POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410,
+ "PowerPC 7410 v1.2 (G4)")
+ POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410,
+ "PowerPC 7410 v1.3 (G4)")
+ POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410,
+ "PowerPC 7410 v1.4 (G4)")
+ POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400,
+ "PowerPC 7448 v1.0 (G4)")
+ POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400,
+ "PowerPC 7448 v1.1 (G4)")
+ POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400,
+ "PowerPC 7448 v2.0 (G4)")
+ POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400,
+ "PowerPC 7448 v2.1 (G4)")
+ POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450,
+ "PowerPC 7450 v1.0 (G4)")
+ POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450,
+ "PowerPC 7450 v1.1 (G4)")
+ POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450,
+ "PowerPC 7450 v1.2 (G4)")
+ POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450,
+ "PowerPC 7450 v2.0 (G4)")
+ POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450,
+ "PowerPC 7450 v2.1 (G4)")
+ POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440,
+ "PowerPC 7441 v2.1 (G4)")
+ POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440,
+ "PowerPC 7441 v2.3 (G4)")
+ POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450,
+ "PowerPC 7451 v2.3 (G4)")
+ POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440,
+ "PowerPC 7441 v2.10 (G4)")
+ POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450,
+ "PowerPC 7451 v2.10 (G4)")
+ POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445,
+ "PowerPC 7445 v1.0 (G4)")
+ POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455,
+ "PowerPC 7455 v1.0 (G4)")
+ POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445,
+ "PowerPC 7445 v2.1 (G4)")
+ POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455,
+ "PowerPC 7455 v2.1 (G4)")
+ POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445,
+ "PowerPC 7445 v3.2 (G4)")
+ POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455,
+ "PowerPC 7455 v3.2 (G4)")
+ POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445,
+ "PowerPC 7445 v3.3 (G4)")
+ POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455,
+ "PowerPC 7455 v3.3 (G4)")
+ POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445,
+ "PowerPC 7445 v3.4 (G4)")
+ POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455,
+ "PowerPC 7455 v3.4 (G4)")
+ POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445,
+ "PowerPC 7447 v1.0 (G4)")
+ POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455,
+ "PowerPC 7457 v1.0 (G4)")
+ POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445,
+ "PowerPC 7447 v1.1 (G4)")
+ POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455,
+ "PowerPC 7457 v1.1 (G4)")
+ POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455,
+ "PowerPC 7457 v1.2 (G4)")
+ POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445,
+ "PowerPC 7447A v1.0 (G4)")
+ POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455,
+ "PowerPC 7457A v1.0 (G4)")
+ POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445,
+ "PowerPC 7447A v1.1 (G4)")
+ POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455,
+ "PowerPC 7457A v1.1 (G4)")
+ POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445,
+ "PowerPC 7447A v1.2 (G4)")
+ POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455,
+ "PowerPC 7457A v1.2 (G4)")
/* 64 bits PowerPC */
#if defined (TARGET_PPC64)
- /* PowerPC 620 */
- POWERPC_DEF("620", CPU_POWERPC_620, 620)
+ POWERPC_DEF("620", CPU_POWERPC_620, 620,
+ "PowerPC 620")
#if defined (TODO)
- /* PowerPC 630 (POWER3) */
- POWERPC_DEF("630", CPU_POWERPC_630, 630)
+ POWERPC_DEF("630", CPU_POWERPC_630, 630,
+ "PowerPC 630 (POWER3)")
#endif
#if defined (TODO)
- /* PowerPC 631 (Power 3+) */
- POWERPC_DEF("631", CPU_POWERPC_631, 631)
+ POWERPC_DEF("631", CPU_POWERPC_631, 631,
+ "PowerPC 631 (Power 3+)")
#endif
#if defined (TODO)
- /* POWER4 */
- POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4)
+ POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4,
+ "POWER4")
#endif
#if defined (TODO)
- /* POWER4p */
- POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P)
+ POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P,
+ "POWER4p")
#endif
#if defined (TODO)
- /* POWER5 */
- POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5)
- /* POWER5GR */
- POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5)
+ POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5,
+ "POWER5")
+ POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5,
+ "POWER5GR")
#endif
#if defined (TODO)
- /* POWER5+ */
- POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P)
- /* POWER5GS */
- POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P)
+ POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P,
+ "POWER5+")
+ POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P,
+ "POWER5GS")
#endif
#if defined (TODO)
- /* POWER6 */
- POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6)
- /* POWER6 running in POWER5 mode */
- POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5)
- /* POWER6A */
- POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6)
-#endif
- /* POWER7 */
- POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7)
- POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7)
- POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7)
- /* PowerPC 970 */
- POWERPC_DEF("970", CPU_POWERPC_970, 970)
- /* PowerPC 970FX v1.0 (G5) */
- POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX)
- /* PowerPC 970FX v2.0 (G5) */
- POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX)
- /* PowerPC 970FX v2.1 (G5) */
- POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX)
- /* PowerPC 970FX v3.0 (G5) */
- POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX)
- /* PowerPC 970FX v3.1 (G5) */
- POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX)
- /* PowerPC 970GX (G5) */
- POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX)
- /* PowerPC 970MP v1.0 */
- POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP)
- /* PowerPC 970MP v1.1 */
- POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP)
+ POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6,
+ "POWER6")
+ POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5,
+ "POWER6 running in POWER5 mode")
+ POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6,
+ "POWER6A")
+#endif
+ POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7,
+ "POWER7 v2.0")
+ POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7,
+ "POWER7 v2.1")
+ POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7,
+ "POWER7 v2.3")
+ POWERPC_DEF("970", CPU_POWERPC_970, 970,
+ "PowerPC 970")
+ POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX,
+ "PowerPC 970FX v1.0 (G5)")
+ POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX,
+ "PowerPC 970FX v2.0 (G5)")
+ POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX,
+ "PowerPC 970FX v2.1 (G5)")
+ POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX,
+ "PowerPC 970FX v3.0 (G5)")
+ POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX,
+ "PowerPC 970FX v3.1 (G5)")
+ POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX,
+ "PowerPC 970GX (G5)")
+ POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP,
+ "PowerPC 970MP v1.0")
+ POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP,
+ "PowerPC 970MP v1.1")
#if defined (TODO)
- /* PowerPC Cell */
- POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970)
+ POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970,
+ "PowerPC Cell")
#endif
#if defined (TODO)
- /* PowerPC Cell v1.0 */
- POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970)
+ POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970,
+ "PowerPC Cell v1.0")
#endif
#if defined (TODO)
- /* PowerPC Cell v2.0 */
- POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970)
+ POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970,
+ "PowerPC Cell v2.0")
#endif
#if defined (TODO)
- /* PowerPC Cell v3.0 */
- POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970)
+ POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970,
+ "PowerPC Cell v3.0")
#endif
#if defined (TODO)
- /* PowerPC Cell v3.1 */
- POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970)
+ POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970,
+ "PowerPC Cell v3.1")
#endif
#if defined (TODO)
- /* PowerPC Cell v3.2 */
- POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970)
+ POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970,
+ "PowerPC Cell v3.2")
#endif
#if defined (TODO)
- /* RS64 (Apache/A35) */
/* This one seems to support the whole POWER2 instruction set
* and the PowerPC 64 one.
*/
/* What about A10 & A30 ? */
- POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64)
+ POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64,
+ "RS64 (Apache/A35)")
#endif
#if defined (TODO)
- /* RS64-II (NorthStar/A50) */
- POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64)
+ POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64,
+ "RS64-II (NorthStar/A50)")
#endif
#if defined (TODO)
- /* RS64-III (Pulsar) */
- POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64)
+ POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64,
+ "RS64-III (Pulsar)")
#endif
#if defined (TODO)
- /* RS64-IV (IceStar/IStar/SStar) */
- POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64)
+ POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64,
+ "RS64-IV (IceStar/IStar/SStar)")
#endif
#endif /* defined (TARGET_PPC64) */
/* POWER */
#if defined (TODO)
- /* Original POWER */
- POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER)
+ POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER,
+ "Original POWER")
#endif
#if defined (TODO)
- /* POWER2 */
- POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER)
+ POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER,
+ "POWER2")
#endif
/* PA semi cores */
#if defined (TODO)
- /* PA PA6T */
- POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T)
+ POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T,
+ "PA PA6T")
#endif
typedef struct PowerPCCPUAlias {
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 51/66] target-ppc: Update Coding Style for CPU models
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (49 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 50/66] target-ppc: Turn descriptive CPU model " Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 52/66] target-ppc: Split model definitions out of translate_init.c Alexander Graf
` (15 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Drop the space in #if defined (TODO).
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 200 +++++++++++++++++++++---------------------
1 files changed, 100 insertions(+), 100 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index bd5230c..31566e0 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7923,7 +7923,7 @@ enum {
"PowerPC 401A1")
POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2,
"PowerPC 401B2")
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3,
"PowerPC 401B3")
#endif
@@ -7939,7 +7939,7 @@ enum {
POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2,
"PowerPC 401G2")
/* PowerPC 401 microcontrolers */
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401,
"PowerPC 401GF")
#endif
@@ -7947,7 +7947,7 @@ enum {
"IOP480 (401 microcontroller)")
POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401,
"IBM Processor for Network Resources")
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401,
NULL)
#endif
@@ -7961,61 +7961,61 @@ enum {
"PowerPC 403 GC")
POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX,
"PowerPC 403 GCX")
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403,
"PowerPC 403 GP")
#endif
/* PowerPC 405 family */
/* PowerPC 405 cores */
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405,
"PowerPC 405 A3")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405,
"PowerPC 405 A4")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405,
"PowerPC 405 B3")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405,
"PowerPC 405 B4")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405,
"PowerPC 405 C3")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405,
"PowerPC 405 C4")
#endif
POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405,
"PowerPC 405 D2")
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405,
"PowerPC 405 D3")
#endif
POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405,
"PowerPC 405 D4")
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405,
"PowerPC 405 D5")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405,
"PowerPC 405 E4")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405,
"PowerPC 405 F4")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405,
"PowerPC 405 F5")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405,
"PowerPC 405 F6")
#endif
@@ -8078,38 +8078,38 @@ enum {
"Npe405 L")
POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405,
"Npe4GS3")
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405,
NULL)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405,
NULL)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405,
"PowerPC LC77700 (Sanyo)")
#endif
/* PowerPC 401/403/405 based set-top-box microcontrolers */
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2,
"STB010000")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2,
"STB01010")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3,
"STB0210")
#endif
POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405,
"STB03xx")
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405,
"STB043x")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405,
"STB045x")
#endif
@@ -8117,7 +8117,7 @@ enum {
"STB04xx")
POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405,
"STB25xx")
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405,
"STB130")
#endif
@@ -8126,19 +8126,19 @@ enum {
NULL)
POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405,
NULL)
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405,
"Zarlink ZL10310")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405,
"Zarlink ZL10311")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405,
"Zarlink ZL10320")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405,
"Zarlink ZL10321")
#endif
@@ -8148,37 +8148,37 @@ enum {
"Generic PowerPC 440")
#endif
/* PowerPC 440 cores */
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4,
"PowerPC 440 A4")
#endif
POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5,
"PowerPC 440 Xilinx 5")
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5,
"PowerPC 440 A5")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4,
"PowerPC 440 B4")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4,
"PowerPC 440 G4")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5,
"PowerPC 440 F5")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5,
"PowerPC 440 G5")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4,
"PowerPC 440H4")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5,
"PowerPC 440H6")
#endif
@@ -8238,16 +8238,16 @@ enum {
"PowerPC 440 SPE")
#endif
/* PowerPC 460 family */
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("464", CPU_POWERPC_464, 460,
"Generic PowerPC 464")
#endif
/* PowerPC 464 microcontrolers */
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460,
"PowerPC 464H90")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F,
"PowerPC 464H90F")
#endif
@@ -8303,19 +8303,19 @@ enum {
POWERPC_DEF_SVR("MPC5200B_v21", "MPC5200B v2.1",
CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
/* e200 family */
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC55xx", "Generic MPC55xx core",
CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200,
"PowerPC e200z0 core")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200,
"PowerPC e200z1 core")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200,
"PowerPC e200z3 core")
#endif
@@ -8324,91 +8324,91 @@ enum {
POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200,
"PowerPC e200z6 core")
/* PowerPC e200 microcontrollers */
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5514E", "MPC5514E",
CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5514E_v0", "MPC5514E v0",
CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5514E_v1", "MPC5514E v1",
CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5514G", "MPC5514G",
CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5514G_v0", "MPC5514G v0",
CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5514G_v1", "MPC5514G v1",
CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5515S", "MPC5515S",
CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5516E", "MPC5516E",
CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5516E_v0", "MPC5516E v0",
CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5516E_v1", "MPC5516E v1",
CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5516G", "MPC5516G",
CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5516G_v0", "MPC5516G v0",
CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5516G_v1", "MPC5516G v1",
CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5516S", "MPC5516S",
CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5533", "MPC5533",
CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5534", "MPC5534",
CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5553", "MPC5553",
CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5554", "MPC5554",
CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5561", "MPC5561",
CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5565", "MPC5565",
CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5566", "MPC5566",
CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC5567", "MPC5567",
CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200)
#endif
@@ -8422,43 +8422,43 @@ enum {
POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300,
"PowerPC e300c4 core")
/* PowerPC e300 microcontrollers */
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC8313", "MPC8313",
CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC8313E", "MPC8313E",
CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC8314", "MPC8314",
CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC8314E", "MPC8314E",
CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC8315", "MPC8315",
CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC8315E", "MPC8315E",
CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC8321", "MPC8321",
CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC8321E", "MPC8321E",
CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC8323", "MPC8323",
CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC8323E", "MPC8323E",
CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300)
#endif
@@ -8494,11 +8494,11 @@ enum {
CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300)
POWERPC_DEF_SVR("MPC8349EA", "MPC8349EA",
CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300)
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC8358E", "MPC8358E",
CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300)
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC8360E", "MPC8360E",
CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300)
#endif
@@ -8640,7 +8640,7 @@ enum {
POWERPC_DEF("e600", CPU_POWERPC_e600, 7400,
"PowerPC e600 core")
/* PowerPC e600 microcontrollers */
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF_SVR("MPC8610", "MPC8610",
CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400)
#endif
@@ -8839,7 +8839,7 @@ enum {
"PowerPC 745 v2.8")
POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755,
"PowerPC 755 v2.8")
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745,
"PowerPC 745P (G3)")
POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755,
@@ -8948,35 +8948,35 @@ enum {
#if defined (TARGET_PPC64)
POWERPC_DEF("620", CPU_POWERPC_620, 620,
"PowerPC 620")
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("630", CPU_POWERPC_630, 630,
"PowerPC 630 (POWER3)")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("631", CPU_POWERPC_631, 631,
"PowerPC 631 (Power 3+)")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4,
"POWER4")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P,
"POWER4p")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5,
"POWER5")
POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5,
"POWER5GR")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P,
"POWER5+")
POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P,
"POWER5GS")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6,
"POWER6")
POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5,
@@ -9008,31 +9008,31 @@ enum {
"PowerPC 970MP v1.0")
POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP,
"PowerPC 970MP v1.1")
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970,
"PowerPC Cell")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970,
"PowerPC Cell v1.0")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970,
"PowerPC Cell v2.0")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970,
"PowerPC Cell v3.0")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970,
"PowerPC Cell v3.1")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970,
"PowerPC Cell v3.2")
#endif
-#if defined (TODO)
+#if defined(TODO)
/* This one seems to support the whole POWER2 instruction set
* and the PowerPC 64 one.
*/
@@ -9040,30 +9040,30 @@ enum {
POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64,
"RS64 (Apache/A35)")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64,
"RS64-II (NorthStar/A50)")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64,
"RS64-III (Pulsar)")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64,
"RS64-IV (IceStar/IStar/SStar)")
#endif
#endif /* defined (TARGET_PPC64) */
/* POWER */
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER,
"Original POWER")
#endif
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER,
"POWER2")
#endif
/* PA semi cores */
-#if defined (TODO)
+#if defined(TODO)
POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T,
"PA PA6T")
#endif
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 52/66] target-ppc: Split model definitions out of translate_init.c
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (50 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 51/66] target-ppc: Update Coding Style for CPU models Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 53/66] target-ppc: Fix remaining microcontroller typos among models Alexander Graf
` (14 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Now that model definitions only reference their parent type, model
definitions are independent of the family definitions and can be
compiled independently of TCG translation.
Keep all #if defined(TODO) code local to cpu-models.c.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/Makefile.objs | 1 +
target-ppc/cpu-models.c | 1225 +++++++++++++++++++++++++++
target-ppc/cpu-models.h | 727 ++++++++++++++++
target-ppc/translate_init.c | 1907 +------------------------------------------
4 files changed, 1955 insertions(+), 1905 deletions(-)
create mode 100644 target-ppc/cpu-models.c
create mode 100644 target-ppc/cpu-models.h
diff --git a/target-ppc/Makefile.objs b/target-ppc/Makefile.objs
index a028dcd..00ac4ad 100644
--- a/target-ppc/Makefile.objs
+++ b/target-ppc/Makefile.objs
@@ -1,3 +1,4 @@
+obj-y += cpu-models.o
obj-y += translate.o
obj-$(CONFIG_SOFTMMU) += machine.o
obj-$(CONFIG_KVM) += kvm.o kvm_ppc.o
diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
new file mode 100644
index 0000000..f0be585
--- /dev/null
+++ b/target-ppc/cpu-models.c
@@ -0,0 +1,1225 @@
+/*
+ * PowerPC CPU initialization for qemu.
+ *
+ * Copyright (c) 2003-2007 Jocelyn Mayer
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* A lot of PowerPC definition have been included here.
+ * Most of them are not usable for now but have been kept
+ * inside "#if defined(TODO) ... #endif" statements to make tests easier.
+ */
+
+#include "cpu.h"
+#include "cpu-models.h"
+
+#if defined(CONFIG_USER_ONLY)
+#define TODO_USER_ONLY 1
+#endif
+
+/***************************************************************************/
+/* PowerPC CPU definitions */
+#define POWERPC_DEF_PREFIX(pvr, svr, type) \
+ glue(glue(glue(glue(pvr, _), svr), _), type)
+#define POWERPC_DEF_SVR(_name, _desc, _pvr, _svr, _type) \
+ static void \
+ glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init) \
+ (ObjectClass *oc, void *data) \
+ { \
+ DeviceClass *dc = DEVICE_CLASS(oc); \
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); \
+ \
+ pcc->pvr = _pvr; \
+ pcc->svr = _svr; \
+ dc->desc = _desc; \
+ } \
+ \
+ static const TypeInfo \
+ glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info) = { \
+ .name = _name "-" TYPE_POWERPC_CPU, \
+ .parent = stringify(_type) "-family-" TYPE_POWERPC_CPU, \
+ .class_init = \
+ glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init), \
+ }; \
+ \
+ static void \
+ glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types)(void) \
+ { \
+ type_register_static( \
+ &glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info)); \
+ } \
+ \
+ type_init( \
+ glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types))
+
+#define POWERPC_DEF(_name, _pvr, _type, _desc) \
+ POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type)
+
+ /* Embedded PowerPC */
+ /* PowerPC 401 family */
+ POWERPC_DEF("401", CPU_POWERPC_401, 401,
+ "Generic PowerPC 401")
+ /* PowerPC 401 cores */
+ POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401,
+ "PowerPC 401A1")
+ POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2,
+ "PowerPC 401B2")
+#if defined(TODO)
+ POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3,
+ "PowerPC 401B3")
+#endif
+ POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2,
+ "PowerPC 401C2")
+ POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2,
+ "PowerPC 401D2")
+ POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2,
+ "PowerPC 401E2")
+ POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2,
+ "PowerPC 401F2")
+ /* XXX: to be checked */
+ POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2,
+ "PowerPC 401G2")
+ /* PowerPC 401 microcontrolers */
+#if defined(TODO)
+ POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401,
+ "PowerPC 401GF")
+#endif
+ POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480,
+ "IOP480 (401 microcontroller)")
+ POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401,
+ "IBM Processor for Network Resources")
+#if defined(TODO)
+ POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401,
+ NULL)
+#endif
+ /* PowerPC 403 family */
+ /* PowerPC 403 microcontrolers */
+ POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403,
+ "PowerPC 403 GA")
+ POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403,
+ "PowerPC 403 GB")
+ POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403,
+ "PowerPC 403 GC")
+ POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX,
+ "PowerPC 403 GCX")
+#if defined(TODO)
+ POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403,
+ "PowerPC 403 GP")
+#endif
+ /* PowerPC 405 family */
+ /* PowerPC 405 cores */
+#if defined(TODO)
+ POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405,
+ "PowerPC 405 A3")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405,
+ "PowerPC 405 A4")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405,
+ "PowerPC 405 B3")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405,
+ "PowerPC 405 B4")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405,
+ "PowerPC 405 C3")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405,
+ "PowerPC 405 C4")
+#endif
+ POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405,
+ "PowerPC 405 D2")
+#if defined(TODO)
+ POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405,
+ "PowerPC 405 D3")
+#endif
+ POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405,
+ "PowerPC 405 D4")
+#if defined(TODO)
+ POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405,
+ "PowerPC 405 D5")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405,
+ "PowerPC 405 E4")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405,
+ "PowerPC 405 F4")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405,
+ "PowerPC 405 F5")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405,
+ "PowerPC 405 F6")
+#endif
+ /* PowerPC 405 microcontrolers */
+ POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405,
+ "PowerPC 405 CRa")
+ POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405,
+ "PowerPC 405 CRb")
+ POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405,
+ "PowerPC 405 CRc")
+ POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405,
+ "PowerPC 405 EP")
+#if defined(TODO)
+ POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405,
+ "PowerPC 405 EXr")
+#endif
+ POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405,
+ "PowerPC 405 EZ")
+#if defined(TODO)
+ POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405,
+ "PowerPC 405 FX")
+#endif
+ POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405,
+ "PowerPC 405 GPa")
+ POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405,
+ "PowerPC 405 GPb")
+ POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405,
+ "PowerPC 405 GPc")
+ POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405,
+ "PowerPC 405 GPd")
+ POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405,
+ "PowerPC 405 GPR")
+#if defined(TODO)
+ POWERPC_DEF("405H", CPU_POWERPC_405H, 405,
+ "PowerPC 405 H")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("405L", CPU_POWERPC_405L, 405,
+ "PowerPC 405 L")
+#endif
+ POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405,
+ "PowerPC 405 LP")
+#if defined(TODO)
+ POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405,
+ "PowerPC 405 PM")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405,
+ "PowerPC 405 PS")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("405S", CPU_POWERPC_405S, 405,
+ "PowerPC 405 S")
+#endif
+ POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405,
+ "Npe405 H")
+ POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405,
+ "Npe405 H2")
+ POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405,
+ "Npe405 L")
+ POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405,
+ "Npe4GS3")
+#if defined(TODO)
+ POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405,
+ NULL)
+#endif
+#if defined(TODO)
+ POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405,
+ NULL)
+#endif
+#if defined(TODO)
+ POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405,
+ "PowerPC LC77700 (Sanyo)")
+#endif
+ /* PowerPC 401/403/405 based set-top-box microcontrolers */
+#if defined(TODO)
+ POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2,
+ "STB010000")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2,
+ "STB01010")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3,
+ "STB0210")
+#endif
+ POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405,
+ "STB03xx")
+#if defined(TODO)
+ POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405,
+ "STB043x")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405,
+ "STB045x")
+#endif
+ POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405,
+ "STB04xx")
+ POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405,
+ "STB25xx")
+#if defined(TODO)
+ POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405,
+ "STB130")
+#endif
+ /* Xilinx PowerPC 405 cores */
+ POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405,
+ NULL)
+ POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405,
+ NULL)
+#if defined(TODO)
+ POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405,
+ "Zarlink ZL10310")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405,
+ "Zarlink ZL10311")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405,
+ "Zarlink ZL10320")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405,
+ "Zarlink ZL10321")
+#endif
+ /* PowerPC 440 family */
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("440", CPU_POWERPC_440, 440GP,
+ "Generic PowerPC 440")
+#endif
+ /* PowerPC 440 cores */
+#if defined(TODO)
+ POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4,
+ "PowerPC 440 A4")
+#endif
+ POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5,
+ "PowerPC 440 Xilinx 5")
+#if defined(TODO)
+ POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5,
+ "PowerPC 440 A5")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4,
+ "PowerPC 440 B4")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4,
+ "PowerPC 440 G4")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5,
+ "PowerPC 440 F5")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5,
+ "PowerPC 440 G5")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4,
+ "PowerPC 440H4")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5,
+ "PowerPC 440H6")
+#endif
+ /* PowerPC 440 microcontrolers */
+ POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP,
+ "PowerPC 440 EPa")
+ POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP,
+ "PowerPC 440 EPb")
+ POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP,
+ "PowerPC 440 EPX")
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP,
+ "PowerPC 440 GPb")
+#endif
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP,
+ "PowerPC 440 GPc")
+#endif
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5,
+ "PowerPC 440 GRa")
+#endif
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5,
+ "PowerPC 440 GRX")
+#endif
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP,
+ "PowerPC 440 GXa")
+#endif
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP,
+ "PowerPC 440 GXb")
+#endif
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP,
+ "PowerPC 440 GXc")
+#endif
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP,
+ "PowerPC 440 GXf")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("440S", CPU_POWERPC_440S, 440,
+ "PowerPC 440 S")
+#endif
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP,
+ "PowerPC 440 SP")
+#endif
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP,
+ "PowerPC 440 SP2")
+#endif
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP,
+ "PowerPC 440 SPE")
+#endif
+ /* PowerPC 460 family */
+#if defined(TODO)
+ POWERPC_DEF("464", CPU_POWERPC_464, 460,
+ "Generic PowerPC 464")
+#endif
+ /* PowerPC 464 microcontrolers */
+#if defined(TODO)
+ POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460,
+ "PowerPC 464H90")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F,
+ "PowerPC 464H90F")
+#endif
+ /* Freescale embedded PowerPC cores */
+ /* MPC5xx family (aka RCPU) */
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx,
+ "Generic MPC5xx core")
+#endif
+ /* MPC8xx family (aka PowerQUICC) */
+#if defined(TODO_USER_ONLY)
+ POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx,
+ "Generic MPC8xx core")
+#endif
+ /* MPC82xx family (aka PowerQUICC-II) */
+ POWERPC_DEF("G2", CPU_POWERPC_G2, G2,
+ "PowerPC G2 core")
+ POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2,
+ "PowerPC G2 H4 core")
+ POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2,
+ "PowerPC G2 GP core")
+ POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2,
+ "PowerPC G2 LS core")
+ POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2,
+ "PowerPC G2 HiP3 core")
+ POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2,
+ "PowerPC G2 HiP4 core")
+ POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E,
+ "PowerPC MPC603 core")
+ POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE,
+ "PowerPC G2le core (same as G2 plus little-endian mode support)")
+ POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE,
+ "PowerPC G2LE GP core")
+ POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE,
+ "PowerPC G2LE LS core")
+ POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE,
+ "PowerPC G2LE GP1 core")
+ POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2LE,
+ "PowerPC G2LE GP3 core")
+ /* PowerPC G2 microcontrollers */
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5121", "MPC5121",
+ CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE)
+#endif
+ POWERPC_DEF_SVR("MPC5200_v10", "MPC5200 v1.0",
+ CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE)
+ POWERPC_DEF_SVR("MPC5200_v11", "MPC5200 v1.1",
+ CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE)
+ POWERPC_DEF_SVR("MPC5200_v12", "MPC5200 v1.2",
+ CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE)
+ POWERPC_DEF_SVR("MPC5200B_v20", "MPC5200B v2.0",
+ CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
+ POWERPC_DEF_SVR("MPC5200B_v21", "MPC5200B v2.1",
+ CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
+ /* e200 family */
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC55xx", "Generic MPC55xx core",
+ CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200,
+ "PowerPC e200z0 core")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200,
+ "PowerPC e200z1 core")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200,
+ "PowerPC e200z3 core")
+#endif
+ POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200,
+ "PowerPC e200z5 core")
+ POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200,
+ "PowerPC e200z6 core")
+ /* PowerPC e200 microcontrollers */
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5514E", "MPC5514E",
+ CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5514E_v0", "MPC5514E v0",
+ CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5514E_v1", "MPC5514E v1",
+ CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5514G", "MPC5514G",
+ CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5514G_v0", "MPC5514G v0",
+ CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5514G_v1", "MPC5514G v1",
+ CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5515S", "MPC5515S",
+ CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5516E", "MPC5516E",
+ CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5516E_v0", "MPC5516E v0",
+ CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5516E_v1", "MPC5516E v1",
+ CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5516G", "MPC5516G",
+ CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5516G_v0", "MPC5516G v0",
+ CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5516G_v1", "MPC5516G v1",
+ CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5516S", "MPC5516S",
+ CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5533", "MPC5533",
+ CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5534", "MPC5534",
+ CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5553", "MPC5553",
+ CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5554", "MPC5554",
+ CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5561", "MPC5561",
+ CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5565", "MPC5565",
+ CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5566", "MPC5566",
+ CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC5567", "MPC5567",
+ CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200)
+#endif
+ /* e300 family */
+ POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300,
+ "PowerPC e300c1 core")
+ POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300,
+ "PowerPC e300c2 core")
+ POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300,
+ "PowerPC e300c3 core")
+ POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300,
+ "PowerPC e300c4 core")
+ /* PowerPC e300 microcontrollers */
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC8313", "MPC8313",
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC8313E", "MPC8313E",
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC8314", "MPC8314",
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC8314E", "MPC8314E",
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC8315", "MPC8315",
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC8315E", "MPC8315E",
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC8321", "MPC8321",
+ CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC8321E", "MPC8321E",
+ CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC8323", "MPC8323",
+ CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC8323E", "MPC8323E",
+ CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300)
+#endif
+ POWERPC_DEF_SVR("MPC8343", "MPC8343",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300)
+ POWERPC_DEF_SVR("MPC8343A", "MPC8343A",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300)
+ POWERPC_DEF_SVR("MPC8343E", "MPC8343E",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300)
+ POWERPC_DEF_SVR("MPC8343EA", "MPC8343EA",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300)
+ POWERPC_DEF_SVR("MPC8347T", "MPC8347T",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300)
+ POWERPC_DEF_SVR("MPC8347P", "MPC8347P",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300)
+ POWERPC_DEF_SVR("MPC8347AT", "MPC8347AT",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300)
+ POWERPC_DEF_SVR("MPC8347AP", "MPC8347AP",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300)
+ POWERPC_DEF_SVR("MPC8347ET", "MPC8347ET",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300)
+ POWERPC_DEF_SVR("MPC8347EP", "MPC8343EP",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300)
+ POWERPC_DEF_SVR("MPC8347EAT", "MPC8347EAT",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300)
+ POWERPC_DEF_SVR("MPC8347EAP", "MPC8343EAP",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300)
+ POWERPC_DEF_SVR("MPC8349", "MPC8349",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300)
+ POWERPC_DEF_SVR("MPC8349A", "MPC8349A",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300)
+ POWERPC_DEF_SVR("MPC8349E", "MPC8349E",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300)
+ POWERPC_DEF_SVR("MPC8349EA", "MPC8349EA",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300)
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC8358E", "MPC8358E",
+ CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300)
+#endif
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC8360E", "MPC8360E",
+ CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300)
+#endif
+ POWERPC_DEF_SVR("MPC8377", "MPC8377",
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300)
+ POWERPC_DEF_SVR("MPC8377E", "MPC8377E",
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300)
+ POWERPC_DEF_SVR("MPC8378", "MPC8378",
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300)
+ POWERPC_DEF_SVR("MPC8378E", "MPC8378E",
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300)
+ POWERPC_DEF_SVR("MPC8379", "MPC8379",
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300)
+ POWERPC_DEF_SVR("MPC8379E", "MPC8379E",
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300)
+ /* e500 family */
+ POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1,
+ "PowerPC e500 v1.0 core")
+ POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1,
+ "PowerPC e500 v2.0 core")
+ POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2,
+ "PowerPC e500v2 v1.0 core")
+ POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2,
+ "PowerPC e500v2 v2.0 core")
+ POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2,
+ "PowerPC e500v2 v2.1 core")
+ POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2,
+ "PowerPC e500v2 v2.2 core")
+ POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2,
+ "PowerPC e500v2 v3.0 core")
+ POWERPC_DEF_SVR("e500mc", "e500mc",
+ CPU_POWERPC_e500mc, POWERPC_SVR_E500, e500mc)
+#ifdef TARGET_PPC64
+ POWERPC_DEF_SVR("e5500", "e5500",
+ CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500)
+#endif
+ /* PowerPC e500 microcontrollers */
+ POWERPC_DEF_SVR("MPC8533_v10", "MPC8533 v1.0",
+ CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2)
+ POWERPC_DEF_SVR("MPC8533_v11", "MPC8533 v1.1",
+ CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2)
+ POWERPC_DEF_SVR("MPC8533E_v10", "MPC8533E v1.0",
+ CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2)
+ POWERPC_DEF_SVR("MPC8533E_v11", "MPC8533E v1.1",
+ CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2)
+ POWERPC_DEF_SVR("MPC8540_v10", "MPC8540 v1.0",
+ CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1)
+ POWERPC_DEF_SVR("MPC8540_v20", "MPC8540 v2.0",
+ CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1)
+ POWERPC_DEF_SVR("MPC8540_v21", "MPC8540 v2.1",
+ CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1)
+ POWERPC_DEF_SVR("MPC8541_v10", "MPC8541 v1.0",
+ CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1)
+ POWERPC_DEF_SVR("MPC8541_v11", "MPC8541 v1.1",
+ CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1)
+ POWERPC_DEF_SVR("MPC8541E_v10", "MPC8541E v1.0",
+ CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1)
+ POWERPC_DEF_SVR("MPC8541E_v11", "MPC8541E v1.1",
+ CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1)
+ POWERPC_DEF_SVR("MPC8543_v10", "MPC8543 v1.0",
+ CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2)
+ POWERPC_DEF_SVR("MPC8543_v11", "MPC8543 v1.1",
+ CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2)
+ POWERPC_DEF_SVR("MPC8543_v20", "MPC8543 v2.0",
+ CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2)
+ POWERPC_DEF_SVR("MPC8543_v21", "MPC8543 v2.1",
+ CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2)
+ POWERPC_DEF_SVR("MPC8543E_v10", "MPC8543E v1.0",
+ CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2)
+ POWERPC_DEF_SVR("MPC8543E_v11", "MPC8543E v1.1",
+ CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2)
+ POWERPC_DEF_SVR("MPC8543E_v20", "MPC8543E v2.0",
+ CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2)
+ POWERPC_DEF_SVR("MPC8543E_v21", "MPC8543E v2.1",
+ CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2)
+ POWERPC_DEF_SVR("MPC8544_v10", "MPC8544 v1.0",
+ CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2)
+ POWERPC_DEF_SVR("MPC8544_v11", "MPC8544 v1.1",
+ CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2)
+ POWERPC_DEF_SVR("MPC8544E_v10", "MPC8544E v1.0",
+ CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2)
+ POWERPC_DEF_SVR("MPC8544E_v11", "MPC8544E v1.1",
+ CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2)
+ POWERPC_DEF_SVR("MPC8545_v20", "MPC8545 v2.0",
+ CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2)
+ POWERPC_DEF_SVR("MPC8545_v21", "MPC8545 v2.1",
+ CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2)
+ POWERPC_DEF_SVR("MPC8545E_v20", "MPC8545E v2.0",
+ CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2)
+ POWERPC_DEF_SVR("MPC8545E_v21", "MPC8545E v2.1",
+ CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2)
+ POWERPC_DEF_SVR("MPC8547E_v20", "MPC8547E v2.0",
+ CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2)
+ POWERPC_DEF_SVR("MPC8547E_v21", "MPC8547E v2.1",
+ CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2)
+ POWERPC_DEF_SVR("MPC8548_v10", "MPC8548 v1.0",
+ CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2)
+ POWERPC_DEF_SVR("MPC8548_v11", "MPC8548 v1.1",
+ CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2)
+ POWERPC_DEF_SVR("MPC8548_v20", "MPC8548 v2.0",
+ CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2)
+ POWERPC_DEF_SVR("MPC8548_v21", "MPC8548 v2.1",
+ CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2)
+ POWERPC_DEF_SVR("MPC8548E_v10", "MPC8548E v1.0",
+ CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2)
+ POWERPC_DEF_SVR("MPC8548E_v11", "MPC8548E v1.1",
+ CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2)
+ POWERPC_DEF_SVR("MPC8548E_v20", "MPC8548E v2.0",
+ CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2)
+ POWERPC_DEF_SVR("MPC8548E_v21", "MPC8548E v2.1",
+ CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2)
+ POWERPC_DEF_SVR("MPC8555_v10", "MPC8555 v1.0",
+ CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2)
+ POWERPC_DEF_SVR("MPC8555_v11", "MPC8555 v1.1",
+ CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2)
+ POWERPC_DEF_SVR("MPC8555E_v10", "MPC8555E v1.0",
+ CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2)
+ POWERPC_DEF_SVR("MPC8555E_v11", "MPC8555E v1.1",
+ CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2)
+ POWERPC_DEF_SVR("MPC8560_v10", "MPC8560 v1.0",
+ CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2)
+ POWERPC_DEF_SVR("MPC8560_v20", "MPC8560 v2.0",
+ CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2)
+ POWERPC_DEF_SVR("MPC8560_v21", "MPC8560 v2.1",
+ CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2)
+ POWERPC_DEF_SVR("MPC8567", "MPC8567",
+ CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2)
+ POWERPC_DEF_SVR("MPC8567E", "MPC8567E",
+ CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2)
+ POWERPC_DEF_SVR("MPC8568", "MPC8568",
+ CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2)
+ POWERPC_DEF_SVR("MPC8568E", "MPC8568E",
+ CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2)
+ POWERPC_DEF_SVR("MPC8572", "MPC8572",
+ CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2)
+ POWERPC_DEF_SVR("MPC8572E", "MPC8572E",
+ CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2)
+ /* e600 family */
+ POWERPC_DEF("e600", CPU_POWERPC_e600, 7400,
+ "PowerPC e600 core")
+ /* PowerPC e600 microcontrollers */
+#if defined(TODO)
+ POWERPC_DEF_SVR("MPC8610", "MPC8610",
+ CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400)
+#endif
+ POWERPC_DEF_SVR("MPC8641", "MPC8641",
+ CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400)
+ POWERPC_DEF_SVR("MPC8641D", "MPC8641D",
+ CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400)
+ /* 32 bits "classic" PowerPC */
+ /* PowerPC 6xx family */
+ POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601,
+ "PowerPC 601v0")
+ POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601,
+ "PowerPC 601v1")
+ POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v,
+ "PowerPC 601v2")
+ POWERPC_DEF("602", CPU_POWERPC_602, 602,
+ "PowerPC 602")
+ POWERPC_DEF("603", CPU_POWERPC_603, 603,
+ "PowerPC 603")
+ POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E,
+ "PowerPC 603e v1.1")
+ POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E,
+ "PowerPC 603e v1.2")
+ POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E,
+ "PowerPC 603e v1.3")
+ POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E,
+ "PowerPC 603e v1.4")
+ POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E,
+ "PowerPC 603e v2.2")
+ POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E,
+ "PowerPC 603e v3")
+ POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E,
+ "PowerPC 603e v4")
+ POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E,
+ "PowerPC 603e v4.1")
+ POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E,
+ "PowerPC 603e (aka PID7)")
+ POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E,
+ "PowerPC 603e7t")
+ POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E,
+ "PowerPC 603e7v")
+ POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E,
+ "PowerPC 603e7v1")
+ POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E,
+ "PowerPC 603e7v2")
+ POWERPC_DEF("603p", CPU_POWERPC_603P, 603E,
+ "PowerPC 603p (aka PID7v)")
+ POWERPC_DEF("604", CPU_POWERPC_604, 604,
+ "PowerPC 604")
+ POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E,
+ "PowerPC 604e v1.0")
+ POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E,
+ "PowerPC 604e v2.2")
+ POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E,
+ "PowerPC 604e v2.4")
+ POWERPC_DEF("604r", CPU_POWERPC_604R, 604E,
+ "PowerPC 604r (aka PIDA)")
+#if defined(TODO)
+ POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E,
+ "PowerPC 604ev")
+#endif
+ /* PowerPC 7xx family */
+ POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740,
+ "PowerPC 740 v1.0 (G3)")
+ POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750,
+ "PowerPC 750 v1.0 (G3)")
+ POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740,
+ "PowerPC 740 v2.0 (G3)")
+ POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750,
+ "PowerPC 750 v2.0 (G3)")
+ POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740,
+ "PowerPC 740 v2.1 (G3)")
+ POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750,
+ "PowerPC 750 v2.1 (G3)")
+ POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740,
+ "PowerPC 740 v2.2 (G3)")
+ POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750,
+ "PowerPC 750 v2.2 (G3)")
+ POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740,
+ "PowerPC 740 v3.0 (G3)")
+ POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750,
+ "PowerPC 750 v3.0 (G3)")
+ POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740,
+ "PowerPC 740 v3.1 (G3)")
+ POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750,
+ "PowerPC 750 v3.1 (G3)")
+ POWERPC_DEF("740e", CPU_POWERPC_740E, 740,
+ "PowerPC 740E (G3)")
+ POWERPC_DEF("750e", CPU_POWERPC_750E, 750,
+ "PowerPC 750E (G3)")
+ POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740,
+ "PowerPC 740P (G3)")
+ POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750,
+ "PowerPC 750P (G3)")
+ POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl,
+ "PowerPC 750CL v1.0")
+ POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl,
+ "PowerPC 750CL v2.0")
+ POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx,
+ "PowerPC 750CX v1.0 (G3 embedded)")
+ POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx,
+ "PowerPC 750CX v2.1 (G3 embedded)")
+ POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx,
+ "PowerPC 750CX v2.1 (G3 embedded)")
+ POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx,
+ "PowerPC 750CX v2.2 (G3 embedded)")
+ POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx,
+ "PowerPC 750CXe v2.1 (G3 embedded)")
+ POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx,
+ "PowerPC 750CXe v2.2 (G3 embedded)")
+ POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx,
+ "PowerPC 750CXe v2.3 (G3 embedded)")
+ POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx,
+ "PowerPC 750CXe v2.4 (G3 embedded)")
+ POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx,
+ "PowerPC 750CXe v2.4b (G3 embedded)")
+ POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx,
+ "PowerPC 750CXe v3.0 (G3 embedded)")
+ POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx,
+ "PowerPC 750CXe v3.1 (G3 embedded)")
+ POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx,
+ "PowerPC 750CXe v3.1b (G3 embedded)")
+ POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx,
+ "PowerPC 750CXr (G3 embedded)")
+ POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx,
+ "PowerPC 750FL (G3 embedded)")
+ POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx,
+ "PowerPC 750FX v1.0 (G3 embedded)")
+ POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx,
+ "PowerPC 750FX v2.0 (G3 embedded)")
+ POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx,
+ "PowerPC 750FX v2.1 (G3 embedded)")
+ POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx,
+ "PowerPC 750FX v2.2 (G3 embedded)")
+ POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx,
+ "PowerPC 750FX v2.3 (G3 embedded)")
+ POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx,
+ "PowerPC 750GL (G3 embedded)")
+ POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx,
+ "PowerPC 750GX v1.0 (G3 embedded)")
+ POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx,
+ "PowerPC 750GX v1.1 (G3 embedded)")
+ POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx,
+ "PowerPC 750GX v1.2 (G3 embedded)")
+ POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750,
+ "PowerPC 750L v2.0 (G3 embedded)")
+ POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750,
+ "PowerPC 750L v2.1 (G3 embedded)")
+ POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750,
+ "PowerPC 750L v2.2 (G3 embedded)")
+ POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750,
+ "PowerPC 750L v3.0 (G3 embedded)")
+ POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750,
+ "PowerPC 750L v3.2 (G3 embedded)")
+ POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745,
+ "PowerPC 745 v1.0")
+ POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755,
+ "PowerPC 755 v1.0")
+ POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745,
+ "PowerPC 745 v1.1")
+ POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755,
+ "PowerPC 755 v1.1")
+ POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745,
+ "PowerPC 745 v2.0")
+ POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755,
+ "PowerPC 755 v2.0")
+ POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745,
+ "PowerPC 745 v2.1")
+ POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755,
+ "PowerPC 755 v2.1")
+ POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745,
+ "PowerPC 745 v2.2")
+ POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755,
+ "PowerPC 755 v2.2")
+ POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745,
+ "PowerPC 745 v2.3")
+ POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755,
+ "PowerPC 755 v2.3")
+ POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745,
+ "PowerPC 745 v2.4")
+ POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755,
+ "PowerPC 755 v2.4")
+ POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745,
+ "PowerPC 745 v2.5")
+ POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755,
+ "PowerPC 755 v2.5")
+ POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745,
+ "PowerPC 745 v2.6")
+ POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755,
+ "PowerPC 755 v2.6")
+ POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745,
+ "PowerPC 745 v2.7")
+ POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755,
+ "PowerPC 755 v2.7")
+ POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745,
+ "PowerPC 745 v2.8")
+ POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755,
+ "PowerPC 755 v2.8")
+#if defined(TODO)
+ POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745,
+ "PowerPC 745P (G3)")
+ POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755,
+ "PowerPC 755P (G3)")
+#endif
+ /* PowerPC 74xx family */
+ POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400,
+ "PowerPC 7400 v1.0 (G4)")
+ POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400,
+ "PowerPC 7400 v1.1 (G4)")
+ POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400,
+ "PowerPC 7400 v2.0 (G4)")
+ POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400,
+ "PowerPC 7400 v2.1 (G4)")
+ POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400,
+ "PowerPC 7400 v2.2 (G4)")
+ POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400,
+ "PowerPC 7400 v2.6 (G4)")
+ POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400,
+ "PowerPC 7400 v2.7 (G4)")
+ POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400,
+ "PowerPC 7400 v2.8 (G4)")
+ POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400,
+ "PowerPC 7400 v2.9 (G4)")
+ POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410,
+ "PowerPC 7410 v1.0 (G4)")
+ POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410,
+ "PowerPC 7410 v1.1 (G4)")
+ POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410,
+ "PowerPC 7410 v1.2 (G4)")
+ POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410,
+ "PowerPC 7410 v1.3 (G4)")
+ POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410,
+ "PowerPC 7410 v1.4 (G4)")
+ POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400,
+ "PowerPC 7448 v1.0 (G4)")
+ POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400,
+ "PowerPC 7448 v1.1 (G4)")
+ POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400,
+ "PowerPC 7448 v2.0 (G4)")
+ POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400,
+ "PowerPC 7448 v2.1 (G4)")
+ POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450,
+ "PowerPC 7450 v1.0 (G4)")
+ POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450,
+ "PowerPC 7450 v1.1 (G4)")
+ POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450,
+ "PowerPC 7450 v1.2 (G4)")
+ POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450,
+ "PowerPC 7450 v2.0 (G4)")
+ POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450,
+ "PowerPC 7450 v2.1 (G4)")
+ POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440,
+ "PowerPC 7441 v2.1 (G4)")
+ POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440,
+ "PowerPC 7441 v2.3 (G4)")
+ POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450,
+ "PowerPC 7451 v2.3 (G4)")
+ POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440,
+ "PowerPC 7441 v2.10 (G4)")
+ POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450,
+ "PowerPC 7451 v2.10 (G4)")
+ POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445,
+ "PowerPC 7445 v1.0 (G4)")
+ POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455,
+ "PowerPC 7455 v1.0 (G4)")
+ POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445,
+ "PowerPC 7445 v2.1 (G4)")
+ POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455,
+ "PowerPC 7455 v2.1 (G4)")
+ POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445,
+ "PowerPC 7445 v3.2 (G4)")
+ POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455,
+ "PowerPC 7455 v3.2 (G4)")
+ POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445,
+ "PowerPC 7445 v3.3 (G4)")
+ POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455,
+ "PowerPC 7455 v3.3 (G4)")
+ POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445,
+ "PowerPC 7445 v3.4 (G4)")
+ POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455,
+ "PowerPC 7455 v3.4 (G4)")
+ POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445,
+ "PowerPC 7447 v1.0 (G4)")
+ POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455,
+ "PowerPC 7457 v1.0 (G4)")
+ POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445,
+ "PowerPC 7447 v1.1 (G4)")
+ POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455,
+ "PowerPC 7457 v1.1 (G4)")
+ POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455,
+ "PowerPC 7457 v1.2 (G4)")
+ POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445,
+ "PowerPC 7447A v1.0 (G4)")
+ POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455,
+ "PowerPC 7457A v1.0 (G4)")
+ POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445,
+ "PowerPC 7447A v1.1 (G4)")
+ POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455,
+ "PowerPC 7457A v1.1 (G4)")
+ POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445,
+ "PowerPC 7447A v1.2 (G4)")
+ POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455,
+ "PowerPC 7457A v1.2 (G4)")
+ /* 64 bits PowerPC */
+#if defined (TARGET_PPC64)
+ POWERPC_DEF("620", CPU_POWERPC_620, 620,
+ "PowerPC 620")
+#if defined(TODO)
+ POWERPC_DEF("630", CPU_POWERPC_630, 630,
+ "PowerPC 630 (POWER3)")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("631", CPU_POWERPC_631, 631,
+ "PowerPC 631 (Power 3+)")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4,
+ "POWER4")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P,
+ "POWER4p")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5,
+ "POWER5")
+ POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5,
+ "POWER5GR")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P,
+ "POWER5+")
+ POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P,
+ "POWER5GS")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6,
+ "POWER6")
+ POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5,
+ "POWER6 running in POWER5 mode")
+ POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6,
+ "POWER6A")
+#endif
+ POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7,
+ "POWER7 v2.0")
+ POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7,
+ "POWER7 v2.1")
+ POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7,
+ "POWER7 v2.3")
+ POWERPC_DEF("970", CPU_POWERPC_970, 970,
+ "PowerPC 970")
+ POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX,
+ "PowerPC 970FX v1.0 (G5)")
+ POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX,
+ "PowerPC 970FX v2.0 (G5)")
+ POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX,
+ "PowerPC 970FX v2.1 (G5)")
+ POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX,
+ "PowerPC 970FX v3.0 (G5)")
+ POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX,
+ "PowerPC 970FX v3.1 (G5)")
+ POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX,
+ "PowerPC 970GX (G5)")
+ POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP,
+ "PowerPC 970MP v1.0")
+ POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP,
+ "PowerPC 970MP v1.1")
+#if defined(TODO)
+ POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970,
+ "PowerPC Cell")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970,
+ "PowerPC Cell v1.0")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970,
+ "PowerPC Cell v2.0")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970,
+ "PowerPC Cell v3.0")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970,
+ "PowerPC Cell v3.1")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970,
+ "PowerPC Cell v3.2")
+#endif
+#if defined(TODO)
+ /* This one seems to support the whole POWER2 instruction set
+ * and the PowerPC 64 one.
+ */
+ /* What about A10 & A30 ? */
+ POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64,
+ "RS64 (Apache/A35)")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64,
+ "RS64-II (NorthStar/A50)")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64,
+ "RS64-III (Pulsar)")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64,
+ "RS64-IV (IceStar/IStar/SStar)")
+#endif
+#endif /* defined (TARGET_PPC64) */
+ /* POWER */
+#if defined(TODO)
+ POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER,
+ "Original POWER")
+#endif
+#if defined(TODO)
+ POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER,
+ "POWER2")
+#endif
+ /* PA semi cores */
+#if defined(TODO)
+ POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T,
+ "PA PA6T")
+#endif
+
diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
new file mode 100644
index 0000000..edff0f4
--- /dev/null
+++ b/target-ppc/cpu-models.h
@@ -0,0 +1,727 @@
+/*
+ * PowerPC CPU initialization for qemu.
+ *
+ * Copyright (c) 2003-2007 Jocelyn Mayer
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef TARGET_PPC_CPU_MODELS_H
+#define TARGET_PPC_CPU_MODELS_H
+
+/*****************************************************************************/
+/* PVR definitions for most known PowerPC */
+enum {
+ /* PowerPC 401 family */
+ /* Generic PowerPC 401 */
+#define CPU_POWERPC_401 CPU_POWERPC_401G2
+ /* PowerPC 401 cores */
+ CPU_POWERPC_401A1 = 0x00210000,
+ CPU_POWERPC_401B2 = 0x00220000,
+#if 0
+ CPU_POWERPC_401B3 = xxx,
+#endif
+ CPU_POWERPC_401C2 = 0x00230000,
+ CPU_POWERPC_401D2 = 0x00240000,
+ CPU_POWERPC_401E2 = 0x00250000,
+ CPU_POWERPC_401F2 = 0x00260000,
+ CPU_POWERPC_401G2 = 0x00270000,
+ /* PowerPC 401 microcontrolers */
+#if 0
+ CPU_POWERPC_401GF = xxx,
+#endif
+#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
+ /* IBM Processor for Network Resources */
+ CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
+#if 0
+ CPU_POWERPC_XIPCHIP = xxx,
+#endif
+ /* PowerPC 403 family */
+ /* PowerPC 403 microcontrollers */
+ CPU_POWERPC_403GA = 0x00200011,
+ CPU_POWERPC_403GB = 0x00200100,
+ CPU_POWERPC_403GC = 0x00200200,
+ CPU_POWERPC_403GCX = 0x00201400,
+#if 0
+ CPU_POWERPC_403GP = xxx,
+#endif
+ /* PowerPC 405 family */
+ /* PowerPC 405 cores */
+#if 0
+ CPU_POWERPC_405A3 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_405A4 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_405B3 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_405B4 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_405C3 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_405C4 = xxx,
+#endif
+ CPU_POWERPC_405D2 = 0x20010000,
+#if 0
+ CPU_POWERPC_405D3 = xxx,
+#endif
+ CPU_POWERPC_405D4 = 0x41810000,
+#if 0
+ CPU_POWERPC_405D5 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_405E4 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_405F4 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_405F5 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_405F6 = xxx,
+#endif
+ /* PowerPC 405 microcontrolers */
+ /* XXX: missing 0x200108a0 */
+ CPU_POWERPC_405CRa = 0x40110041,
+ CPU_POWERPC_405CRb = 0x401100C5,
+ CPU_POWERPC_405CRc = 0x40110145,
+ CPU_POWERPC_405EP = 0x51210950,
+#if 0
+ CPU_POWERPC_405EXr = xxx,
+#endif
+ CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
+#if 0
+ CPU_POWERPC_405FX = xxx,
+#endif
+ CPU_POWERPC_405GPa = 0x40110000,
+ CPU_POWERPC_405GPb = 0x40110040,
+ CPU_POWERPC_405GPc = 0x40110082,
+ CPU_POWERPC_405GPd = 0x401100C4,
+ CPU_POWERPC_405GPR = 0x50910951,
+#if 0
+ CPU_POWERPC_405H = xxx,
+#endif
+#if 0
+ CPU_POWERPC_405L = xxx,
+#endif
+ CPU_POWERPC_405LP = 0x41F10000,
+#if 0
+ CPU_POWERPC_405PM = xxx,
+#endif
+#if 0
+ CPU_POWERPC_405PS = xxx,
+#endif
+#if 0
+ CPU_POWERPC_405S = xxx,
+#endif
+ /* IBM network processors */
+ CPU_POWERPC_NPE405H = 0x414100C0,
+ CPU_POWERPC_NPE405H2 = 0x41410140,
+ CPU_POWERPC_NPE405L = 0x416100C0,
+ CPU_POWERPC_NPE4GS3 = 0x40B10000,
+#if 0
+ CPU_POWERPC_NPCxx1 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_NPR161 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_LC77700 = xxx,
+#endif
+ /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
+#if 0
+ CPU_POWERPC_STB01000 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_STB01010 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_STB0210 = xxx, /* 401B3 */
+#endif
+ CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
+#if 0
+ CPU_POWERPC_STB043 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_STB045 = xxx,
+#endif
+ CPU_POWERPC_STB04 = 0x41810000,
+ CPU_POWERPC_STB25 = 0x51510950,
+#if 0
+ CPU_POWERPC_STB130 = xxx,
+#endif
+ /* Xilinx cores */
+ CPU_POWERPC_X2VP4 = 0x20010820,
+ CPU_POWERPC_X2VP20 = 0x20010860,
+#if 0
+ CPU_POWERPC_ZL10310 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_ZL10311 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_ZL10320 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_ZL10321 = xxx,
+#endif
+ /* PowerPC 440 family */
+ /* Generic PowerPC 440 */
+#define CPU_POWERPC_440 CPU_POWERPC_440GXf
+ /* PowerPC 440 cores */
+#if 0
+ CPU_POWERPC_440A4 = xxx,
+#endif
+ CPU_POWERPC_440_XILINX = 0x7ff21910,
+#if 0
+ CPU_POWERPC_440A5 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_440B4 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_440F5 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_440G5 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_440H4 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_440H6 = xxx,
+#endif
+ /* PowerPC 440 microcontrolers */
+ CPU_POWERPC_440EPa = 0x42221850,
+ CPU_POWERPC_440EPb = 0x422218D3,
+ CPU_POWERPC_440GPb = 0x40120440,
+ CPU_POWERPC_440GPc = 0x40120481,
+#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
+ CPU_POWERPC_440GRX = 0x200008D0,
+#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
+ CPU_POWERPC_440GXa = 0x51B21850,
+ CPU_POWERPC_440GXb = 0x51B21851,
+ CPU_POWERPC_440GXc = 0x51B21892,
+ CPU_POWERPC_440GXf = 0x51B21894,
+#if 0
+ CPU_POWERPC_440S = xxx,
+#endif
+ CPU_POWERPC_440SP = 0x53221850,
+ CPU_POWERPC_440SP2 = 0x53221891,
+ CPU_POWERPC_440SPE = 0x53421890,
+ /* PowerPC 460 family */
+#if 0
+ /* Generic PowerPC 464 */
+#define CPU_POWERPC_464 CPU_POWERPC_464H90
+#endif
+ /* PowerPC 464 microcontrolers */
+#if 0
+ CPU_POWERPC_464H90 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_464H90FP = xxx,
+#endif
+ /* Freescale embedded PowerPC cores */
+ /* PowerPC MPC 5xx cores (aka RCPU) */
+ CPU_POWERPC_MPC5xx = 0x00020020,
+ /* PowerPC MPC 8xx cores (aka PowerQUICC) */
+ CPU_POWERPC_MPC8xx = 0x00500000,
+ /* G2 cores (aka PowerQUICC-II) */
+ CPU_POWERPC_G2 = 0x00810011,
+ CPU_POWERPC_G2H4 = 0x80811010,
+ CPU_POWERPC_G2gp = 0x80821010,
+ CPU_POWERPC_G2ls = 0x90810010,
+ CPU_POWERPC_MPC603 = 0x00810100,
+ CPU_POWERPC_G2_HIP3 = 0x00810101,
+ CPU_POWERPC_G2_HIP4 = 0x80811014,
+ /* G2_LE core (aka PowerQUICC-II) */
+ CPU_POWERPC_G2LE = 0x80820010,
+ CPU_POWERPC_G2LEgp = 0x80822010,
+ CPU_POWERPC_G2LEls = 0xA0822010,
+ CPU_POWERPC_G2LEgp1 = 0x80822011,
+ CPU_POWERPC_G2LEgp3 = 0x80822013,
+ /* MPC52xx microcontrollers */
+ /* XXX: MPC 5121 ? */
+#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
+#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
+#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
+#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
+#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
+ /* e200 family */
+ /* e200 cores */
+#if 0
+ CPU_POWERPC_e200z0 = xxx,
+#endif
+#if 0
+ CPU_POWERPC_e200z1 = xxx,
+#endif
+#if 0 /* ? */
+ CPU_POWERPC_e200z3 = 0x81120000,
+#endif
+ CPU_POWERPC_e200z5 = 0x81000000,
+ CPU_POWERPC_e200z6 = 0x81120000,
+ /* MPC55xx microcontrollers */
+#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
+#if 0
+#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
+#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
+#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
+#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
+#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
+#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
+#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
+#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
+#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
+#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
+#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
+#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
+#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
+#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
+#endif
+#if 0
+#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
+#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
+#endif
+#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
+#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
+#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
+#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
+#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
+#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
+ /* e300 family */
+ /* e300 cores */
+ CPU_POWERPC_e300c1 = 0x00830010,
+ CPU_POWERPC_e300c2 = 0x00840010,
+ CPU_POWERPC_e300c3 = 0x00850010,
+ CPU_POWERPC_e300c4 = 0x00860010,
+ /* MPC83xx microcontrollers */
+#define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
+#define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
+#define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
+ /* e500 family */
+ /* e500 cores */
+#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
+ CPU_POWERPC_e500v1_v10 = 0x80200010,
+ CPU_POWERPC_e500v1_v20 = 0x80200020,
+ CPU_POWERPC_e500v2_v10 = 0x80210010,
+ CPU_POWERPC_e500v2_v11 = 0x80210011,
+ CPU_POWERPC_e500v2_v20 = 0x80210020,
+ CPU_POWERPC_e500v2_v21 = 0x80210021,
+ CPU_POWERPC_e500v2_v22 = 0x80210022,
+ CPU_POWERPC_e500v2_v30 = 0x80210030,
+ CPU_POWERPC_e500mc = 0x80230020,
+ CPU_POWERPC_e5500 = 0x80240020,
+ /* MPC85xx microcontrollers */
+#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
+#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
+#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
+#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
+#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
+#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
+#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
+#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
+#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
+#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
+#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
+#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
+#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
+#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
+#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
+#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
+#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
+#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
+ /* e600 family */
+ /* e600 cores */
+ CPU_POWERPC_e600 = 0x80040010,
+ /* MPC86xx microcontrollers */
+#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
+#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
+#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
+ /* PowerPC 6xx cores */
+ CPU_POWERPC_601_v0 = 0x00010001,
+ CPU_POWERPC_601_v1 = 0x00010001,
+ CPU_POWERPC_601_v2 = 0x00010002,
+ CPU_POWERPC_602 = 0x00050100,
+ CPU_POWERPC_603 = 0x00030100,
+ CPU_POWERPC_603E_v11 = 0x00060101,
+ CPU_POWERPC_603E_v12 = 0x00060102,
+ CPU_POWERPC_603E_v13 = 0x00060103,
+ CPU_POWERPC_603E_v14 = 0x00060104,
+ CPU_POWERPC_603E_v22 = 0x00060202,
+ CPU_POWERPC_603E_v3 = 0x00060300,
+ CPU_POWERPC_603E_v4 = 0x00060400,
+ CPU_POWERPC_603E_v41 = 0x00060401,
+ CPU_POWERPC_603E7t = 0x00071201,
+ CPU_POWERPC_603E7v = 0x00070100,
+ CPU_POWERPC_603E7v1 = 0x00070101,
+ CPU_POWERPC_603E7v2 = 0x00070201,
+ CPU_POWERPC_603E7 = 0x00070200,
+ CPU_POWERPC_603P = 0x00070000,
+ /* XXX: missing 0x00040303 (604) */
+ CPU_POWERPC_604 = 0x00040103,
+ /* XXX: missing 0x00091203 */
+ /* XXX: missing 0x00092110 */
+ /* XXX: missing 0x00092120 */
+ CPU_POWERPC_604E_v10 = 0x00090100,
+ CPU_POWERPC_604E_v22 = 0x00090202,
+ CPU_POWERPC_604E_v24 = 0x00090204,
+ /* XXX: missing 0x000a0100 */
+ /* XXX: missing 0x00093102 */
+ CPU_POWERPC_604R = 0x000a0101,
+#if 0
+ CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
+#endif
+ /* PowerPC 740/750 cores (aka G3) */
+ /* XXX: missing 0x00084202 */
+ CPU_POWERPC_7x0_v10 = 0x00080100,
+ CPU_POWERPC_7x0_v20 = 0x00080200,
+ CPU_POWERPC_7x0_v21 = 0x00080201,
+ CPU_POWERPC_7x0_v22 = 0x00080202,
+ CPU_POWERPC_7x0_v30 = 0x00080300,
+ CPU_POWERPC_7x0_v31 = 0x00080301,
+ CPU_POWERPC_740E = 0x00080100,
+ CPU_POWERPC_750E = 0x00080200,
+ CPU_POWERPC_7x0P = 0x10080000,
+ /* XXX: missing 0x00087010 (CL ?) */
+ CPU_POWERPC_750CL_v10 = 0x00087200,
+ CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
+ CPU_POWERPC_750CX_v10 = 0x00082100,
+ CPU_POWERPC_750CX_v20 = 0x00082200,
+ CPU_POWERPC_750CX_v21 = 0x00082201,
+ CPU_POWERPC_750CX_v22 = 0x00082202,
+ CPU_POWERPC_750CXE_v21 = 0x00082211,
+ CPU_POWERPC_750CXE_v22 = 0x00082212,
+ CPU_POWERPC_750CXE_v23 = 0x00082213,
+ CPU_POWERPC_750CXE_v24 = 0x00082214,
+ CPU_POWERPC_750CXE_v24b = 0x00083214,
+ CPU_POWERPC_750CXE_v30 = 0x00082310,
+ CPU_POWERPC_750CXE_v31 = 0x00082311,
+ CPU_POWERPC_750CXE_v31b = 0x00083311,
+ CPU_POWERPC_750CXR = 0x00083410,
+ CPU_POWERPC_750FL = 0x70000203,
+ CPU_POWERPC_750FX_v10 = 0x70000100,
+ CPU_POWERPC_750FX_v20 = 0x70000200,
+ CPU_POWERPC_750FX_v21 = 0x70000201,
+ CPU_POWERPC_750FX_v22 = 0x70000202,
+ CPU_POWERPC_750FX_v23 = 0x70000203,
+ CPU_POWERPC_750GL = 0x70020102,
+ CPU_POWERPC_750GX_v10 = 0x70020100,
+ CPU_POWERPC_750GX_v11 = 0x70020101,
+ CPU_POWERPC_750GX_v12 = 0x70020102,
+ CPU_POWERPC_750L_v20 = 0x00088200,
+ CPU_POWERPC_750L_v21 = 0x00088201,
+ CPU_POWERPC_750L_v22 = 0x00088202,
+ CPU_POWERPC_750L_v30 = 0x00088300,
+ CPU_POWERPC_750L_v32 = 0x00088302,
+ /* PowerPC 745/755 cores */
+ CPU_POWERPC_7x5_v10 = 0x00083100,
+ CPU_POWERPC_7x5_v11 = 0x00083101,
+ CPU_POWERPC_7x5_v20 = 0x00083200,
+ CPU_POWERPC_7x5_v21 = 0x00083201,
+ CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
+ CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
+ CPU_POWERPC_7x5_v24 = 0x00083204,
+ CPU_POWERPC_7x5_v25 = 0x00083205,
+ CPU_POWERPC_7x5_v26 = 0x00083206,
+ CPU_POWERPC_7x5_v27 = 0x00083207,
+ CPU_POWERPC_7x5_v28 = 0x00083208,
+#if 0
+ CPU_POWERPC_7x5P = xxx,
+#endif
+ /* PowerPC 74xx cores (aka G4) */
+ /* XXX: missing 0x000C1101 */
+ CPU_POWERPC_7400_v10 = 0x000C0100,
+ CPU_POWERPC_7400_v11 = 0x000C0101,
+ CPU_POWERPC_7400_v20 = 0x000C0200,
+ CPU_POWERPC_7400_v21 = 0x000C0201,
+ CPU_POWERPC_7400_v22 = 0x000C0202,
+ CPU_POWERPC_7400_v26 = 0x000C0206,
+ CPU_POWERPC_7400_v27 = 0x000C0207,
+ CPU_POWERPC_7400_v28 = 0x000C0208,
+ CPU_POWERPC_7400_v29 = 0x000C0209,
+ CPU_POWERPC_7410_v10 = 0x800C1100,
+ CPU_POWERPC_7410_v11 = 0x800C1101,
+ CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
+ CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
+ CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
+ CPU_POWERPC_7448_v10 = 0x80040100,
+ CPU_POWERPC_7448_v11 = 0x80040101,
+ CPU_POWERPC_7448_v20 = 0x80040200,
+ CPU_POWERPC_7448_v21 = 0x80040201,
+ CPU_POWERPC_7450_v10 = 0x80000100,
+ CPU_POWERPC_7450_v11 = 0x80000101,
+ CPU_POWERPC_7450_v12 = 0x80000102,
+ CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
+ CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
+ CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
+ /* XXX: this entry might be a bug in some documentation */
+ CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
+ CPU_POWERPC_74x5_v10 = 0x80010100,
+ /* XXX: missing 0x80010200 */
+ CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
+ CPU_POWERPC_74x5_v32 = 0x80010302,
+ CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
+ CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
+ CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
+ CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
+ CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
+ CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
+ CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
+ CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
+ /* 64 bits PowerPC */
+#if defined(TARGET_PPC64)
+ CPU_POWERPC_620 = 0x00140000,
+ CPU_POWERPC_630 = 0x00400000,
+ CPU_POWERPC_631 = 0x00410104,
+ CPU_POWERPC_POWER4 = 0x00350000,
+ CPU_POWERPC_POWER4P = 0x00380000,
+ /* XXX: missing 0x003A0201 */
+ CPU_POWERPC_POWER5 = 0x003A0203,
+#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
+ CPU_POWERPC_POWER5P = 0x003B0000,
+#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
+ CPU_POWERPC_POWER6 = 0x003E0000,
+ CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
+ CPU_POWERPC_POWER6A = 0x0F000002,
+ CPU_POWERPC_POWER7_v20 = 0x003F0200,
+ CPU_POWERPC_POWER7_v21 = 0x003F0201,
+ CPU_POWERPC_POWER7_v23 = 0x003F0203,
+ CPU_POWERPC_970 = 0x00390202,
+ CPU_POWERPC_970FX_v10 = 0x00391100,
+ CPU_POWERPC_970FX_v20 = 0x003C0200,
+ CPU_POWERPC_970FX_v21 = 0x003C0201,
+ CPU_POWERPC_970FX_v30 = 0x003C0300,
+ CPU_POWERPC_970FX_v31 = 0x003C0301,
+ CPU_POWERPC_970GX = 0x00450000,
+ CPU_POWERPC_970MP_v10 = 0x00440100,
+ CPU_POWERPC_970MP_v11 = 0x00440101,
+#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
+ CPU_POWERPC_CELL_v10 = 0x00700100,
+ CPU_POWERPC_CELL_v20 = 0x00700400,
+ CPU_POWERPC_CELL_v30 = 0x00700500,
+ CPU_POWERPC_CELL_v31 = 0x00700501,
+#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
+ CPU_POWERPC_RS64 = 0x00330000,
+ CPU_POWERPC_RS64II = 0x00340000,
+ CPU_POWERPC_RS64III = 0x00360000,
+ CPU_POWERPC_RS64IV = 0x00370000,
+#endif /* defined(TARGET_PPC64) */
+ /* Original POWER */
+ /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
+ * POWER2 (RIOS2) & RSC2 (P2SC) here
+ */
+#if 0
+ CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
+#endif
+#if 0
+ CPU_POWER2 = xxx, /* 0x40000 ? */
+#endif
+ /* PA Semi core */
+ CPU_POWERPC_PA6T = 0x00900000,
+};
+
+/* System version register (used on MPC 8xxx) */
+enum {
+ POWERPC_SVR_NONE = 0x00000000,
+ POWERPC_SVR_5200_v10 = 0x80110010,
+ POWERPC_SVR_5200_v11 = 0x80110011,
+ POWERPC_SVR_5200_v12 = 0x80110012,
+ POWERPC_SVR_5200B_v20 = 0x80110020,
+ POWERPC_SVR_5200B_v21 = 0x80110021,
+#define POWERPC_SVR_55xx POWERPC_SVR_5567
+#if 0
+ POWERPC_SVR_5533 = xxx,
+#endif
+#if 0
+ POWERPC_SVR_5534 = xxx,
+#endif
+#if 0
+ POWERPC_SVR_5553 = xxx,
+#endif
+#if 0
+ POWERPC_SVR_5554 = xxx,
+#endif
+#if 0
+ POWERPC_SVR_5561 = xxx,
+#endif
+#if 0
+ POWERPC_SVR_5565 = xxx,
+#endif
+#if 0
+ POWERPC_SVR_5566 = xxx,
+#endif
+#if 0
+ POWERPC_SVR_5567 = xxx,
+#endif
+#if 0
+ POWERPC_SVR_8313 = xxx,
+#endif
+#if 0
+ POWERPC_SVR_8313E = xxx,
+#endif
+#if 0
+ POWERPC_SVR_8314 = xxx,
+#endif
+#if 0
+ POWERPC_SVR_8314E = xxx,
+#endif
+#if 0
+ POWERPC_SVR_8315 = xxx,
+#endif
+#if 0
+ POWERPC_SVR_8315E = xxx,
+#endif
+#if 0
+ POWERPC_SVR_8321 = xxx,
+#endif
+#if 0
+ POWERPC_SVR_8321E = xxx,
+#endif
+#if 0
+ POWERPC_SVR_8323 = xxx,
+#endif
+#if 0
+ POWERPC_SVR_8323E = xxx,
+#endif
+ POWERPC_SVR_8343 = 0x80570010,
+ POWERPC_SVR_8343A = 0x80570030,
+ POWERPC_SVR_8343E = 0x80560010,
+ POWERPC_SVR_8343EA = 0x80560030,
+ POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
+ POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
+ POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
+ POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
+ POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
+ POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
+ POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
+ POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
+ POWERPC_SVR_8349 = 0x80510010,
+ POWERPC_SVR_8349A = 0x80510030,
+ POWERPC_SVR_8349E = 0x80500010,
+ POWERPC_SVR_8349EA = 0x80500030,
+#if 0
+ POWERPC_SVR_8358E = xxx,
+#endif
+#if 0
+ POWERPC_SVR_8360E = xxx,
+#endif
+#define POWERPC_SVR_E500 0x40000000
+ POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
+ POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
+ POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
+ POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
+ POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
+ POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
+ POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
+ POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
+ POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
+ POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
+ POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
+ POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
+ POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
+ POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
+ POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
+ POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
+ POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
+ POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
+ POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
+ POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
+ POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
+ POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
+#if 0
+ POWERPC_SVR_8610 = xxx,
+#endif
+ POWERPC_SVR_8641 = 0x80900021,
+ POWERPC_SVR_8641D = 0x80900121,
+};
+
+#endif
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 31566e0..b0d4357 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -18,24 +18,17 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
-/* A lot of PowerPC definition have been included here.
- * Most of them are not usable for now but have been kept
- * inside "#if defined(TODO) ... #endif" statements to make tests easier.
- */
-
#include "disas/bfd.h"
#include "exec/gdbstub.h"
#include <sysemu/kvm.h>
#include "kvm_ppc.h"
#include "sysemu/arch_init.h"
#include "sysemu/cpus.h"
+#include "cpu-models.h"
//#define PPC_DUMP_CPU
//#define PPC_DEBUG_SPR
//#define PPC_DUMP_SPR_ACCESSES
-#if defined(CONFIG_USER_ONLY)
-#define TODO_USER_ONLY 1
-#endif
/* For user-mode emulation, we don't emulate any IRQ controller */
#if defined(CONFIG_USER_ONLY)
@@ -4876,18 +4869,16 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
/* Non-embedded PowerPC */
/* POWER : same as 601, without mfmsr, mfsr */
-#if defined(TODO)
POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
dc->desc = "POWER";
- pcc->insns_flags = XXX_TODO;
+ /* pcc->insns_flags = XXX_TODO; */
/* POWER RSC (from RAD6000) */
pcc->msr_mask = 0x00000000FEF0ULL;
}
-#endif /* TODO */
#define POWERPC_MSRR_601 (0x0000000000001040ULL)
@@ -7173,1900 +7164,6 @@ POWERPC_FAMILY(620)(ObjectClass *oc, void *data)
#endif /* defined (TARGET_PPC64) */
-/*****************************************************************************/
-/* PVR definitions for most known PowerPC */
-enum {
- /* PowerPC 401 family */
- /* Generic PowerPC 401 */
-#define CPU_POWERPC_401 CPU_POWERPC_401G2
- /* PowerPC 401 cores */
- CPU_POWERPC_401A1 = 0x00210000,
- CPU_POWERPC_401B2 = 0x00220000,
-#if 0
- CPU_POWERPC_401B3 = xxx,
-#endif
- CPU_POWERPC_401C2 = 0x00230000,
- CPU_POWERPC_401D2 = 0x00240000,
- CPU_POWERPC_401E2 = 0x00250000,
- CPU_POWERPC_401F2 = 0x00260000,
- CPU_POWERPC_401G2 = 0x00270000,
- /* PowerPC 401 microcontrolers */
-#if 0
- CPU_POWERPC_401GF = xxx,
-#endif
-#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
- /* IBM Processor for Network Resources */
- CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
-#if 0
- CPU_POWERPC_XIPCHIP = xxx,
-#endif
- /* PowerPC 403 family */
- /* PowerPC 403 microcontrollers */
- CPU_POWERPC_403GA = 0x00200011,
- CPU_POWERPC_403GB = 0x00200100,
- CPU_POWERPC_403GC = 0x00200200,
- CPU_POWERPC_403GCX = 0x00201400,
-#if 0
- CPU_POWERPC_403GP = xxx,
-#endif
- /* PowerPC 405 family */
- /* PowerPC 405 cores */
-#if 0
- CPU_POWERPC_405A3 = xxx,
-#endif
-#if 0
- CPU_POWERPC_405A4 = xxx,
-#endif
-#if 0
- CPU_POWERPC_405B3 = xxx,
-#endif
-#if 0
- CPU_POWERPC_405B4 = xxx,
-#endif
-#if 0
- CPU_POWERPC_405C3 = xxx,
-#endif
-#if 0
- CPU_POWERPC_405C4 = xxx,
-#endif
- CPU_POWERPC_405D2 = 0x20010000,
-#if 0
- CPU_POWERPC_405D3 = xxx,
-#endif
- CPU_POWERPC_405D4 = 0x41810000,
-#if 0
- CPU_POWERPC_405D5 = xxx,
-#endif
-#if 0
- CPU_POWERPC_405E4 = xxx,
-#endif
-#if 0
- CPU_POWERPC_405F4 = xxx,
-#endif
-#if 0
- CPU_POWERPC_405F5 = xxx,
-#endif
-#if 0
- CPU_POWERPC_405F6 = xxx,
-#endif
- /* PowerPC 405 microcontrolers */
- /* XXX: missing 0x200108a0 */
- CPU_POWERPC_405CRa = 0x40110041,
- CPU_POWERPC_405CRb = 0x401100C5,
- CPU_POWERPC_405CRc = 0x40110145,
- CPU_POWERPC_405EP = 0x51210950,
-#if 0
- CPU_POWERPC_405EXr = xxx,
-#endif
- CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
-#if 0
- CPU_POWERPC_405FX = xxx,
-#endif
- CPU_POWERPC_405GPa = 0x40110000,
- CPU_POWERPC_405GPb = 0x40110040,
- CPU_POWERPC_405GPc = 0x40110082,
- CPU_POWERPC_405GPd = 0x401100C4,
- CPU_POWERPC_405GPR = 0x50910951,
-#if 0
- CPU_POWERPC_405H = xxx,
-#endif
-#if 0
- CPU_POWERPC_405L = xxx,
-#endif
- CPU_POWERPC_405LP = 0x41F10000,
-#if 0
- CPU_POWERPC_405PM = xxx,
-#endif
-#if 0
- CPU_POWERPC_405PS = xxx,
-#endif
-#if 0
- CPU_POWERPC_405S = xxx,
-#endif
- /* IBM network processors */
- CPU_POWERPC_NPE405H = 0x414100C0,
- CPU_POWERPC_NPE405H2 = 0x41410140,
- CPU_POWERPC_NPE405L = 0x416100C0,
- CPU_POWERPC_NPE4GS3 = 0x40B10000,
-#if 0
- CPU_POWERPC_NPCxx1 = xxx,
-#endif
-#if 0
- CPU_POWERPC_NPR161 = xxx,
-#endif
-#if 0
- CPU_POWERPC_LC77700 = xxx,
-#endif
- /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
-#if 0
- CPU_POWERPC_STB01000 = xxx,
-#endif
-#if 0
- CPU_POWERPC_STB01010 = xxx,
-#endif
-#if 0
- CPU_POWERPC_STB0210 = xxx, /* 401B3 */
-#endif
- CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
-#if 0
- CPU_POWERPC_STB043 = xxx,
-#endif
-#if 0
- CPU_POWERPC_STB045 = xxx,
-#endif
- CPU_POWERPC_STB04 = 0x41810000,
- CPU_POWERPC_STB25 = 0x51510950,
-#if 0
- CPU_POWERPC_STB130 = xxx,
-#endif
- /* Xilinx cores */
- CPU_POWERPC_X2VP4 = 0x20010820,
- CPU_POWERPC_X2VP20 = 0x20010860,
-#if 0
- CPU_POWERPC_ZL10310 = xxx,
-#endif
-#if 0
- CPU_POWERPC_ZL10311 = xxx,
-#endif
-#if 0
- CPU_POWERPC_ZL10320 = xxx,
-#endif
-#if 0
- CPU_POWERPC_ZL10321 = xxx,
-#endif
- /* PowerPC 440 family */
- /* Generic PowerPC 440 */
-#define CPU_POWERPC_440 CPU_POWERPC_440GXf
- /* PowerPC 440 cores */
-#if 0
- CPU_POWERPC_440A4 = xxx,
-#endif
- CPU_POWERPC_440_XILINX = 0x7ff21910,
-#if 0
- CPU_POWERPC_440A5 = xxx,
-#endif
-#if 0
- CPU_POWERPC_440B4 = xxx,
-#endif
-#if 0
- CPU_POWERPC_440F5 = xxx,
-#endif
-#if 0
- CPU_POWERPC_440G5 = xxx,
-#endif
-#if 0
- CPU_POWERPC_440H4 = xxx,
-#endif
-#if 0
- CPU_POWERPC_440H6 = xxx,
-#endif
- /* PowerPC 440 microcontrolers */
- CPU_POWERPC_440EPa = 0x42221850,
- CPU_POWERPC_440EPb = 0x422218D3,
- CPU_POWERPC_440GPb = 0x40120440,
- CPU_POWERPC_440GPc = 0x40120481,
-#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
- CPU_POWERPC_440GRX = 0x200008D0,
-#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
- CPU_POWERPC_440GXa = 0x51B21850,
- CPU_POWERPC_440GXb = 0x51B21851,
- CPU_POWERPC_440GXc = 0x51B21892,
- CPU_POWERPC_440GXf = 0x51B21894,
-#if 0
- CPU_POWERPC_440S = xxx,
-#endif
- CPU_POWERPC_440SP = 0x53221850,
- CPU_POWERPC_440SP2 = 0x53221891,
- CPU_POWERPC_440SPE = 0x53421890,
- /* PowerPC 460 family */
-#if 0
- /* Generic PowerPC 464 */
-#define CPU_POWERPC_464 CPU_POWERPC_464H90
-#endif
- /* PowerPC 464 microcontrolers */
-#if 0
- CPU_POWERPC_464H90 = xxx,
-#endif
-#if 0
- CPU_POWERPC_464H90FP = xxx,
-#endif
- /* Freescale embedded PowerPC cores */
- /* PowerPC MPC 5xx cores (aka RCPU) */
- CPU_POWERPC_MPC5xx = 0x00020020,
- /* PowerPC MPC 8xx cores (aka PowerQUICC) */
- CPU_POWERPC_MPC8xx = 0x00500000,
- /* G2 cores (aka PowerQUICC-II) */
- CPU_POWERPC_G2 = 0x00810011,
- CPU_POWERPC_G2H4 = 0x80811010,
- CPU_POWERPC_G2gp = 0x80821010,
- CPU_POWERPC_G2ls = 0x90810010,
- CPU_POWERPC_MPC603 = 0x00810100,
- CPU_POWERPC_G2_HIP3 = 0x00810101,
- CPU_POWERPC_G2_HIP4 = 0x80811014,
- /* G2_LE core (aka PowerQUICC-II) */
- CPU_POWERPC_G2LE = 0x80820010,
- CPU_POWERPC_G2LEgp = 0x80822010,
- CPU_POWERPC_G2LEls = 0xA0822010,
- CPU_POWERPC_G2LEgp1 = 0x80822011,
- CPU_POWERPC_G2LEgp3 = 0x80822013,
- /* MPC52xx microcontrollers */
- /* XXX: MPC 5121 ? */
-#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
-#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
-#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
-#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
-#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
- /* e200 family */
- /* e200 cores */
-#if 0
- CPU_POWERPC_e200z0 = xxx,
-#endif
-#if 0
- CPU_POWERPC_e200z1 = xxx,
-#endif
-#if 0 /* ? */
- CPU_POWERPC_e200z3 = 0x81120000,
-#endif
- CPU_POWERPC_e200z5 = 0x81000000,
- CPU_POWERPC_e200z6 = 0x81120000,
- /* MPC55xx microcontrollers */
-#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
-#if 0
-#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
-#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
-#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
-#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
-#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
-#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
-#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
-#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
-#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
-#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
-#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
-#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
-#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
-#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
-#endif
-#if 0
-#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
-#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
-#endif
-#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
-#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
-#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
-#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
-#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
-#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
- /* e300 family */
- /* e300 cores */
- CPU_POWERPC_e300c1 = 0x00830010,
- CPU_POWERPC_e300c2 = 0x00840010,
- CPU_POWERPC_e300c3 = 0x00850010,
- CPU_POWERPC_e300c4 = 0x00860010,
- /* MPC83xx microcontrollers */
-#define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
-#define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
-#define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
- /* e500 family */
- /* e500 cores */
-#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
- CPU_POWERPC_e500v1_v10 = 0x80200010,
- CPU_POWERPC_e500v1_v20 = 0x80200020,
- CPU_POWERPC_e500v2_v10 = 0x80210010,
- CPU_POWERPC_e500v2_v11 = 0x80210011,
- CPU_POWERPC_e500v2_v20 = 0x80210020,
- CPU_POWERPC_e500v2_v21 = 0x80210021,
- CPU_POWERPC_e500v2_v22 = 0x80210022,
- CPU_POWERPC_e500v2_v30 = 0x80210030,
- CPU_POWERPC_e500mc = 0x80230020,
- CPU_POWERPC_e5500 = 0x80240020,
- /* MPC85xx microcontrollers */
-#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
-#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
-#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
-#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
-#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
-#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
-#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
-#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
-#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
-#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
-#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
-#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
-#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
-#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
-#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
-#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
-#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
-#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
-#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
-#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
-#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
-#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
-#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
-#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
-#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
-#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
- /* e600 family */
- /* e600 cores */
- CPU_POWERPC_e600 = 0x80040010,
- /* MPC86xx microcontrollers */
-#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
-#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
-#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
- /* PowerPC 6xx cores */
- CPU_POWERPC_601_v0 = 0x00010001,
- CPU_POWERPC_601_v1 = 0x00010001,
- CPU_POWERPC_601_v2 = 0x00010002,
- CPU_POWERPC_602 = 0x00050100,
- CPU_POWERPC_603 = 0x00030100,
- CPU_POWERPC_603E_v11 = 0x00060101,
- CPU_POWERPC_603E_v12 = 0x00060102,
- CPU_POWERPC_603E_v13 = 0x00060103,
- CPU_POWERPC_603E_v14 = 0x00060104,
- CPU_POWERPC_603E_v22 = 0x00060202,
- CPU_POWERPC_603E_v3 = 0x00060300,
- CPU_POWERPC_603E_v4 = 0x00060400,
- CPU_POWERPC_603E_v41 = 0x00060401,
- CPU_POWERPC_603E7t = 0x00071201,
- CPU_POWERPC_603E7v = 0x00070100,
- CPU_POWERPC_603E7v1 = 0x00070101,
- CPU_POWERPC_603E7v2 = 0x00070201,
- CPU_POWERPC_603E7 = 0x00070200,
- CPU_POWERPC_603P = 0x00070000,
- /* XXX: missing 0x00040303 (604) */
- CPU_POWERPC_604 = 0x00040103,
- /* XXX: missing 0x00091203 */
- /* XXX: missing 0x00092110 */
- /* XXX: missing 0x00092120 */
- CPU_POWERPC_604E_v10 = 0x00090100,
- CPU_POWERPC_604E_v22 = 0x00090202,
- CPU_POWERPC_604E_v24 = 0x00090204,
- /* XXX: missing 0x000a0100 */
- /* XXX: missing 0x00093102 */
- CPU_POWERPC_604R = 0x000a0101,
-#if 0
- CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
-#endif
- /* PowerPC 740/750 cores (aka G3) */
- /* XXX: missing 0x00084202 */
- CPU_POWERPC_7x0_v10 = 0x00080100,
- CPU_POWERPC_7x0_v20 = 0x00080200,
- CPU_POWERPC_7x0_v21 = 0x00080201,
- CPU_POWERPC_7x0_v22 = 0x00080202,
- CPU_POWERPC_7x0_v30 = 0x00080300,
- CPU_POWERPC_7x0_v31 = 0x00080301,
- CPU_POWERPC_740E = 0x00080100,
- CPU_POWERPC_750E = 0x00080200,
- CPU_POWERPC_7x0P = 0x10080000,
- /* XXX: missing 0x00087010 (CL ?) */
- CPU_POWERPC_750CL_v10 = 0x00087200,
- CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
- CPU_POWERPC_750CX_v10 = 0x00082100,
- CPU_POWERPC_750CX_v20 = 0x00082200,
- CPU_POWERPC_750CX_v21 = 0x00082201,
- CPU_POWERPC_750CX_v22 = 0x00082202,
- CPU_POWERPC_750CXE_v21 = 0x00082211,
- CPU_POWERPC_750CXE_v22 = 0x00082212,
- CPU_POWERPC_750CXE_v23 = 0x00082213,
- CPU_POWERPC_750CXE_v24 = 0x00082214,
- CPU_POWERPC_750CXE_v24b = 0x00083214,
- CPU_POWERPC_750CXE_v30 = 0x00082310,
- CPU_POWERPC_750CXE_v31 = 0x00082311,
- CPU_POWERPC_750CXE_v31b = 0x00083311,
- CPU_POWERPC_750CXR = 0x00083410,
- CPU_POWERPC_750FL = 0x70000203,
- CPU_POWERPC_750FX_v10 = 0x70000100,
- CPU_POWERPC_750FX_v20 = 0x70000200,
- CPU_POWERPC_750FX_v21 = 0x70000201,
- CPU_POWERPC_750FX_v22 = 0x70000202,
- CPU_POWERPC_750FX_v23 = 0x70000203,
- CPU_POWERPC_750GL = 0x70020102,
- CPU_POWERPC_750GX_v10 = 0x70020100,
- CPU_POWERPC_750GX_v11 = 0x70020101,
- CPU_POWERPC_750GX_v12 = 0x70020102,
- CPU_POWERPC_750L_v20 = 0x00088200,
- CPU_POWERPC_750L_v21 = 0x00088201,
- CPU_POWERPC_750L_v22 = 0x00088202,
- CPU_POWERPC_750L_v30 = 0x00088300,
- CPU_POWERPC_750L_v32 = 0x00088302,
- /* PowerPC 745/755 cores */
- CPU_POWERPC_7x5_v10 = 0x00083100,
- CPU_POWERPC_7x5_v11 = 0x00083101,
- CPU_POWERPC_7x5_v20 = 0x00083200,
- CPU_POWERPC_7x5_v21 = 0x00083201,
- CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
- CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
- CPU_POWERPC_7x5_v24 = 0x00083204,
- CPU_POWERPC_7x5_v25 = 0x00083205,
- CPU_POWERPC_7x5_v26 = 0x00083206,
- CPU_POWERPC_7x5_v27 = 0x00083207,
- CPU_POWERPC_7x5_v28 = 0x00083208,
-#if 0
- CPU_POWERPC_7x5P = xxx,
-#endif
- /* PowerPC 74xx cores (aka G4) */
- /* XXX: missing 0x000C1101 */
- CPU_POWERPC_7400_v10 = 0x000C0100,
- CPU_POWERPC_7400_v11 = 0x000C0101,
- CPU_POWERPC_7400_v20 = 0x000C0200,
- CPU_POWERPC_7400_v21 = 0x000C0201,
- CPU_POWERPC_7400_v22 = 0x000C0202,
- CPU_POWERPC_7400_v26 = 0x000C0206,
- CPU_POWERPC_7400_v27 = 0x000C0207,
- CPU_POWERPC_7400_v28 = 0x000C0208,
- CPU_POWERPC_7400_v29 = 0x000C0209,
- CPU_POWERPC_7410_v10 = 0x800C1100,
- CPU_POWERPC_7410_v11 = 0x800C1101,
- CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
- CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
- CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
- CPU_POWERPC_7448_v10 = 0x80040100,
- CPU_POWERPC_7448_v11 = 0x80040101,
- CPU_POWERPC_7448_v20 = 0x80040200,
- CPU_POWERPC_7448_v21 = 0x80040201,
- CPU_POWERPC_7450_v10 = 0x80000100,
- CPU_POWERPC_7450_v11 = 0x80000101,
- CPU_POWERPC_7450_v12 = 0x80000102,
- CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
- CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
- CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
- /* XXX: this entry might be a bug in some documentation */
- CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
- CPU_POWERPC_74x5_v10 = 0x80010100,
- /* XXX: missing 0x80010200 */
- CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
- CPU_POWERPC_74x5_v32 = 0x80010302,
- CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
- CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
- CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
- CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
- CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
- CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
- CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
- CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
- /* 64 bits PowerPC */
-#if defined(TARGET_PPC64)
- CPU_POWERPC_620 = 0x00140000,
- CPU_POWERPC_630 = 0x00400000,
- CPU_POWERPC_631 = 0x00410104,
- CPU_POWERPC_POWER4 = 0x00350000,
- CPU_POWERPC_POWER4P = 0x00380000,
- /* XXX: missing 0x003A0201 */
- CPU_POWERPC_POWER5 = 0x003A0203,
-#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
- CPU_POWERPC_POWER5P = 0x003B0000,
-#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
- CPU_POWERPC_POWER6 = 0x003E0000,
- CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
- CPU_POWERPC_POWER6A = 0x0F000002,
- CPU_POWERPC_POWER7_v20 = 0x003F0200,
- CPU_POWERPC_POWER7_v21 = 0x003F0201,
- CPU_POWERPC_POWER7_v23 = 0x003F0203,
- CPU_POWERPC_970 = 0x00390202,
- CPU_POWERPC_970FX_v10 = 0x00391100,
- CPU_POWERPC_970FX_v20 = 0x003C0200,
- CPU_POWERPC_970FX_v21 = 0x003C0201,
- CPU_POWERPC_970FX_v30 = 0x003C0300,
- CPU_POWERPC_970FX_v31 = 0x003C0301,
- CPU_POWERPC_970GX = 0x00450000,
- CPU_POWERPC_970MP_v10 = 0x00440100,
- CPU_POWERPC_970MP_v11 = 0x00440101,
-#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
- CPU_POWERPC_CELL_v10 = 0x00700100,
- CPU_POWERPC_CELL_v20 = 0x00700400,
- CPU_POWERPC_CELL_v30 = 0x00700500,
- CPU_POWERPC_CELL_v31 = 0x00700501,
-#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
- CPU_POWERPC_RS64 = 0x00330000,
- CPU_POWERPC_RS64II = 0x00340000,
- CPU_POWERPC_RS64III = 0x00360000,
- CPU_POWERPC_RS64IV = 0x00370000,
-#endif /* defined(TARGET_PPC64) */
- /* Original POWER */
- /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
- * POWER2 (RIOS2) & RSC2 (P2SC) here
- */
-#if 0
- CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
-#endif
-#if 0
- CPU_POWER2 = xxx, /* 0x40000 ? */
-#endif
- /* PA Semi core */
- CPU_POWERPC_PA6T = 0x00900000,
-};
-
-/* System version register (used on MPC 8xxx) */
-enum {
- POWERPC_SVR_NONE = 0x00000000,
- POWERPC_SVR_5200_v10 = 0x80110010,
- POWERPC_SVR_5200_v11 = 0x80110011,
- POWERPC_SVR_5200_v12 = 0x80110012,
- POWERPC_SVR_5200B_v20 = 0x80110020,
- POWERPC_SVR_5200B_v21 = 0x80110021,
-#define POWERPC_SVR_55xx POWERPC_SVR_5567
-#if 0
- POWERPC_SVR_5533 = xxx,
-#endif
-#if 0
- POWERPC_SVR_5534 = xxx,
-#endif
-#if 0
- POWERPC_SVR_5553 = xxx,
-#endif
-#if 0
- POWERPC_SVR_5554 = xxx,
-#endif
-#if 0
- POWERPC_SVR_5561 = xxx,
-#endif
-#if 0
- POWERPC_SVR_5565 = xxx,
-#endif
-#if 0
- POWERPC_SVR_5566 = xxx,
-#endif
-#if 0
- POWERPC_SVR_5567 = xxx,
-#endif
-#if 0
- POWERPC_SVR_8313 = xxx,
-#endif
-#if 0
- POWERPC_SVR_8313E = xxx,
-#endif
-#if 0
- POWERPC_SVR_8314 = xxx,
-#endif
-#if 0
- POWERPC_SVR_8314E = xxx,
-#endif
-#if 0
- POWERPC_SVR_8315 = xxx,
-#endif
-#if 0
- POWERPC_SVR_8315E = xxx,
-#endif
-#if 0
- POWERPC_SVR_8321 = xxx,
-#endif
-#if 0
- POWERPC_SVR_8321E = xxx,
-#endif
-#if 0
- POWERPC_SVR_8323 = xxx,
-#endif
-#if 0
- POWERPC_SVR_8323E = xxx,
-#endif
- POWERPC_SVR_8343 = 0x80570010,
- POWERPC_SVR_8343A = 0x80570030,
- POWERPC_SVR_8343E = 0x80560010,
- POWERPC_SVR_8343EA = 0x80560030,
- POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
- POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
- POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
- POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
- POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
- POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
- POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
- POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
- POWERPC_SVR_8349 = 0x80510010,
- POWERPC_SVR_8349A = 0x80510030,
- POWERPC_SVR_8349E = 0x80500010,
- POWERPC_SVR_8349EA = 0x80500030,
-#if 0
- POWERPC_SVR_8358E = xxx,
-#endif
-#if 0
- POWERPC_SVR_8360E = xxx,
-#endif
-#define POWERPC_SVR_E500 0x40000000
- POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
- POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
- POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
- POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
- POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
- POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
- POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
- POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
- POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
- POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
- POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
- POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
- POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
- POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
- POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
- POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
- POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
- POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
- POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
- POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
- POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
- POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
- POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
- POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
- POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
- POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
- POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
- POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
- POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
- POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
- POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
- POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
- POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
- POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
- POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
- POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
- POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
- POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
- POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
- POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
- POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
- POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
- POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
- POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
- POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
- POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
- POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
- POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
- POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
- POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
- POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
- POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
- POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
- POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
- POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
- POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
-#if 0
- POWERPC_SVR_8610 = xxx,
-#endif
- POWERPC_SVR_8641 = 0x80900021,
- POWERPC_SVR_8641D = 0x80900121,
-};
-
-/***************************************************************************/
-/* PowerPC CPU definitions */
-#define POWERPC_DEF_PREFIX(pvr, svr, type) \
- glue(glue(glue(glue(pvr, _), svr), _), type)
-#define POWERPC_DEF_SVR(_name, _desc, _pvr, _svr, _type) \
- static void \
- glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init) \
- (ObjectClass *oc, void *data) \
- { \
- DeviceClass *dc = DEVICE_CLASS(oc); \
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); \
- \
- pcc->pvr = _pvr; \
- pcc->svr = _svr; \
- dc->desc = _desc; \
- } \
- \
- static const TypeInfo \
- glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info) = { \
- .name = _name "-" TYPE_POWERPC_CPU, \
- .parent = stringify(_type) "-family-" TYPE_POWERPC_CPU, \
- .class_init = \
- glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init), \
- }; \
- \
- static void \
- glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types)(void) \
- { \
- type_register_static( \
- &glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info)); \
- } \
- \
- type_init( \
- glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types))
-
-#define POWERPC_DEF(_name, _pvr, _type, _desc) \
- POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type)
-
- /* Embedded PowerPC */
- /* PowerPC 401 family */
- POWERPC_DEF("401", CPU_POWERPC_401, 401,
- "Generic PowerPC 401")
- /* PowerPC 401 cores */
- POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401,
- "PowerPC 401A1")
- POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2,
- "PowerPC 401B2")
-#if defined(TODO)
- POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3,
- "PowerPC 401B3")
-#endif
- POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2,
- "PowerPC 401C2")
- POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2,
- "PowerPC 401D2")
- POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2,
- "PowerPC 401E2")
- POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2,
- "PowerPC 401F2")
- /* XXX: to be checked */
- POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2,
- "PowerPC 401G2")
- /* PowerPC 401 microcontrolers */
-#if defined(TODO)
- POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401,
- "PowerPC 401GF")
-#endif
- POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480,
- "IOP480 (401 microcontroller)")
- POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401,
- "IBM Processor for Network Resources")
-#if defined(TODO)
- POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401,
- NULL)
-#endif
- /* PowerPC 403 family */
- /* PowerPC 403 microcontrolers */
- POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403,
- "PowerPC 403 GA")
- POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403,
- "PowerPC 403 GB")
- POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403,
- "PowerPC 403 GC")
- POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX,
- "PowerPC 403 GCX")
-#if defined(TODO)
- POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403,
- "PowerPC 403 GP")
-#endif
- /* PowerPC 405 family */
- /* PowerPC 405 cores */
-#if defined(TODO)
- POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405,
- "PowerPC 405 A3")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405,
- "PowerPC 405 A4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405,
- "PowerPC 405 B3")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405,
- "PowerPC 405 B4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405,
- "PowerPC 405 C3")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405,
- "PowerPC 405 C4")
-#endif
- POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405,
- "PowerPC 405 D2")
-#if defined(TODO)
- POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405,
- "PowerPC 405 D3")
-#endif
- POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405,
- "PowerPC 405 D4")
-#if defined(TODO)
- POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405,
- "PowerPC 405 D5")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405,
- "PowerPC 405 E4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405,
- "PowerPC 405 F4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405,
- "PowerPC 405 F5")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405,
- "PowerPC 405 F6")
-#endif
- /* PowerPC 405 microcontrolers */
- POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405,
- "PowerPC 405 CRa")
- POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405,
- "PowerPC 405 CRb")
- POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405,
- "PowerPC 405 CRc")
- POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405,
- "PowerPC 405 EP")
-#if defined(TODO)
- POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405,
- "PowerPC 405 EXr")
-#endif
- POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405,
- "PowerPC 405 EZ")
-#if defined(TODO)
- POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405,
- "PowerPC 405 FX")
-#endif
- POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405,
- "PowerPC 405 GPa")
- POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405,
- "PowerPC 405 GPb")
- POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405,
- "PowerPC 405 GPc")
- POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405,
- "PowerPC 405 GPd")
- POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405,
- "PowerPC 405 GPR")
-#if defined(TODO)
- POWERPC_DEF("405H", CPU_POWERPC_405H, 405,
- "PowerPC 405 H")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405L", CPU_POWERPC_405L, 405,
- "PowerPC 405 L")
-#endif
- POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405,
- "PowerPC 405 LP")
-#if defined(TODO)
- POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405,
- "PowerPC 405 PM")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405,
- "PowerPC 405 PS")
-#endif
-#if defined(TODO)
- POWERPC_DEF("405S", CPU_POWERPC_405S, 405,
- "PowerPC 405 S")
-#endif
- POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405,
- "Npe405 H")
- POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405,
- "Npe405 H2")
- POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405,
- "Npe405 L")
- POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405,
- "Npe4GS3")
-#if defined(TODO)
- POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405,
- NULL)
-#endif
-#if defined(TODO)
- POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405,
- NULL)
-#endif
-#if defined(TODO)
- POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405,
- "PowerPC LC77700 (Sanyo)")
-#endif
- /* PowerPC 401/403/405 based set-top-box microcontrolers */
-#if defined(TODO)
- POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2,
- "STB010000")
-#endif
-#if defined(TODO)
- POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2,
- "STB01010")
-#endif
-#if defined(TODO)
- POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3,
- "STB0210")
-#endif
- POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405,
- "STB03xx")
-#if defined(TODO)
- POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405,
- "STB043x")
-#endif
-#if defined(TODO)
- POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405,
- "STB045x")
-#endif
- POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405,
- "STB04xx")
- POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405,
- "STB25xx")
-#if defined(TODO)
- POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405,
- "STB130")
-#endif
- /* Xilinx PowerPC 405 cores */
- POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405,
- NULL)
- POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405,
- NULL)
-#if defined(TODO)
- POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405,
- "Zarlink ZL10310")
-#endif
-#if defined(TODO)
- POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405,
- "Zarlink ZL10311")
-#endif
-#if defined(TODO)
- POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405,
- "Zarlink ZL10320")
-#endif
-#if defined(TODO)
- POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405,
- "Zarlink ZL10321")
-#endif
- /* PowerPC 440 family */
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440", CPU_POWERPC_440, 440GP,
- "Generic PowerPC 440")
-#endif
- /* PowerPC 440 cores */
-#if defined(TODO)
- POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4,
- "PowerPC 440 A4")
-#endif
- POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5,
- "PowerPC 440 Xilinx 5")
-#if defined(TODO)
- POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5,
- "PowerPC 440 A5")
-#endif
-#if defined(TODO)
- POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4,
- "PowerPC 440 B4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4,
- "PowerPC 440 G4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5,
- "PowerPC 440 F5")
-#endif
-#if defined(TODO)
- POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5,
- "PowerPC 440 G5")
-#endif
-#if defined(TODO)
- POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4,
- "PowerPC 440H4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5,
- "PowerPC 440H6")
-#endif
- /* PowerPC 440 microcontrolers */
- POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP,
- "PowerPC 440 EPa")
- POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP,
- "PowerPC 440 EPb")
- POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP,
- "PowerPC 440 EPX")
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP,
- "PowerPC 440 GPb")
-#endif
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP,
- "PowerPC 440 GPc")
-#endif
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5,
- "PowerPC 440 GRa")
-#endif
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5,
- "PowerPC 440 GRX")
-#endif
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP,
- "PowerPC 440 GXa")
-#endif
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP,
- "PowerPC 440 GXb")
-#endif
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP,
- "PowerPC 440 GXc")
-#endif
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP,
- "PowerPC 440 GXf")
-#endif
-#if defined(TODO)
- POWERPC_DEF("440S", CPU_POWERPC_440S, 440,
- "PowerPC 440 S")
-#endif
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP,
- "PowerPC 440 SP")
-#endif
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP,
- "PowerPC 440 SP2")
-#endif
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP,
- "PowerPC 440 SPE")
-#endif
- /* PowerPC 460 family */
-#if defined(TODO)
- POWERPC_DEF("464", CPU_POWERPC_464, 460,
- "Generic PowerPC 464")
-#endif
- /* PowerPC 464 microcontrolers */
-#if defined(TODO)
- POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460,
- "PowerPC 464H90")
-#endif
-#if defined(TODO)
- POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F,
- "PowerPC 464H90F")
-#endif
- /* Freescale embedded PowerPC cores */
- /* MPC5xx family (aka RCPU) */
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx,
- "Generic MPC5xx core")
-#endif
- /* MPC8xx family (aka PowerQUICC) */
-#if defined(TODO_USER_ONLY)
- POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx,
- "Generic MPC8xx core")
-#endif
- /* MPC82xx family (aka PowerQUICC-II) */
- POWERPC_DEF("G2", CPU_POWERPC_G2, G2,
- "PowerPC G2 core")
- POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2,
- "PowerPC G2 H4 core")
- POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2,
- "PowerPC G2 GP core")
- POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2,
- "PowerPC G2 LS core")
- POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2,
- "PowerPC G2 HiP3 core")
- POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2,
- "PowerPC G2 HiP4 core")
- POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E,
- "PowerPC MPC603 core")
- POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE,
- "PowerPC G2le core (same as G2 plus little-endian mode support)")
- POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE,
- "PowerPC G2LE GP core")
- POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE,
- "PowerPC G2LE LS core")
- POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE,
- "PowerPC G2LE GP1 core")
- POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2LE,
- "PowerPC G2LE GP3 core")
- /* PowerPC G2 microcontrollers */
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5121", "MPC5121",
- CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE)
-#endif
- POWERPC_DEF_SVR("MPC5200_v10", "MPC5200 v1.0",
- CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE)
- POWERPC_DEF_SVR("MPC5200_v11", "MPC5200 v1.1",
- CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE)
- POWERPC_DEF_SVR("MPC5200_v12", "MPC5200 v1.2",
- CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE)
- POWERPC_DEF_SVR("MPC5200B_v20", "MPC5200B v2.0",
- CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
- POWERPC_DEF_SVR("MPC5200B_v21", "MPC5200B v2.1",
- CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
- /* e200 family */
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC55xx", "Generic MPC55xx core",
- CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200,
- "PowerPC e200z0 core")
-#endif
-#if defined(TODO)
- POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200,
- "PowerPC e200z1 core")
-#endif
-#if defined(TODO)
- POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200,
- "PowerPC e200z3 core")
-#endif
- POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200,
- "PowerPC e200z5 core")
- POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200,
- "PowerPC e200z6 core")
- /* PowerPC e200 microcontrollers */
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5514E", "MPC5514E",
- CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5514E_v0", "MPC5514E v0",
- CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5514E_v1", "MPC5514E v1",
- CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5514G", "MPC5514G",
- CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5514G_v0", "MPC5514G v0",
- CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5514G_v1", "MPC5514G v1",
- CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5515S", "MPC5515S",
- CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516E", "MPC5516E",
- CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516E_v0", "MPC5516E v0",
- CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516E_v1", "MPC5516E v1",
- CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516G", "MPC5516G",
- CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516G_v0", "MPC5516G v0",
- CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516G_v1", "MPC5516G v1",
- CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5516S", "MPC5516S",
- CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5533", "MPC5533",
- CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5534", "MPC5534",
- CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5553", "MPC5553",
- CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5554", "MPC5554",
- CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5561", "MPC5561",
- CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5565", "MPC5565",
- CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5566", "MPC5566",
- CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC5567", "MPC5567",
- CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200)
-#endif
- /* e300 family */
- POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300,
- "PowerPC e300c1 core")
- POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300,
- "PowerPC e300c2 core")
- POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300,
- "PowerPC e300c3 core")
- POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300,
- "PowerPC e300c4 core")
- /* PowerPC e300 microcontrollers */
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC8313", "MPC8313",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC8313E", "MPC8313E",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC8314", "MPC8314",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC8314E", "MPC8314E",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC8315", "MPC8315",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC8315E", "MPC8315E",
- CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC8321", "MPC8321",
- CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC8321E", "MPC8321E",
- CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC8323", "MPC8323",
- CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC8323E", "MPC8323E",
- CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300)
-#endif
- POWERPC_DEF_SVR("MPC8343", "MPC8343",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300)
- POWERPC_DEF_SVR("MPC8343A", "MPC8343A",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300)
- POWERPC_DEF_SVR("MPC8343E", "MPC8343E",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300)
- POWERPC_DEF_SVR("MPC8343EA", "MPC8343EA",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300)
- POWERPC_DEF_SVR("MPC8347T", "MPC8347T",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300)
- POWERPC_DEF_SVR("MPC8347P", "MPC8347P",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300)
- POWERPC_DEF_SVR("MPC8347AT", "MPC8347AT",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300)
- POWERPC_DEF_SVR("MPC8347AP", "MPC8347AP",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300)
- POWERPC_DEF_SVR("MPC8347ET", "MPC8347ET",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300)
- POWERPC_DEF_SVR("MPC8347EP", "MPC8343EP",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300)
- POWERPC_DEF_SVR("MPC8347EAT", "MPC8347EAT",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300)
- POWERPC_DEF_SVR("MPC8347EAP", "MPC8343EAP",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300)
- POWERPC_DEF_SVR("MPC8349", "MPC8349",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300)
- POWERPC_DEF_SVR("MPC8349A", "MPC8349A",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300)
- POWERPC_DEF_SVR("MPC8349E", "MPC8349E",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300)
- POWERPC_DEF_SVR("MPC8349EA", "MPC8349EA",
- CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300)
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC8358E", "MPC8358E",
- CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300)
-#endif
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC8360E", "MPC8360E",
- CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300)
-#endif
- POWERPC_DEF_SVR("MPC8377", "MPC8377",
- CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300)
- POWERPC_DEF_SVR("MPC8377E", "MPC8377E",
- CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300)
- POWERPC_DEF_SVR("MPC8378", "MPC8378",
- CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300)
- POWERPC_DEF_SVR("MPC8378E", "MPC8378E",
- CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300)
- POWERPC_DEF_SVR("MPC8379", "MPC8379",
- CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300)
- POWERPC_DEF_SVR("MPC8379E", "MPC8379E",
- CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300)
- /* e500 family */
- POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1,
- "PowerPC e500 v1.0 core")
- POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1,
- "PowerPC e500 v2.0 core")
- POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2,
- "PowerPC e500v2 v1.0 core")
- POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2,
- "PowerPC e500v2 v2.0 core")
- POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2,
- "PowerPC e500v2 v2.1 core")
- POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2,
- "PowerPC e500v2 v2.2 core")
- POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2,
- "PowerPC e500v2 v3.0 core")
- POWERPC_DEF_SVR("e500mc", "e500mc",
- CPU_POWERPC_e500mc, POWERPC_SVR_E500, e500mc)
-#ifdef TARGET_PPC64
- POWERPC_DEF_SVR("e5500", "e5500",
- CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500)
-#endif
- /* PowerPC e500 microcontrollers */
- POWERPC_DEF_SVR("MPC8533_v10", "MPC8533 v1.0",
- CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2)
- POWERPC_DEF_SVR("MPC8533_v11", "MPC8533 v1.1",
- CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2)
- POWERPC_DEF_SVR("MPC8533E_v10", "MPC8533E v1.0",
- CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2)
- POWERPC_DEF_SVR("MPC8533E_v11", "MPC8533E v1.1",
- CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2)
- POWERPC_DEF_SVR("MPC8540_v10", "MPC8540 v1.0",
- CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1)
- POWERPC_DEF_SVR("MPC8540_v20", "MPC8540 v2.0",
- CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1)
- POWERPC_DEF_SVR("MPC8540_v21", "MPC8540 v2.1",
- CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1)
- POWERPC_DEF_SVR("MPC8541_v10", "MPC8541 v1.0",
- CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1)
- POWERPC_DEF_SVR("MPC8541_v11", "MPC8541 v1.1",
- CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1)
- POWERPC_DEF_SVR("MPC8541E_v10", "MPC8541E v1.0",
- CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1)
- POWERPC_DEF_SVR("MPC8541E_v11", "MPC8541E v1.1",
- CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1)
- POWERPC_DEF_SVR("MPC8543_v10", "MPC8543 v1.0",
- CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2)
- POWERPC_DEF_SVR("MPC8543_v11", "MPC8543 v1.1",
- CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2)
- POWERPC_DEF_SVR("MPC8543_v20", "MPC8543 v2.0",
- CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2)
- POWERPC_DEF_SVR("MPC8543_v21", "MPC8543 v2.1",
- CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2)
- POWERPC_DEF_SVR("MPC8543E_v10", "MPC8543E v1.0",
- CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2)
- POWERPC_DEF_SVR("MPC8543E_v11", "MPC8543E v1.1",
- CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2)
- POWERPC_DEF_SVR("MPC8543E_v20", "MPC8543E v2.0",
- CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2)
- POWERPC_DEF_SVR("MPC8543E_v21", "MPC8543E v2.1",
- CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2)
- POWERPC_DEF_SVR("MPC8544_v10", "MPC8544 v1.0",
- CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2)
- POWERPC_DEF_SVR("MPC8544_v11", "MPC8544 v1.1",
- CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2)
- POWERPC_DEF_SVR("MPC8544E_v10", "MPC8544E v1.0",
- CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2)
- POWERPC_DEF_SVR("MPC8544E_v11", "MPC8544E v1.1",
- CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2)
- POWERPC_DEF_SVR("MPC8545_v20", "MPC8545 v2.0",
- CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2)
- POWERPC_DEF_SVR("MPC8545_v21", "MPC8545 v2.1",
- CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2)
- POWERPC_DEF_SVR("MPC8545E_v20", "MPC8545E v2.0",
- CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2)
- POWERPC_DEF_SVR("MPC8545E_v21", "MPC8545E v2.1",
- CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2)
- POWERPC_DEF_SVR("MPC8547E_v20", "MPC8547E v2.0",
- CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2)
- POWERPC_DEF_SVR("MPC8547E_v21", "MPC8547E v2.1",
- CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2)
- POWERPC_DEF_SVR("MPC8548_v10", "MPC8548 v1.0",
- CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2)
- POWERPC_DEF_SVR("MPC8548_v11", "MPC8548 v1.1",
- CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2)
- POWERPC_DEF_SVR("MPC8548_v20", "MPC8548 v2.0",
- CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2)
- POWERPC_DEF_SVR("MPC8548_v21", "MPC8548 v2.1",
- CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2)
- POWERPC_DEF_SVR("MPC8548E_v10", "MPC8548E v1.0",
- CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2)
- POWERPC_DEF_SVR("MPC8548E_v11", "MPC8548E v1.1",
- CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2)
- POWERPC_DEF_SVR("MPC8548E_v20", "MPC8548E v2.0",
- CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2)
- POWERPC_DEF_SVR("MPC8548E_v21", "MPC8548E v2.1",
- CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2)
- POWERPC_DEF_SVR("MPC8555_v10", "MPC8555 v1.0",
- CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2)
- POWERPC_DEF_SVR("MPC8555_v11", "MPC8555 v1.1",
- CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2)
- POWERPC_DEF_SVR("MPC8555E_v10", "MPC8555E v1.0",
- CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2)
- POWERPC_DEF_SVR("MPC8555E_v11", "MPC8555E v1.1",
- CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2)
- POWERPC_DEF_SVR("MPC8560_v10", "MPC8560 v1.0",
- CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2)
- POWERPC_DEF_SVR("MPC8560_v20", "MPC8560 v2.0",
- CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2)
- POWERPC_DEF_SVR("MPC8560_v21", "MPC8560 v2.1",
- CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2)
- POWERPC_DEF_SVR("MPC8567", "MPC8567",
- CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2)
- POWERPC_DEF_SVR("MPC8567E", "MPC8567E",
- CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2)
- POWERPC_DEF_SVR("MPC8568", "MPC8568",
- CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2)
- POWERPC_DEF_SVR("MPC8568E", "MPC8568E",
- CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2)
- POWERPC_DEF_SVR("MPC8572", "MPC8572",
- CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2)
- POWERPC_DEF_SVR("MPC8572E", "MPC8572E",
- CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2)
- /* e600 family */
- POWERPC_DEF("e600", CPU_POWERPC_e600, 7400,
- "PowerPC e600 core")
- /* PowerPC e600 microcontrollers */
-#if defined(TODO)
- POWERPC_DEF_SVR("MPC8610", "MPC8610",
- CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400)
-#endif
- POWERPC_DEF_SVR("MPC8641", "MPC8641",
- CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400)
- POWERPC_DEF_SVR("MPC8641D", "MPC8641D",
- CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400)
- /* 32 bits "classic" PowerPC */
- /* PowerPC 6xx family */
- POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601,
- "PowerPC 601v0")
- POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601,
- "PowerPC 601v1")
- POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v,
- "PowerPC 601v2")
- POWERPC_DEF("602", CPU_POWERPC_602, 602,
- "PowerPC 602")
- POWERPC_DEF("603", CPU_POWERPC_603, 603,
- "PowerPC 603")
- POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E,
- "PowerPC 603e v1.1")
- POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E,
- "PowerPC 603e v1.2")
- POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E,
- "PowerPC 603e v1.3")
- POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E,
- "PowerPC 603e v1.4")
- POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E,
- "PowerPC 603e v2.2")
- POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E,
- "PowerPC 603e v3")
- POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E,
- "PowerPC 603e v4")
- POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E,
- "PowerPC 603e v4.1")
- POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E,
- "PowerPC 603e (aka PID7)")
- POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E,
- "PowerPC 603e7t")
- POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E,
- "PowerPC 603e7v")
- POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E,
- "PowerPC 603e7v1")
- POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E,
- "PowerPC 603e7v2")
- POWERPC_DEF("603p", CPU_POWERPC_603P, 603E,
- "PowerPC 603p (aka PID7v)")
- POWERPC_DEF("604", CPU_POWERPC_604, 604,
- "PowerPC 604")
- POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E,
- "PowerPC 604e v1.0")
- POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E,
- "PowerPC 604e v2.2")
- POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E,
- "PowerPC 604e v2.4")
- POWERPC_DEF("604r", CPU_POWERPC_604R, 604E,
- "PowerPC 604r (aka PIDA)")
-#if defined(TODO)
- POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E,
- "PowerPC 604ev")
-#endif
- /* PowerPC 7xx family */
- POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740,
- "PowerPC 740 v1.0 (G3)")
- POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750,
- "PowerPC 750 v1.0 (G3)")
- POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740,
- "PowerPC 740 v2.0 (G3)")
- POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750,
- "PowerPC 750 v2.0 (G3)")
- POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740,
- "PowerPC 740 v2.1 (G3)")
- POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750,
- "PowerPC 750 v2.1 (G3)")
- POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740,
- "PowerPC 740 v2.2 (G3)")
- POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750,
- "PowerPC 750 v2.2 (G3)")
- POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740,
- "PowerPC 740 v3.0 (G3)")
- POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750,
- "PowerPC 750 v3.0 (G3)")
- POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740,
- "PowerPC 740 v3.1 (G3)")
- POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750,
- "PowerPC 750 v3.1 (G3)")
- POWERPC_DEF("740e", CPU_POWERPC_740E, 740,
- "PowerPC 740E (G3)")
- POWERPC_DEF("750e", CPU_POWERPC_750E, 750,
- "PowerPC 750E (G3)")
- POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740,
- "PowerPC 740P (G3)")
- POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750,
- "PowerPC 750P (G3)")
- POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl,
- "PowerPC 750CL v1.0")
- POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl,
- "PowerPC 750CL v2.0")
- POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx,
- "PowerPC 750CX v1.0 (G3 embedded)")
- POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx,
- "PowerPC 750CX v2.1 (G3 embedded)")
- POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx,
- "PowerPC 750CX v2.1 (G3 embedded)")
- POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx,
- "PowerPC 750CX v2.2 (G3 embedded)")
- POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx,
- "PowerPC 750CXe v2.1 (G3 embedded)")
- POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx,
- "PowerPC 750CXe v2.2 (G3 embedded)")
- POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx,
- "PowerPC 750CXe v2.3 (G3 embedded)")
- POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx,
- "PowerPC 750CXe v2.4 (G3 embedded)")
- POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx,
- "PowerPC 750CXe v2.4b (G3 embedded)")
- POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx,
- "PowerPC 750CXe v3.0 (G3 embedded)")
- POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx,
- "PowerPC 750CXe v3.1 (G3 embedded)")
- POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx,
- "PowerPC 750CXe v3.1b (G3 embedded)")
- POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx,
- "PowerPC 750CXr (G3 embedded)")
- POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx,
- "PowerPC 750FL (G3 embedded)")
- POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx,
- "PowerPC 750FX v1.0 (G3 embedded)")
- POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx,
- "PowerPC 750FX v2.0 (G3 embedded)")
- POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx,
- "PowerPC 750FX v2.1 (G3 embedded)")
- POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx,
- "PowerPC 750FX v2.2 (G3 embedded)")
- POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx,
- "PowerPC 750FX v2.3 (G3 embedded)")
- POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx,
- "PowerPC 750GL (G3 embedded)")
- POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx,
- "PowerPC 750GX v1.0 (G3 embedded)")
- POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx,
- "PowerPC 750GX v1.1 (G3 embedded)")
- POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx,
- "PowerPC 750GX v1.2 (G3 embedded)")
- POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750,
- "PowerPC 750L v2.0 (G3 embedded)")
- POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750,
- "PowerPC 750L v2.1 (G3 embedded)")
- POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750,
- "PowerPC 750L v2.2 (G3 embedded)")
- POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750,
- "PowerPC 750L v3.0 (G3 embedded)")
- POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750,
- "PowerPC 750L v3.2 (G3 embedded)")
- POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745,
- "PowerPC 745 v1.0")
- POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755,
- "PowerPC 755 v1.0")
- POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745,
- "PowerPC 745 v1.1")
- POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755,
- "PowerPC 755 v1.1")
- POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745,
- "PowerPC 745 v2.0")
- POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755,
- "PowerPC 755 v2.0")
- POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745,
- "PowerPC 745 v2.1")
- POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755,
- "PowerPC 755 v2.1")
- POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745,
- "PowerPC 745 v2.2")
- POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755,
- "PowerPC 755 v2.2")
- POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745,
- "PowerPC 745 v2.3")
- POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755,
- "PowerPC 755 v2.3")
- POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745,
- "PowerPC 745 v2.4")
- POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755,
- "PowerPC 755 v2.4")
- POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745,
- "PowerPC 745 v2.5")
- POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755,
- "PowerPC 755 v2.5")
- POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745,
- "PowerPC 745 v2.6")
- POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755,
- "PowerPC 755 v2.6")
- POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745,
- "PowerPC 745 v2.7")
- POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755,
- "PowerPC 755 v2.7")
- POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745,
- "PowerPC 745 v2.8")
- POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755,
- "PowerPC 755 v2.8")
-#if defined(TODO)
- POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745,
- "PowerPC 745P (G3)")
- POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755,
- "PowerPC 755P (G3)")
-#endif
- /* PowerPC 74xx family */
- POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400,
- "PowerPC 7400 v1.0 (G4)")
- POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400,
- "PowerPC 7400 v1.1 (G4)")
- POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400,
- "PowerPC 7400 v2.0 (G4)")
- POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400,
- "PowerPC 7400 v2.1 (G4)")
- POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400,
- "PowerPC 7400 v2.2 (G4)")
- POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400,
- "PowerPC 7400 v2.6 (G4)")
- POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400,
- "PowerPC 7400 v2.7 (G4)")
- POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400,
- "PowerPC 7400 v2.8 (G4)")
- POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400,
- "PowerPC 7400 v2.9 (G4)")
- POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410,
- "PowerPC 7410 v1.0 (G4)")
- POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410,
- "PowerPC 7410 v1.1 (G4)")
- POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410,
- "PowerPC 7410 v1.2 (G4)")
- POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410,
- "PowerPC 7410 v1.3 (G4)")
- POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410,
- "PowerPC 7410 v1.4 (G4)")
- POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400,
- "PowerPC 7448 v1.0 (G4)")
- POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400,
- "PowerPC 7448 v1.1 (G4)")
- POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400,
- "PowerPC 7448 v2.0 (G4)")
- POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400,
- "PowerPC 7448 v2.1 (G4)")
- POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450,
- "PowerPC 7450 v1.0 (G4)")
- POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450,
- "PowerPC 7450 v1.1 (G4)")
- POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450,
- "PowerPC 7450 v1.2 (G4)")
- POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450,
- "PowerPC 7450 v2.0 (G4)")
- POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450,
- "PowerPC 7450 v2.1 (G4)")
- POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440,
- "PowerPC 7441 v2.1 (G4)")
- POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440,
- "PowerPC 7441 v2.3 (G4)")
- POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450,
- "PowerPC 7451 v2.3 (G4)")
- POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440,
- "PowerPC 7441 v2.10 (G4)")
- POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450,
- "PowerPC 7451 v2.10 (G4)")
- POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445,
- "PowerPC 7445 v1.0 (G4)")
- POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455,
- "PowerPC 7455 v1.0 (G4)")
- POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445,
- "PowerPC 7445 v2.1 (G4)")
- POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455,
- "PowerPC 7455 v2.1 (G4)")
- POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445,
- "PowerPC 7445 v3.2 (G4)")
- POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455,
- "PowerPC 7455 v3.2 (G4)")
- POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445,
- "PowerPC 7445 v3.3 (G4)")
- POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455,
- "PowerPC 7455 v3.3 (G4)")
- POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445,
- "PowerPC 7445 v3.4 (G4)")
- POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455,
- "PowerPC 7455 v3.4 (G4)")
- POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445,
- "PowerPC 7447 v1.0 (G4)")
- POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455,
- "PowerPC 7457 v1.0 (G4)")
- POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445,
- "PowerPC 7447 v1.1 (G4)")
- POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455,
- "PowerPC 7457 v1.1 (G4)")
- POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455,
- "PowerPC 7457 v1.2 (G4)")
- POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445,
- "PowerPC 7447A v1.0 (G4)")
- POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455,
- "PowerPC 7457A v1.0 (G4)")
- POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445,
- "PowerPC 7447A v1.1 (G4)")
- POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455,
- "PowerPC 7457A v1.1 (G4)")
- POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445,
- "PowerPC 7447A v1.2 (G4)")
- POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455,
- "PowerPC 7457A v1.2 (G4)")
- /* 64 bits PowerPC */
-#if defined (TARGET_PPC64)
- POWERPC_DEF("620", CPU_POWERPC_620, 620,
- "PowerPC 620")
-#if defined(TODO)
- POWERPC_DEF("630", CPU_POWERPC_630, 630,
- "PowerPC 630 (POWER3)")
-#endif
-#if defined(TODO)
- POWERPC_DEF("631", CPU_POWERPC_631, 631,
- "PowerPC 631 (Power 3+)")
-#endif
-#if defined(TODO)
- POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4,
- "POWER4")
-#endif
-#if defined(TODO)
- POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P,
- "POWER4p")
-#endif
-#if defined(TODO)
- POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5,
- "POWER5")
- POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5,
- "POWER5GR")
-#endif
-#if defined(TODO)
- POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P,
- "POWER5+")
- POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P,
- "POWER5GS")
-#endif
-#if defined(TODO)
- POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6,
- "POWER6")
- POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5,
- "POWER6 running in POWER5 mode")
- POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6,
- "POWER6A")
-#endif
- POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7,
- "POWER7 v2.0")
- POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7,
- "POWER7 v2.1")
- POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7,
- "POWER7 v2.3")
- POWERPC_DEF("970", CPU_POWERPC_970, 970,
- "PowerPC 970")
- POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX,
- "PowerPC 970FX v1.0 (G5)")
- POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX,
- "PowerPC 970FX v2.0 (G5)")
- POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX,
- "PowerPC 970FX v2.1 (G5)")
- POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX,
- "PowerPC 970FX v3.0 (G5)")
- POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX,
- "PowerPC 970FX v3.1 (G5)")
- POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX,
- "PowerPC 970GX (G5)")
- POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP,
- "PowerPC 970MP v1.0")
- POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP,
- "PowerPC 970MP v1.1")
-#if defined(TODO)
- POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970,
- "PowerPC Cell")
-#endif
-#if defined(TODO)
- POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970,
- "PowerPC Cell v1.0")
-#endif
-#if defined(TODO)
- POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970,
- "PowerPC Cell v2.0")
-#endif
-#if defined(TODO)
- POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970,
- "PowerPC Cell v3.0")
-#endif
-#if defined(TODO)
- POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970,
- "PowerPC Cell v3.1")
-#endif
-#if defined(TODO)
- POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970,
- "PowerPC Cell v3.2")
-#endif
-#if defined(TODO)
- /* This one seems to support the whole POWER2 instruction set
- * and the PowerPC 64 one.
- */
- /* What about A10 & A30 ? */
- POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64,
- "RS64 (Apache/A35)")
-#endif
-#if defined(TODO)
- POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64,
- "RS64-II (NorthStar/A50)")
-#endif
-#if defined(TODO)
- POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64,
- "RS64-III (Pulsar)")
-#endif
-#if defined(TODO)
- POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64,
- "RS64-IV (IceStar/IStar/SStar)")
-#endif
-#endif /* defined (TARGET_PPC64) */
- /* POWER */
-#if defined(TODO)
- POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER,
- "Original POWER")
-#endif
-#if defined(TODO)
- POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER,
- "POWER2")
-#endif
- /* PA semi cores */
-#if defined(TODO)
- POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T,
- "PA PA6T")
-#endif
typedef struct PowerPCCPUAlias {
const char *alias;
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 53/66] target-ppc: Fix remaining microcontroller typos among models
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (51 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 52/66] target-ppc: Split model definitions out of translate_init.c Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 54/66] target-ppc: Change "POWER7" CPU alias Alexander Graf
` (13 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
controler -> controller
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/cpu-models.c | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index f0be585..66408c0 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -93,7 +93,7 @@
/* XXX: to be checked */
POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2,
"PowerPC 401G2")
- /* PowerPC 401 microcontrolers */
+ /* PowerPC 401 microcontrollers */
#if defined(TODO)
POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401,
"PowerPC 401GF")
@@ -107,7 +107,7 @@
NULL)
#endif
/* PowerPC 403 family */
- /* PowerPC 403 microcontrolers */
+ /* PowerPC 403 microcontrollers */
POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403,
"PowerPC 403 GA")
POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403,
@@ -174,7 +174,7 @@
POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405,
"PowerPC 405 F6")
#endif
- /* PowerPC 405 microcontrolers */
+ /* PowerPC 405 microcontrollers */
POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405,
"PowerPC 405 CRa")
POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405,
@@ -245,7 +245,7 @@
POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405,
"PowerPC LC77700 (Sanyo)")
#endif
- /* PowerPC 401/403/405 based set-top-box microcontrolers */
+ /* PowerPC 401/403/405 based set-top-box microcontrollers */
#if defined(TODO)
POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2,
"STB010000")
@@ -337,7 +337,7 @@
POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5,
"PowerPC 440H6")
#endif
- /* PowerPC 440 microcontrolers */
+ /* PowerPC 440 microcontrollers */
POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP,
"PowerPC 440 EPa")
POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP,
@@ -397,7 +397,7 @@
POWERPC_DEF("464", CPU_POWERPC_464, 460,
"Generic PowerPC 464")
#endif
- /* PowerPC 464 microcontrolers */
+ /* PowerPC 464 microcontrollers */
#if defined(TODO)
POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460,
"PowerPC 464H90")
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 54/66] target-ppc: Change "POWER7" CPU alias
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (52 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 53/66] target-ppc: Fix remaining microcontroller typos among models Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 55/66] pseries: Implement h_read hcall Alexander Graf
` (12 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Let it resolve to v2.3 rather than v2.0.
Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index b0d4357..1015077 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7332,7 +7332,7 @@ static const PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "Boxer", "POWER3" },
{ "Dino", "POWER3" },
{ "POWER3+", "631" },
- { "POWER7", "POWER7_v2.0" },
+ { "POWER7", "POWER7_v2.3" },
{ "970fx", "970fx_v3.1" },
{ "970mp", "970mp_v1.1" },
{ "Apache", "RS64" },
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 55/66] pseries: Implement h_read hcall
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (53 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 54/66] target-ppc: Change "POWER7" CPU alias Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 56/66] Save memory allocation in the elf loader Alexander Graf
` (11 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, Erlon Cruz, qemu-ppc@nongnu.org list:PowerPC,
Aurélien Jarno
From: Erlon Cruz <erlon.cruz@br.flextronics.com>
This h_call is useful for DLPAR in future amongst other things. Given an index
it fetches the corresponding PTE stored in the htab.
Signed-off-by: Erlon Cruz <erlon.cruz@br.flextronics.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/spapr_hcall.c | 31 +++++++++++++++++++++++++++++++
1 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c
index 7b89594..77c052f 100644
--- a/hw/spapr_hcall.c
+++ b/hw/spapr_hcall.c
@@ -323,6 +323,36 @@ static target_ulong h_protect(PowerPCCPU *cpu, sPAPREnvironment *spapr,
return H_SUCCESS;
}
+static target_ulong h_read(PowerPCCPU *cpu, sPAPREnvironment *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ CPUPPCState *env = &cpu->env;
+ target_ulong flags = args[0];
+ target_ulong pte_index = args[1];
+ uint8_t *hpte;
+ int i, ridx, n_entries = 1;
+
+ if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
+ return H_PARAMETER;
+ }
+
+ if (flags & H_READ_4) {
+ /* Clear the two low order bits */
+ pte_index &= ~(3ULL);
+ n_entries = 4;
+ }
+
+ hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
+
+ for (i = 0, ridx = 0; i < n_entries; i++) {
+ args[ridx++] = ldq_p(hpte);
+ args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
+ hpte += HASH_PTE_SIZE_64;
+ }
+
+ return H_SUCCESS;
+}
+
static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
@@ -710,6 +740,7 @@ static void hypercall_register_types(void)
spapr_register_hypercall(H_ENTER, h_enter);
spapr_register_hypercall(H_REMOVE, h_remove);
spapr_register_hypercall(H_PROTECT, h_protect);
+ spapr_register_hypercall(H_READ, h_read);
/* hcall-bulk */
spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove);
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 56/66] Save memory allocation in the elf loader
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (54 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 55/66] pseries: Implement h_read hcall Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 57/66] target-ppc: Add mechanism for synchronizing SPRs with KVM Alexander Graf
` (10 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Fabien Chouteau,
Aurélien Jarno
From: Fabien Chouteau <chouteau@adacore.com>
The current elf loader uses too much memory. For example, I have a
executable with a bss section of 400 MB and I set the ram size to 512
MB. Qemu uses about 780MB of RAM (which is fine), but there's a peak at
1.6 GB during initialization (this is not fine).
This patch fixes two things:
1) do not allocate each elf program twice.
2) do not allocate memory for areas that are only zeros.
For this we need a new field in Rom: "datasize" which is the size of the
allocated data. If datasize is less than romsize, it means that the area
from datasize to romsize is filled with zeros.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/elf_ops.h | 19 ++++++++------
hw/loader.c | 75 +++++++++++++++++++++++++++++++++++++++++++++++----------
hw/loader.h | 2 +
3 files changed, 75 insertions(+), 21 deletions(-)
diff --git a/hw/elf_ops.h b/hw/elf_ops.h
index 531a425..acc701e 100644
--- a/hw/elf_ops.h
+++ b/hw/elf_ops.h
@@ -197,7 +197,7 @@ static int glue(load_elf, SZ)(const char *name, int fd,
struct elfhdr ehdr;
struct elf_phdr *phdr = NULL, *ph;
int size, i, total_size;
- elf_word mem_size;
+ elf_word mem_size, file_size;
uint64_t addr, low = (uint64_t)-1, high = 0;
uint8_t *data = NULL;
char label[128];
@@ -252,14 +252,16 @@ static int glue(load_elf, SZ)(const char *name, int fd,
for(i = 0; i < ehdr.e_phnum; i++) {
ph = &phdr[i];
if (ph->p_type == PT_LOAD) {
- mem_size = ph->p_memsz;
- /* XXX: avoid allocating */
- data = g_malloc0(mem_size);
+ mem_size = ph->p_memsz; /* Size of the ROM */
+ file_size = ph->p_filesz; /* Size of the allocated data */
+ data = g_malloc0(file_size);
if (ph->p_filesz > 0) {
- if (lseek(fd, ph->p_offset, SEEK_SET) < 0)
+ if (lseek(fd, ph->p_offset, SEEK_SET) < 0) {
goto fail;
- if (read(fd, data, ph->p_filesz) != ph->p_filesz)
+ }
+ if (read(fd, data, file_size) != file_size) {
goto fail;
+ }
}
/* address_offset is hack for kernel images that are
linked at the wrong physical address. */
@@ -281,7 +283,9 @@ static int glue(load_elf, SZ)(const char *name, int fd,
}
snprintf(label, sizeof(label), "phdr #%d: %s", i, name);
- rom_add_blob_fixed(label, data, mem_size, addr);
+
+ /* rom_add_elf_program() seize the ownership of 'data' */
+ rom_add_elf_program(label, data, file_size, mem_size, addr);
total_size += mem_size;
if (addr < low)
@@ -289,7 +293,6 @@ static int glue(load_elf, SZ)(const char *name, int fd,
if ((addr + mem_size) > high)
high = addr + mem_size;
- g_free(data);
data = NULL;
}
}
diff --git a/hw/loader.c b/hw/loader.c
index 995edc3..bd2b52d 100644
--- a/hw/loader.c
+++ b/hw/loader.c
@@ -533,7 +533,14 @@ typedef struct Rom Rom;
struct Rom {
char *name;
char *path;
+
+ /* datasize is the amount of memory allocated in "data". If datasize is less
+ * than romsize, it means that the area from datasize to romsize is filled
+ * with zeros.
+ */
size_t romsize;
+ size_t datasize;
+
uint8_t *data;
int isrom;
char *fw_dir;
@@ -589,14 +596,15 @@ int rom_add_file(const char *file, const char *fw_dir,
rom->fw_dir = g_strdup(fw_dir);
rom->fw_file = g_strdup(file);
}
- rom->addr = addr;
- rom->romsize = lseek(fd, 0, SEEK_END);
- rom->data = g_malloc0(rom->romsize);
+ rom->addr = addr;
+ rom->romsize = lseek(fd, 0, SEEK_END);
+ rom->datasize = rom->romsize;
+ rom->data = g_malloc0(rom->datasize);
lseek(fd, 0, SEEK_SET);
- rc = read(fd, rom->data, rom->romsize);
- if (rc != rom->romsize) {
+ rc = read(fd, rom->data, rom->datasize);
+ if (rc != rom->datasize) {
fprintf(stderr, "rom: file %-20s: read error: rc=%d (expected %zd)\n",
- rom->name, rc, rom->romsize);
+ rom->name, rc, rom->datasize);
goto err;
}
close(fd);
@@ -637,16 +645,37 @@ int rom_add_blob(const char *name, const void *blob, size_t len,
{
Rom *rom;
- rom = g_malloc0(sizeof(*rom));
- rom->name = g_strdup(name);
- rom->addr = addr;
- rom->romsize = len;
- rom->data = g_malloc0(rom->romsize);
+ rom = g_malloc0(sizeof(*rom));
+ rom->name = g_strdup(name);
+ rom->addr = addr;
+ rom->romsize = len;
+ rom->datasize = len;
+ rom->data = g_malloc0(rom->datasize);
memcpy(rom->data, blob, len);
rom_insert(rom);
return 0;
}
+/* This function is specific for elf program because we don't need to allocate
+ * all the rom. We just allocate the first part and the rest is just zeros. This
+ * is why romsize and datasize are different. Also, this function seize the
+ * memory ownership of "data", so we don't have to allocate and copy the buffer.
+ */
+int rom_add_elf_program(const char *name, void *data, size_t datasize,
+ size_t romsize, hwaddr addr)
+{
+ Rom *rom;
+
+ rom = g_malloc0(sizeof(*rom));
+ rom->name = g_strdup(name);
+ rom->addr = addr;
+ rom->datasize = datasize;
+ rom->romsize = romsize;
+ rom->data = data;
+ rom_insert(rom);
+ return 0;
+}
+
int rom_add_vga(const char *file)
{
return rom_add_file(file, "vgaroms", 0, -1);
@@ -668,7 +697,7 @@ static void rom_reset(void *unused)
if (rom->data == NULL) {
continue;
}
- cpu_physical_memory_write_rom(rom->addr, rom->data, rom->romsize);
+ cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
if (rom->isrom) {
/* rom needs to be written only once */
g_free(rom->data);
@@ -756,13 +785,33 @@ int rom_copy(uint8_t *dest, hwaddr addr, size_t size)
d = dest + (rom->addr - addr);
s = rom->data;
- l = rom->romsize;
+ l = rom->datasize;
if ((d + l) > (dest + size)) {
l = dest - d;
}
memcpy(d, s, l);
+
+ if (rom->romsize > rom->datasize) {
+ /* If datasize is less than romsize, it means that we didn't
+ * allocate all the ROM because the trailing data are only zeros.
+ */
+
+ d += l;
+ l = rom->romsize - rom->datasize;
+
+ if ((d + l) > (dest + size)) {
+ /* Rom size doesn't fit in the destination area. Adjust to avoid
+ * overflow.
+ */
+ l = dest - d;
+ }
+
+ if (l > 0) {
+ memset(d, 0x0, l);
+ }
+ }
}
return (d + l) - dest;
diff --git a/hw/loader.h b/hw/loader.h
index 5e61c95..0958f06 100644
--- a/hw/loader.h
+++ b/hw/loader.h
@@ -27,6 +27,8 @@ int rom_add_file(const char *file, const char *fw_dir,
hwaddr addr, int32_t bootindex);
int rom_add_blob(const char *name, const void *blob, size_t len,
hwaddr addr);
+int rom_add_elf_program(const char *name, void *data, size_t datasize,
+ size_t romsize, hwaddr addr);
int rom_load_all(void);
void rom_set_fw(void *f);
int rom_copy(uint8_t *dest, hwaddr addr, size_t size);
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 57/66] target-ppc: Add mechanism for synchronizing SPRs with KVM
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (55 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 56/66] Save memory allocation in the elf loader Alexander Graf
@ 2013-03-08 20:06 ` Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 58/66] target-ppc: Synchronize FPU state " Alexander Graf
` (9 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:06 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Aurélien Jarno,
David Gibson
From: David Gibson <david@gibson.dropbear.id.au>
Currently when runing under KVM on ppc, we synchronize a certain number of
vital SPRs to KVM through the SET_SREGS call. This leaves out quite a lot
of important SPRs which are maintained in KVM. It would be helpful to
have their contents in qemu for debugging purposes, and when we implement
migration it will be vital, since they include important guest state that
will need to be restored on the target.
This patch sets up for synchronization of any registers supported by the
KVM ONE_REG calls. A new variant on spr_register() allows a ONE_REG id to
be stored with the SPR information. When we set/get information to KVM
we also synchronize any SPRs so registered.
For now we set this mechanism up to synchronize a handful of important
registers that already have ONE_REG IDs, notably the DAR and DSISR.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/cpu.h | 6 ++
target-ppc/kvm.c | 115 ++++++++++++++++++++++++++++++++++++++++---
target-ppc/translate_init.c | 114 ++++++++++++++++++++++++------------------
3 files changed, 178 insertions(+), 57 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index e4cf96c..417abb0 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -329,6 +329,12 @@ struct ppc_spr_t {
void (*hea_write)(void *opaque, int spr_num, int gpr_num);
#endif
const char *name;
+#ifdef CONFIG_KVM
+ /* We (ab)use the fact that all the SPRs will have ids for the
+ * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
+ * don't sync this */
+ uint64_t one_reg_id;
+#endif
};
/* Altivec registers (128 bits) */
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index a89c3cf..02ab559 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -61,6 +61,7 @@ static int cap_ppc_smt;
static int cap_ppc_rma;
static int cap_spapr_tce;
static int cap_hior;
+static int cap_one_reg;
/* XXX We have a race condition where we actually have a level triggered
* interrupt, but the infrastructure can't expose that yet, so the guest
@@ -89,6 +90,7 @@ int kvm_arch_init(KVMState *s)
cap_ppc_smt = kvm_check_extension(s, KVM_CAP_PPC_SMT);
cap_ppc_rma = kvm_check_extension(s, KVM_CAP_PPC_RMA);
cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
+ cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
if (!cap_interrupt_level) {
@@ -449,6 +451,76 @@ static void kvm_sw_tlb_put(PowerPCCPU *cpu)
g_free(bitmap);
}
+static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+ union {
+ uint32_t u32;
+ uint64_t u64;
+ } val;
+ struct kvm_one_reg reg = {
+ .id = id,
+ .addr = (uintptr_t) &val,
+ };
+ int ret;
+
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
+ if (ret != 0) {
+ fprintf(stderr, "Warning: Unable to retrieve SPR %d from KVM: %s\n",
+ spr, strerror(errno));
+ } else {
+ switch (id & KVM_REG_SIZE_MASK) {
+ case KVM_REG_SIZE_U32:
+ env->spr[spr] = val.u32;
+ break;
+
+ case KVM_REG_SIZE_U64:
+ env->spr[spr] = val.u64;
+ break;
+
+ default:
+ /* Don't handle this size yet */
+ abort();
+ }
+ }
+}
+
+static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+ union {
+ uint32_t u32;
+ uint64_t u64;
+ } val;
+ struct kvm_one_reg reg = {
+ .id = id,
+ .addr = (uintptr_t) &val,
+ };
+ int ret;
+
+ switch (id & KVM_REG_SIZE_MASK) {
+ case KVM_REG_SIZE_U32:
+ val.u32 = env->spr[spr];
+ break;
+
+ case KVM_REG_SIZE_U64:
+ val.u64 = env->spr[spr];
+ break;
+
+ default:
+ /* Don't handle this size yet */
+ abort();
+ }
+
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
+ if (ret != 0) {
+ fprintf(stderr, "Warning: Unable to set SPR %d to KVM: %s\n",
+ spr, strerror(errno));
+ }
+}
+
int kvm_arch_put_registers(CPUState *cs, int level)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -530,15 +602,22 @@ int kvm_arch_put_registers(CPUState *cs, int level)
}
if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
- uint64_t hior = env->spr[SPR_HIOR];
- struct kvm_one_reg reg = {
- .id = KVM_REG_PPC_HIOR,
- .addr = (uintptr_t) &hior,
- };
+ kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
+ }
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
- if (ret) {
- return ret;
+ if (cap_one_reg) {
+ int i;
+
+ /* We deliberately ignore errors here, for kernels which have
+ * the ONE_REG calls, but don't support the specific
+ * registers, there's a reasonable chance things will still
+ * work, at least until we try to migrate. */
+ for (i = 0; i < 1024; i++) {
+ uint64_t id = env->spr_cb[i].one_reg_id;
+
+ if (id != 0) {
+ kvm_put_one_spr(cs, id, i);
+ }
}
}
@@ -721,6 +800,26 @@ int kvm_arch_get_registers(CPUState *cs)
}
}
+ if (cap_hior) {
+ kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
+ }
+
+ if (cap_one_reg) {
+ int i;
+
+ /* We deliberately ignore errors here, for kernels which have
+ * the ONE_REG calls, but don't support the specific
+ * registers, there's a reasonable chance things will still
+ * work, at least until we try to migrate. */
+ for (i = 0; i < 1024; i++) {
+ uint64_t id = env->spr_cb[i].one_reg_id;
+
+ if (id != 0) {
+ kvm_get_one_spr(cs, id, i);
+ }
+ }
+ }
+
return 0;
}
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 1015077..7fb314c 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -572,26 +572,42 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val)
set_flush_to_zero(vscr_nj, &env->vec_status);
}
-#if defined(CONFIG_USER_ONLY)
-#define spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, initial_value) \
-do { \
- _spr_register(env, num, name, uea_read, uea_write, initial_value); \
-} while (0)
-static inline void _spr_register (CPUPPCState *env, int num,
- const char *name,
- void (*uea_read)(void *opaque, int gprn, int sprn),
- void (*uea_write)(void *opaque, int sprn, int gprn),
- target_ulong initial_value)
+#ifdef CONFIG_USER_ONLY
+#define spr_register_kvm(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, initial_value)
+#else
+#if !defined(CONFIG_KVM)
+#define spr_register_kvm(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, initial_value)
#else
-static inline void spr_register (CPUPPCState *env, int num,
+#define spr_register_kvm(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, one_reg_id, initial_value)
+#endif
+#endif
+
+#define spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, initial_value) \
+ spr_register_kvm(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, 0, initial_value)
+
+static inline void _spr_register(CPUPPCState *env, int num,
const char *name,
void (*uea_read)(void *opaque, int gprn, int sprn),
void (*uea_write)(void *opaque, int sprn, int gprn),
+#if !defined(CONFIG_USER_ONLY)
+
void (*oea_read)(void *opaque, int gprn, int sprn),
void (*oea_write)(void *opaque, int sprn, int gprn),
- target_ulong initial_value)
#endif
+#if defined(CONFIG_KVM)
+ uint64_t one_reg_id,
+#endif
+ target_ulong initial_value)
{
ppc_spr_t *spr;
@@ -667,14 +683,14 @@ static void gen_spr_generic (CPUPPCState *env)
static void gen_spr_ne_601 (CPUPPCState *env)
{
/* Exception processing */
- spr_register(env, SPR_DSISR, "DSISR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_DAR, "DAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ spr_register_kvm(env, SPR_DSISR, "DSISR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DSISR, 0x00000000);
+ spr_register_kvm(env, SPR_DAR, "DAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DAR, 0x00000000);
/* Timer */
spr_register(env, SPR_DECR, "DECR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -918,10 +934,10 @@ static void gen_spr_7xx (CPUPPCState *env)
{
/* Breakpoints */
/* XXX : not implemented */
- spr_register(env, SPR_DABR, "DABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ spr_register_kvm(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DABR, 0x00000000);
/* XXX : not implemented */
spr_register(env, SPR_IABR, "IABR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -1047,10 +1063,10 @@ static void gen_spr_604 (CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_DABR, "DABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ spr_register_kvm(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DABR, 0x00000000);
/* Performance counters */
/* XXX : not implemented */
spr_register(env, SPR_MMCR0, "MMCR0",
@@ -2305,14 +2321,14 @@ static void gen_spr_620 (CPUPPCState *env)
static void gen_spr_5xx_8xx (CPUPPCState *env)
{
/* Exception processing */
- spr_register(env, SPR_DSISR, "DSISR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_DAR, "DAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ spr_register_kvm(env, SPR_DSISR, "DSISR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DSISR, 0x00000000);
+ spr_register_kvm(env, SPR_DAR, "DAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DAR, 0x00000000);
/* Timer */
spr_register(env, SPR_DECR, "DECR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7036,22 +7052,22 @@ static void init_proc_POWER7 (CPUPPCState *env)
0x00000000);
#if !defined(CONFIG_USER_ONLY)
/* PURR & SPURR: Hack - treat these as aliases for the TB for now */
- spr_register(env, SPR_PURR, "PURR",
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPURR, "SPURR",
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, SPR_NOACCESS,
- 0x00000000);
+ spr_register_kvm(env, SPR_PURR, "PURR",
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ KVM_REG_PPC_PURR, 0x00000000);
+ spr_register_kvm(env, SPR_SPURR, "SPURR",
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ KVM_REG_PPC_SPURR, 0x00000000);
spr_register(env, SPR_CFAR, "SPR_CFAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_cfar, &spr_write_cfar,
0x00000000);
- spr_register(env, SPR_DSCR, "SPR_DSCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DSCR, 0x00000000);
#endif /* !CONFIG_USER_ONLY */
/* Memory management */
/* XXX : not implemented */
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 58/66] target-ppc: Synchronize FPU state with KVM
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (56 preceding siblings ...)
2013-03-08 20:06 ` [Qemu-devel] [PATCH 57/66] target-ppc: Add mechanism for synchronizing SPRs with KVM Alexander Graf
@ 2013-03-08 20:07 ` Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 59/66] target-ppc: Fix PPC_DUMP_SPR_ACCESS build Alexander Graf
` (8 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:07 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Aurélien Jarno,
David Gibson
From: David Gibson <david@gibson.dropbear.id.au>
Currently qemu does not get and put the state of the floating point and
vector registers to KVM. This is obviously a problem for savevm, as well
as possibly being problematic for debugging of FP-using guests.
This patch fixes this by using new extensions to the ONE_REG interface to
synchronize the qemu floating point state with KVM.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/kvm.c | 130 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 130 insertions(+), 0 deletions(-)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 02ab559..4451159 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -521,6 +521,132 @@ static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
}
}
+static int kvm_put_fp(CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+ struct kvm_one_reg reg;
+ int i;
+ int ret;
+
+ if (env->insns_flags & PPC_FLOAT) {
+ uint64_t fpscr = env->fpscr;
+ bool vsx = !!(env->insns_flags2 & PPC2_VSX);
+
+ reg.id = KVM_REG_PPC_FPSCR;
+ reg.addr = (uintptr_t)&fpscr;
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
+ if (ret < 0) {
+ dprintf("Unable to set FPSCR to KVM: %s\n", strerror(errno));
+ return ret;
+ }
+
+ for (i = 0; i < 32; i++) {
+ uint64_t vsr[2];
+
+ vsr[0] = float64_val(env->fpr[i]);
+ vsr[1] = env->vsr[i];
+ reg.addr = (uintptr_t) &vsr;
+ reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
+
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
+ if (ret < 0) {
+ dprintf("Unable to set %s%d to KVM: %s\n", vsx ? "VSR" : "FPR",
+ i, strerror(errno));
+ return ret;
+ }
+ }
+ }
+
+ if (env->insns_flags & PPC_ALTIVEC) {
+ reg.id = KVM_REG_PPC_VSCR;
+ reg.addr = (uintptr_t)&env->vscr;
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
+ if (ret < 0) {
+ dprintf("Unable to set VSCR to KVM: %s\n", strerror(errno));
+ return ret;
+ }
+
+ for (i = 0; i < 32; i++) {
+ reg.id = KVM_REG_PPC_VR(i);
+ reg.addr = (uintptr_t)&env->avr[i];
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
+ if (ret < 0) {
+ dprintf("Unable to set VR%d to KVM: %s\n", i, strerror(errno));
+ return ret;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int kvm_get_fp(CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+ struct kvm_one_reg reg;
+ int i;
+ int ret;
+
+ if (env->insns_flags & PPC_FLOAT) {
+ uint64_t fpscr;
+ bool vsx = !!(env->insns_flags2 & PPC2_VSX);
+
+ reg.id = KVM_REG_PPC_FPSCR;
+ reg.addr = (uintptr_t)&fpscr;
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
+ if (ret < 0) {
+ dprintf("Unable to get FPSCR from KVM: %s\n", strerror(errno));
+ return ret;
+ } else {
+ env->fpscr = fpscr;
+ }
+
+ for (i = 0; i < 32; i++) {
+ uint64_t vsr[2];
+
+ reg.addr = (uintptr_t) &vsr;
+ reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
+
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
+ if (ret < 0) {
+ dprintf("Unable to get %s%d from KVM: %s\n",
+ vsx ? "VSR" : "FPR", i, strerror(errno));
+ return ret;
+ } else {
+ env->fpr[i] = vsr[0];
+ if (vsx) {
+ env->vsr[i] = vsr[1];
+ }
+ }
+ }
+ }
+
+ if (env->insns_flags & PPC_ALTIVEC) {
+ reg.id = KVM_REG_PPC_VSCR;
+ reg.addr = (uintptr_t)&env->vscr;
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
+ if (ret < 0) {
+ dprintf("Unable to get VSCR from KVM: %s\n", strerror(errno));
+ return ret;
+ }
+
+ for (i = 0; i < 32; i++) {
+ reg.id = KVM_REG_PPC_VR(i);
+ reg.addr = (uintptr_t)&env->avr[i];
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
+ if (ret < 0) {
+ dprintf("Unable to get VR%d from KVM: %s\n",
+ i, strerror(errno));
+ return ret;
+ }
+ }
+ }
+
+ return 0;
+}
+
int kvm_arch_put_registers(CPUState *cs, int level)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -561,6 +687,8 @@ int kvm_arch_put_registers(CPUState *cs, int level)
if (ret < 0)
return ret;
+ kvm_put_fp(cs);
+
if (env->tlb_dirty) {
kvm_sw_tlb_put(cpu);
env->tlb_dirty = false;
@@ -666,6 +794,8 @@ int kvm_arch_get_registers(CPUState *cs)
for (i = 0;i < 32; i++)
env->gpr[i] = regs.gpr[i];
+ kvm_get_fp(cs);
+
if (cap_booke_sregs) {
ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
if (ret < 0) {
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 59/66] target-ppc: Fix PPC_DUMP_SPR_ACCESS build
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (57 preceding siblings ...)
2013-03-08 20:07 ` [Qemu-devel] [PATCH 58/66] target-ppc: Synchronize FPU state " Alexander Graf
@ 2013-03-08 20:07 ` Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 60/66] PPC: Fix dma interrupt Alexander Graf
` (7 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:07 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
A victim of the d523dd00a7d73b28f2e99acf45a4b3f92e56e40a AREG0
conversion, insert the missing cpu_env arguments.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 7fb314c..1783c22 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -54,7 +54,7 @@ static void spr_load_dump_spr(int sprn)
{
#ifdef PPC_DUMP_SPR_ACCESSES
TCGv_i32 t0 = tcg_const_i32(sprn);
- gen_helper_load_dump_spr(t0);
+ gen_helper_load_dump_spr(cpu_env, t0);
tcg_temp_free_i32(t0);
#endif
}
@@ -69,7 +69,7 @@ static void spr_store_dump_spr(int sprn)
{
#ifdef PPC_DUMP_SPR_ACCESSES
TCGv_i32 t0 = tcg_const_i32(sprn);
- gen_helper_store_dump_spr(t0);
+ gen_helper_store_dump_spr(cpu_env, t0);
tcg_temp_free_i32(t0);
#endif
}
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 60/66] PPC: Fix dma interrupt
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (58 preceding siblings ...)
2013-03-08 20:07 ` [Qemu-devel] [PATCH 59/66] target-ppc: Fix PPC_DUMP_SPR_ACCESS build Alexander Graf
@ 2013-03-08 20:07 ` Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 61/66] PPC: xnu kernel expects FLUSH to be cleared on STOP Alexander Graf
` (6 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:07 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, Amadeusz Sławiński,
qemu-ppc@nongnu.org list:PowerPC, Aurélien Jarno
From: Amadeusz Sławiński <amade@asmblr.net>
In openbios (drivers/ide.c) they are set to
0000000d 00000000 00000002 00000000
0000000e 00000000 00000003 00000000
0000000f 00000000 00000004 00000000
(The last one seems to be not implemented in qemu)
It follows convention of how they are set on real machines,
both ide and dma ones are increased
Real machine one:
http://web.archive.org/web/20090107151044/http://penguinppc.org/historical/dev-trees-html/g4_agp_500_2.html
00000013 00000001 0000000b 00000000
00000014 00000001 0000000c 00000000
00000015 00000001 0000000d 00000000
Signed-off-by: Amadeusz Sławiński <amade@asmblr.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/mac_newworld.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 065ea87..a08a6b2 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -370,7 +370,7 @@ static void ppc_core99_init(QEMUMachineInitArgs *args)
qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */
qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */
qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */
- qdev_connect_gpio_out(dev, 4, pic[0x02]); /* IDE DMA */
+ qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */
macio_init(macio, pic_mem, escc_bar);
/* We only emulate 2 out of 3 IDE controllers for now */
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 61/66] PPC: xnu kernel expects FLUSH to be cleared on STOP
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (59 preceding siblings ...)
2013-03-08 20:07 ` [Qemu-devel] [PATCH 60/66] PPC: Fix dma interrupt Alexander Graf
@ 2013-03-08 20:07 ` Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 62/66] target-ppc: Make host CPU a subclass of the host's CPU model Alexander Graf
` (5 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:07 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, Amadeusz Sławiński,
qemu-ppc@nongnu.org list:PowerPC, Aurélien Jarno
From: Amadeusz Sławiński <amade@asmblr.net>
otherwise it gets stuck in a loop
so clear it when unsetting run when flush is set
void
IODBDMAStop( volatile IODBDMAChannelRegisters *registers)
{
IOSetDBDMAChannelControl( registers,
IOClearDBDMAChannelControlBits( kdbdmaRun )
| IOSetDBDMAChannelControlBits( kdbdmaFlush ));
DBDMA: writel 0x0000000000000b00 <= 0xa0002000
DBDMA: channel 0x16 reg 0x0
DBDMA: status 0x00002000
while( IOGetDBDMAChannelStatus( registers) & (
kdbdmaActive | kdbdmaFlush))
eieio();
DBDMA: readl 0x0000000000000b04 => 0x00002000
DBDMA: channel 0x16 reg 0x1
DBDMA: readl 0x0000000000000b04 => 0x00002000
DBDMA: channel 0x16 reg 0x1
DBDMA: readl 0x0000000000000b04 => 0x00002000
DBDMA: channel 0x16 reg 0x1
DBDMA: readl 0x0000000000000b04 => 0x00002000
DBDMA: channel 0x16 reg 0x1
it continues to get printed
}
Signed-off-by: Amadeusz Sławiński <amade@asmblr.net>
[agraf: replace tabs with spaces]
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/mac_dbdma.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/hw/mac_dbdma.c b/hw/mac_dbdma.c
index b894ab2..73d74c2 100644
--- a/hw/mac_dbdma.c
+++ b/hw/mac_dbdma.c
@@ -688,6 +688,10 @@ dbdma_control_write(DBDMA_channel *ch)
if ((ch->regs[DBDMA_STATUS] & RUN) && !(status & RUN)) {
/* RUN is cleared */
status &= ~(ACTIVE|DEAD);
+ if ((status & FLUSH) && ch->flush) {
+ ch->flush(&ch->io);
+ status &= ~FLUSH;
+ }
}
DBDMA_DPRINTF(" status 0x%08x\n", status);
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 62/66] target-ppc: Make host CPU a subclass of the host's CPU model
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (60 preceding siblings ...)
2013-03-08 20:07 ` [Qemu-devel] [PATCH 61/66] PPC: xnu kernel expects FLUSH to be cleared on STOP Alexander Graf
@ 2013-03-08 20:07 ` Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 63/66] target-ppc: List alias names alongside CPU models Alexander Graf
` (4 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:07 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
This avoids assigning individual class fields and contributors
forgetting to add field assignments in KVM-only code.
ppc_cpu_class_find_by_pvr() requires the CPU model classes to be
registered, so defer host CPU type registration to kvm_arch_init().
Only register the host CPU type if there is a class with matching PVR.
This lets us drop error handling from instance_init.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/kvm.c | 66 +++++++++++++++----------------------------
target-ppc/translate_init.c | 15 +++++----
2 files changed, 31 insertions(+), 50 deletions(-)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 4451159..9dff760 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -81,6 +81,8 @@ static void kvm_kick_cpu(void *opaque)
qemu_cpu_kick(CPU(cpu));
}
+static int kvm_ppc_register_host_cpu_type(void);
+
int kvm_arch_init(KVMState *s)
{
cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
@@ -98,6 +100,8 @@ int kvm_arch_init(KVMState *s)
"VM to stall at times!\n");
}
+ kvm_ppc_register_host_cpu_type();
+
return 0;
}
@@ -1488,44 +1492,15 @@ static void alter_insns(uint64_t *word, uint64_t flags, bool on)
static void kvmppc_host_cpu_initfn(Object *obj)
{
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj);
-
assert(kvm_enabled());
-
- if (pcc->pvr != mfpvr()) {
- fprintf(stderr, "Your host CPU is unsupported.\n"
- "Please choose a supported model instead, see -cpu ?.\n");
- exit(1);
- }
}
static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
{
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
- uint32_t host_pvr = mfpvr();
- PowerPCCPUClass *pvr_pcc;
uint32_t vmx = kvmppc_get_vmx();
uint32_t dfp = kvmppc_get_dfp();
- pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
- if (pvr_pcc != NULL) {
- pcc->pvr = pvr_pcc->pvr;
- pcc->svr = pvr_pcc->svr;
- pcc->insns_flags = pvr_pcc->insns_flags;
- pcc->insns_flags2 = pvr_pcc->insns_flags2;
- pcc->msr_mask = pvr_pcc->msr_mask;
- pcc->mmu_model = pvr_pcc->mmu_model;
- pcc->excp_model = pvr_pcc->excp_model;
- pcc->bus_model = pvr_pcc->bus_model;
- pcc->flags = pvr_pcc->flags;
- pcc->bfd_mach = pvr_pcc->bfd_mach;
-#ifdef TARGET_PPC64
- pcc->sps = pvr_pcc->sps;
-#endif
- pcc->init_proc = pvr_pcc->init_proc;
- pcc->check_pow = pvr_pcc->check_pow;
- }
-
/* Now fix up the class with information we can query from the host */
if (vmx != -1) {
@@ -1552,6 +1527,25 @@ int kvmppc_fixup_cpu(PowerPCCPU *cpu)
return 0;
}
+static int kvm_ppc_register_host_cpu_type(void)
+{
+ TypeInfo type_info = {
+ .name = TYPE_HOST_POWERPC_CPU,
+ .instance_init = kvmppc_host_cpu_initfn,
+ .class_init = kvmppc_host_cpu_class_init,
+ };
+ uint32_t host_pvr = mfpvr();
+ PowerPCCPUClass *pvr_pcc;
+
+ pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
+ if (pvr_pcc == NULL) {
+ return -1;
+ }
+ type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
+ type_register(&type_info);
+ return 0;
+}
+
bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
{
@@ -1567,17 +1561,3 @@ int kvm_arch_on_sigbus(int code, void *addr)
{
return 1;
}
-
-static const TypeInfo kvm_host_cpu_type_info = {
- .name = TYPE_HOST_POWERPC_CPU,
- .parent = TYPE_POWERPC_CPU,
- .instance_init = kvmppc_host_cpu_initfn,
- .class_init = kvmppc_host_cpu_class_init,
-};
-
-static void kvm_ppc_register_types(void)
-{
- type_register_static(&kvm_host_cpu_type_info);
-}
-
-type_init(kvm_ppc_register_types)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 1783c22..521cdcc 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8298,13 +8298,6 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name)
const char *p;
int i, len;
- if (strcasecmp(name, "host") == 0) {
- if (kvm_enabled()) {
- ret = object_class_by_name(TYPE_HOST_POWERPC_CPU);
- }
- return ret;
- }
-
/* Check if the given name is a PVR */
len = strlen(name);
if (len == 10 && name[0] == '0' && name[1] == 'x') {
@@ -8405,6 +8398,9 @@ static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
return;
}
#endif
+ if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
+ return;
+ }
name = g_strndup(typename,
strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
@@ -8427,6 +8423,11 @@ void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
g_slist_foreach(list, ppc_cpu_list_entry, &s);
g_slist_free(list);
+#ifdef CONFIG_KVM
+ cpu_fprintf(f, "\n");
+ cpu_fprintf(f, "PowerPC %-16s\n", "host");
+#endif
+
cpu_fprintf(f, "\n");
for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
ObjectClass *oc = ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 63/66] target-ppc: List alias names alongside CPU models
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (61 preceding siblings ...)
2013-03-08 20:07 ` [Qemu-devel] [PATCH 62/66] target-ppc: Make host CPU a subclass of the host's CPU model Alexander Graf
@ 2013-03-08 20:07 ` Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 64/66] target-ppc: Report CPU aliases for QMP Alexander Graf
` (3 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:07 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Revert adding a separate -cpu ? output section for aliases and list them
per CPU subclass.
Requested-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 23 +++++++++++------------
1 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 521cdcc..6fbb7b3 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8392,6 +8392,7 @@ static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
const char *typename = object_class_get_name(oc);
char *name;
+ int i;
#if defined(TARGET_PPCEMB)
if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
@@ -8406,6 +8407,16 @@ static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
(*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
name, pcc->pvr);
+ for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
+ const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
+ ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
+
+ if (alias_oc != oc) {
+ continue;
+ }
+ (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
+ alias->alias, name);
+ }
g_free(name);
}
@@ -8416,7 +8427,6 @@ void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
.cpu_fprintf = cpu_fprintf,
};
GSList *list;
- int i;
list = object_class_get_list(TYPE_POWERPC_CPU, false);
list = g_slist_sort(list, ppc_cpu_list_compare);
@@ -8427,17 +8437,6 @@ void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
cpu_fprintf(f, "\n");
cpu_fprintf(f, "PowerPC %-16s\n", "host");
#endif
-
- cpu_fprintf(f, "\n");
- for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
- ObjectClass *oc = ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
- if (oc == NULL) {
- /* Hide aliases that point to a TODO or TODO_USER_ONLY model */
- continue;
- }
- cpu_fprintf(f, "PowerPC %-16s\n",
- ppc_cpu_aliases[i].alias);
- }
}
static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 64/66] target-ppc: Report CPU aliases for QMP
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (62 preceding siblings ...)
2013-03-08 20:07 ` [Qemu-devel] [PATCH 63/66] target-ppc: List alias names alongside CPU models Alexander Graf
@ 2013-03-08 20:07 ` Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 65/66] target-ppc: Move CPU aliases out of translate_init.c Alexander Graf
` (2 subsequent siblings)
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:07 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
The QMP query-cpu-definitions implementation iterated over CPU classes
only, which were getting less and less as aliases were extracted.
Keep them in QMP as valid -cpu arguments even if not guaranteed stable.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 21 +++++++++++++++++++++
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6fbb7b3..8ce9f7a 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8469,11 +8469,32 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
{
CpuDefinitionInfoList *cpu_list = NULL;
GSList *list;
+ int i;
list = object_class_get_list(TYPE_POWERPC_CPU, false);
g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
g_slist_free(list);
+ for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
+ const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
+ ObjectClass *oc;
+ CpuDefinitionInfoList *entry;
+ CpuDefinitionInfo *info;
+
+ oc = ppc_cpu_class_by_name(alias->model);
+ if (oc == NULL) {
+ continue;
+ }
+
+ info = g_malloc0(sizeof(*info));
+ info->name = g_strdup(alias->alias);
+
+ entry = g_malloc0(sizeof(*entry));
+ entry->value = info;
+ entry->next = cpu_list;
+ cpu_list = entry;
+ }
+
return cpu_list;
}
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 65/66] target-ppc: Move CPU aliases out of translate_init.c
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (63 preceding siblings ...)
2013-03-08 20:07 ` [Qemu-devel] [PATCH 64/66] target-ppc: Report CPU aliases for QMP Alexander Graf
@ 2013-03-08 20:07 ` Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 66/66] pseries: Add compatible property to root of device tree Alexander Graf
2013-03-09 12:09 ` [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Blue Swirl
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:07 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, Andreas Färber,
Aurélien Jarno
From: Andreas Färber <afaerber@suse.de>
Move array of CPU aliases to cpu-models.c, alongside model definitions.
This requires to zero-terminate the aliases array since ARRAY_SIZE() can
no longer be used in translate_init.c then.
Suggested-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/cpu-models.c | 194 +++++++++++++++++++++++++++++++++++++++++
target-ppc/cpu-models.h | 14 +++
target-ppc/translate_init.c | 201 +------------------------------------------
3 files changed, 211 insertions(+), 198 deletions(-)
diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index 66408c0..20ca84e 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -1223,3 +1223,197 @@
"PA PA6T")
#endif
+
+/***************************************************************************/
+/* PowerPC CPU aliases */
+
+const PowerPCCPUAlias ppc_cpu_aliases[] = {
+ { "403", "403GC" },
+ { "405", "405D4" },
+ { "405CR", "405CRc" },
+ { "405GP", "405GPd" },
+ { "405GPe", "405CRc" },
+ { "x2vp7", "x2vp4" },
+ { "x2vp50", "x2vp20" },
+
+ { "440EP", "440EPb" },
+ { "440GP", "440GPc" },
+ { "440GR", "440GRa" },
+ { "440GX", "440GXf" },
+
+ { "RCPU", "MPC5xx" },
+ /* MPC5xx microcontrollers */
+ { "MGT560", "MPC5xx" },
+ { "MPC509", "MPC5xx" },
+ { "MPC533", "MPC5xx" },
+ { "MPC534", "MPC5xx" },
+ { "MPC555", "MPC5xx" },
+ { "MPC556", "MPC5xx" },
+ { "MPC560", "MPC5xx" },
+ { "MPC561", "MPC5xx" },
+ { "MPC562", "MPC5xx" },
+ { "MPC563", "MPC5xx" },
+ { "MPC564", "MPC5xx" },
+ { "MPC565", "MPC5xx" },
+ { "MPC566", "MPC5xx" },
+
+ { "PowerQUICC", "MPC8xx" },
+ /* MPC8xx microcontrollers */
+ { "MGT823", "MPC8xx" },
+ { "MPC821", "MPC8xx" },
+ { "MPC823", "MPC8xx" },
+ { "MPC850", "MPC8xx" },
+ { "MPC852T", "MPC8xx" },
+ { "MPC855T", "MPC8xx" },
+ { "MPC857", "MPC8xx" },
+ { "MPC859", "MPC8xx" },
+ { "MPC860", "MPC8xx" },
+ { "MPC862", "MPC8xx" },
+ { "MPC866", "MPC8xx" },
+ { "MPC870", "MPC8xx" },
+ { "MPC875", "MPC8xx" },
+ { "MPC880", "MPC8xx" },
+ { "MPC885", "MPC8xx" },
+
+ /* PowerPC MPC603 microcontrollers */
+ { "MPC8240", "603" },
+
+ { "MPC52xx", "MPC5200" },
+ { "MPC5200", "MPC5200_v12" },
+ { "MPC5200B", "MPC5200B_v21" },
+
+ { "MPC82xx", "MPC8280" },
+ { "PowerQUICC-II", "MPC82xx" },
+ { "MPC8241", "G2HiP4" },
+ { "MPC8245", "G2HiP4" },
+ { "MPC8247", "G2leGP3" },
+ { "MPC8248", "G2leGP3" },
+ { "MPC8250", "MPC8250_HiP4" },
+ { "MPC8250_HiP3", "G2HiP3" },
+ { "MPC8250_HiP4", "G2HiP4" },
+ { "MPC8255", "MPC8255_HiP4" },
+ { "MPC8255_HiP3", "G2HiP3" },
+ { "MPC8255_HiP4", "G2HiP4" },
+ { "MPC8260", "MPC8260_HiP4" },
+ { "MPC8260_HiP3", "G2HiP3" },
+ { "MPC8260_HiP4", "G2HiP4" },
+ { "MPC8264", "MPC8264_HiP4" },
+ { "MPC8264_HiP3", "G2HiP3" },
+ { "MPC8264_HiP4", "G2HiP4" },
+ { "MPC8265", "MPC8265_HiP4" },
+ { "MPC8265_HiP3", "G2HiP3" },
+ { "MPC8265_HiP4", "G2HiP4" },
+ { "MPC8266", "MPC8266_HiP4" },
+ { "MPC8266_HiP3", "G2HiP3" },
+ { "MPC8266_HiP4", "G2HiP4" },
+ { "MPC8270", "G2leGP3" },
+ { "MPC8271", "G2leGP3" },
+ { "MPC8272", "G2leGP3" },
+ { "MPC8275", "G2leGP3" },
+ { "MPC8280", "G2leGP3" },
+ { "e200", "e200z6" },
+ { "e300", "e300c3" },
+ { "MPC8347", "MPC8347T" },
+ { "MPC8347A", "MPC8347AT" },
+ { "MPC8347E", "MPC8347ET" },
+ { "MPC8347EA", "MPC8347EAT" },
+ { "e500", "e500v2_v22" },
+ { "e500v1", "e500_v20" },
+ { "e500v2", "e500v2_v22" },
+ { "MPC8533", "MPC8533_v11" },
+ { "MPC8533E", "MPC8533E_v11" },
+ { "MPC8540", "MPC8540_v21" },
+ { "MPC8541", "MPC8541_v11" },
+ { "MPC8541E", "MPC8541E_v11" },
+ { "MPC8543", "MPC8543_v21" },
+ { "MPC8543E", "MPC8543E_v21" },
+ { "MPC8544", "MPC8544_v11" },
+ { "MPC8544E", "MPC8544E_v11" },
+ { "MPC8545", "MPC8545_v21" },
+ { "MPC8545E", "MPC8545E_v21" },
+ { "MPC8547E", "MPC8547E_v21" },
+ { "MPC8548", "MPC8548_v21" },
+ { "MPC8548E", "MPC8548E_v21" },
+ { "MPC8555", "MPC8555_v11" },
+ { "MPC8555E", "MPC8555E_v11" },
+ { "MPC8560", "MPC8560_v21" },
+ { "601", "601_v2" },
+ { "601v", "601_v2" },
+ { "Vanilla", "603" },
+ { "603e", "603e_v4.1" },
+ { "Stretch", "603e" },
+ { "Vaillant", "603e7v" },
+ { "603r", "603e7t" },
+ { "Goldeneye", "603r" },
+ { "604e", "604e_v2.4" },
+ { "Sirocco", "604e" },
+ { "Mach5", "604r" },
+ { "740", "740_v3.1" },
+ { "Arthur", "740" },
+ { "750", "750_v3.1" },
+ { "Typhoon", "750" },
+ { "G3", "750" },
+ { "Conan/Doyle", "750p" },
+ { "750cl", "750cl_v2.0" },
+ { "750cx", "750cx_v2.2" },
+ { "750cxe", "750cxe_v3.1b" },
+ { "750fx", "750fx_v2.3" },
+ { "750gx", "750gx_v1.2" },
+ { "750l", "750l_v3.2" },
+ { "LoneStar", "750l" },
+ { "745", "745_v2.8" },
+ { "755", "755_v2.8" },
+ { "Goldfinger", "755" },
+ { "7400", "7400_v2.9" },
+ { "Max", "7400" },
+ { "G4", "7400" },
+ { "7410", "7410_v1.4" },
+ { "Nitro", "7410" },
+ { "7448", "7448_v2.1" },
+ { "7450", "7450_v2.1" },
+ { "Vger", "7450" },
+ { "7441", "7441_v2.3" },
+ { "7451", "7451_v2.3" },
+ { "7445", "7445_v3.2" },
+ { "7455", "7455_v3.2" },
+ { "Apollo6", "7455" },
+ { "7447", "7447_v1.2" },
+ { "7457", "7457_v1.2" },
+ { "Apollo7", "7457" },
+ { "7447A", "7447A_v1.2" },
+ { "7457A", "7457A_v1.2" },
+ { "Apollo7PM", "7457A_v1.0" },
+#if defined(TARGET_PPC64)
+ { "Trident", "620" },
+ { "POWER3", "630" },
+ { "Boxer", "POWER3" },
+ { "Dino", "POWER3" },
+ { "POWER3+", "631" },
+ { "POWER7", "POWER7_v2.3" },
+ { "970fx", "970fx_v3.1" },
+ { "970mp", "970mp_v1.1" },
+ { "Apache", "RS64" },
+ { "A35", "RS64" },
+ { "NorthStar", "RS64-II" },
+ { "A50", "RS64-II" },
+ { "Pulsar", "RS64-III" },
+ { "IceStar", "RS64-IV" },
+ { "IStar", "RS64-IV" },
+ { "SStar", "RS64-IV" },
+#endif
+ { "RIOS", "POWER" },
+ { "RSC", "POWER" },
+ { "RSC3308", "POWER" },
+ { "RSC4608", "POWER" },
+ { "RSC2", "POWER2" },
+ { "P2SC", "POWER2" },
+
+ /* Generic PowerPCs */
+#if defined(TARGET_PPC64)
+ { "ppc64", "970fx" },
+#endif
+ { "ppc32", "604" },
+ { "ppc", "ppc32" },
+ { "default", "ppc" },
+ { NULL, NULL }
+};
diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
index edff0f4..a94f835 100644
--- a/target-ppc/cpu-models.h
+++ b/target-ppc/cpu-models.h
@@ -21,6 +21,20 @@
#ifndef TARGET_PPC_CPU_MODELS_H
#define TARGET_PPC_CPU_MODELS_H
+/**
+ * PowerPCCPUAlias:
+ * @alias: The alias name.
+ * @model: The CPU model @alias refers to.
+ *
+ * A mapping entry from CPU @alias to CPU @model.
+ */
+typedef struct PowerPCCPUAlias {
+ const char *alias;
+ const char *model;
+} PowerPCCPUAlias;
+
+extern const PowerPCCPUAlias ppc_cpu_aliases[];
+
/*****************************************************************************/
/* PVR definitions for most known PowerPC */
enum {
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 8ce9f7a..09ad4ba 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7181,201 +7181,6 @@ POWERPC_FAMILY(620)(ObjectClass *oc, void *data)
#endif /* defined (TARGET_PPC64) */
-typedef struct PowerPCCPUAlias {
- const char *alias;
- const char *model;
-} PowerPCCPUAlias;
-
-static const PowerPCCPUAlias ppc_cpu_aliases[] = {
- { "403", "403GC" },
- { "405", "405D4" },
- { "405CR", "405CRc" },
- { "405GP", "405GPd" },
- { "405GPe", "405CRc" },
- { "x2vp7", "x2vp4" },
- { "x2vp50", "x2vp20" },
-
- { "440EP", "440EPb" },
- { "440GP", "440GPc" },
- { "440GR", "440GRa" },
- { "440GX", "440GXf" },
-
- { "RCPU", "MPC5xx" },
- /* MPC5xx microcontrollers */
- { "MGT560", "MPC5xx" },
- { "MPC509", "MPC5xx" },
- { "MPC533", "MPC5xx" },
- { "MPC534", "MPC5xx" },
- { "MPC555", "MPC5xx" },
- { "MPC556", "MPC5xx" },
- { "MPC560", "MPC5xx" },
- { "MPC561", "MPC5xx" },
- { "MPC562", "MPC5xx" },
- { "MPC563", "MPC5xx" },
- { "MPC564", "MPC5xx" },
- { "MPC565", "MPC5xx" },
- { "MPC566", "MPC5xx" },
-
- { "PowerQUICC", "MPC8xx" },
- /* MPC8xx microcontrollers */
- { "MGT823", "MPC8xx" },
- { "MPC821", "MPC8xx" },
- { "MPC823", "MPC8xx" },
- { "MPC850", "MPC8xx" },
- { "MPC852T", "MPC8xx" },
- { "MPC855T", "MPC8xx" },
- { "MPC857", "MPC8xx" },
- { "MPC859", "MPC8xx" },
- { "MPC860", "MPC8xx" },
- { "MPC862", "MPC8xx" },
- { "MPC866", "MPC8xx" },
- { "MPC870", "MPC8xx" },
- { "MPC875", "MPC8xx" },
- { "MPC880", "MPC8xx" },
- { "MPC885", "MPC8xx" },
-
- /* PowerPC MPC603 microcontrollers */
- { "MPC8240", "603" },
-
- { "MPC52xx", "MPC5200" },
- { "MPC5200", "MPC5200_v12" },
- { "MPC5200B", "MPC5200B_v21" },
-
- { "MPC82xx", "MPC8280" },
- { "PowerQUICC-II", "MPC82xx" },
- { "MPC8241", "G2HiP4" },
- { "MPC8245", "G2HiP4" },
- { "MPC8247", "G2leGP3" },
- { "MPC8248", "G2leGP3" },
- { "MPC8250", "MPC8250_HiP4" },
- { "MPC8250_HiP3", "G2HiP3" },
- { "MPC8250_HiP4", "G2HiP4" },
- { "MPC8255", "MPC8255_HiP4" },
- { "MPC8255_HiP3", "G2HiP3" },
- { "MPC8255_HiP4", "G2HiP4" },
- { "MPC8260", "MPC8260_HiP4" },
- { "MPC8260_HiP3", "G2HiP3" },
- { "MPC8260_HiP4", "G2HiP4" },
- { "MPC8264", "MPC8264_HiP4" },
- { "MPC8264_HiP3", "G2HiP3" },
- { "MPC8264_HiP4", "G2HiP4" },
- { "MPC8265", "MPC8265_HiP4" },
- { "MPC8265_HiP3", "G2HiP3" },
- { "MPC8265_HiP4", "G2HiP4" },
- { "MPC8266", "MPC8266_HiP4" },
- { "MPC8266_HiP3", "G2HiP3" },
- { "MPC8266_HiP4", "G2HiP4" },
- { "MPC8270", "G2leGP3" },
- { "MPC8271", "G2leGP3" },
- { "MPC8272", "G2leGP3" },
- { "MPC8275", "G2leGP3" },
- { "MPC8280", "G2leGP3" },
- { "e200", "e200z6" },
- { "e300", "e300c3" },
- { "MPC8347", "MPC8347T" },
- { "MPC8347A", "MPC8347AT" },
- { "MPC8347E", "MPC8347ET" },
- { "MPC8347EA", "MPC8347EAT" },
- { "e500", "e500v2_v22" },
- { "e500v1", "e500_v20" },
- { "e500v2", "e500v2_v22" },
- { "MPC8533", "MPC8533_v11" },
- { "MPC8533E", "MPC8533E_v11" },
- { "MPC8540", "MPC8540_v21" },
- { "MPC8541", "MPC8541_v11" },
- { "MPC8541E", "MPC8541E_v11" },
- { "MPC8543", "MPC8543_v21" },
- { "MPC8543E", "MPC8543E_v21" },
- { "MPC8544", "MPC8544_v11" },
- { "MPC8544E", "MPC8544E_v11" },
- { "MPC8545", "MPC8545_v21" },
- { "MPC8545E", "MPC8545E_v21" },
- { "MPC8547E", "MPC8547E_v21" },
- { "MPC8548", "MPC8548_v21" },
- { "MPC8548E", "MPC8548E_v21" },
- { "MPC8555", "MPC8555_v11" },
- { "MPC8555E", "MPC8555E_v11" },
- { "MPC8560", "MPC8560_v21" },
- { "601", "601_v2" },
- { "601v", "601_v2" },
- { "Vanilla", "603" },
- { "603e", "603e_v4.1" },
- { "Stretch", "603e" },
- { "Vaillant", "603e7v" },
- { "603r", "603e7t" },
- { "Goldeneye", "603r" },
- { "604e", "604e_v2.4" },
- { "Sirocco", "604e" },
- { "Mach5", "604r" },
- { "740", "740_v3.1" },
- { "Arthur", "740" },
- { "750", "750_v3.1" },
- { "Typhoon", "750" },
- { "G3", "750" },
- { "Conan/Doyle", "750p" },
- { "750cl", "750cl_v2.0" },
- { "750cx", "750cx_v2.2" },
- { "750cxe", "750cxe_v3.1b" },
- { "750fx", "750fx_v2.3" },
- { "750gx", "750gx_v1.2" },
- { "750l", "750l_v3.2" },
- { "LoneStar", "750l" },
- { "745", "745_v2.8" },
- { "755", "755_v2.8" },
- { "Goldfinger", "755" },
- { "7400", "7400_v2.9" },
- { "Max", "7400" },
- { "G4", "7400" },
- { "7410", "7410_v1.4" },
- { "Nitro", "7410" },
- { "7448", "7448_v2.1" },
- { "7450", "7450_v2.1" },
- { "Vger", "7450" },
- { "7441", "7441_v2.3" },
- { "7451", "7451_v2.3" },
- { "7445", "7445_v3.2" },
- { "7455", "7455_v3.2" },
- { "Apollo6", "7455" },
- { "7447", "7447_v1.2" },
- { "7457", "7457_v1.2" },
- { "Apollo7", "7457" },
- { "7447A", "7447A_v1.2" },
- { "7457A", "7457A_v1.2" },
- { "Apollo7PM", "7457A_v1.0" },
-#if defined(TARGET_PPC64)
- { "Trident", "620" },
- { "POWER3", "630" },
- { "Boxer", "POWER3" },
- { "Dino", "POWER3" },
- { "POWER3+", "631" },
- { "POWER7", "POWER7_v2.3" },
- { "970fx", "970fx_v3.1" },
- { "970mp", "970mp_v1.1" },
- { "Apache", "RS64" },
- { "A35", "RS64" },
- { "NorthStar", "RS64-II" },
- { "A50", "RS64-II" },
- { "Pulsar", "RS64-III" },
- { "IceStar", "RS64-IV" },
- { "IStar", "RS64-IV" },
- { "SStar", "RS64-IV" },
-#endif
- { "RIOS", "POWER" },
- { "RSC", "POWER" },
- { "RSC3308", "POWER" },
- { "RSC4608", "POWER" },
- { "RSC2", "POWER2" },
- { "P2SC", "POWER2" },
-
- /* Generic PowerPCs */
-#if defined(TARGET_PPC64)
- { "ppc64", "970fx" },
-#endif
- { "ppc32", "604" },
- { "ppc", "ppc32" },
- { "default", "ppc" },
-};
-
/*****************************************************************************/
/* Generic CPU instantiation routine */
static void init_ppc_proc(PowerPCCPU *cpu)
@@ -8316,7 +8121,7 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name)
}
}
- for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
+ for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
}
@@ -8407,7 +8212,7 @@ static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
(*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
name, pcc->pvr);
- for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
+ for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
@@ -8475,7 +8280,7 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
g_slist_free(list);
- for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
+ for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
ObjectClass *oc;
CpuDefinitionInfoList *entry;
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 66/66] pseries: Add compatible property to root of device tree
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (64 preceding siblings ...)
2013-03-08 20:07 ` [Qemu-devel] [PATCH 65/66] target-ppc: Move CPU aliases out of translate_init.c Alexander Graf
@ 2013-03-08 20:07 ` Alexander Graf
2013-03-09 12:09 ` [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Blue Swirl
66 siblings, 0 replies; 68+ messages in thread
From: Alexander Graf @ 2013-03-08 20:07 UTC (permalink / raw)
To: qemu-devel qemu-devel
Cc: Blue Swirl, qemu-ppc@nongnu.org list:PowerPC, qemu-stable,
Aurélien Jarno, David Gibson
From: David Gibson <david@gibson.dropbear.id.au>
Currently, for the pseries machine the device tree supplied by qemu to SLOF
and from there to the guest does not include a 'compatible property' at the
root level. Usually that works fine, since in this case the compatible
property doesn't really give any information not already found in the
'device_type' or 'model' properties.
However, the lack of 'compatible' confuses the bootloader install in the
SLES11 SP2 and SLES11 SP3 installers. This patch therefore adds a token
'compatible' property to work around that.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-stable@nongnu.org
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/spapr.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/spapr.c b/hw/spapr.c
index e88a27a..fadf70f 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -260,6 +260,7 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
_FDT((fdt_begin_node(fdt, "")));
_FDT((fdt_property_string(fdt, "device_type", "chrp")));
_FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
+ _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
_FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
_FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
--
1.6.0.2
^ permalink raw reply related [flat|nested] 68+ messages in thread
* Re: [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
` (65 preceding siblings ...)
2013-03-08 20:07 ` [Qemu-devel] [PATCH 66/66] pseries: Add compatible property to root of device tree Alexander Graf
@ 2013-03-09 12:09 ` Blue Swirl
66 siblings, 0 replies; 68+ messages in thread
From: Blue Swirl @ 2013-03-09 12:09 UTC (permalink / raw)
To: Alexander Graf
Cc: qemu-ppc@nongnu.org list:PowerPC, qemu-devel qemu-devel,
Aurélien Jarno
On Fri, Mar 8, 2013 at 8:06 PM, Alexander Graf <agraf@suse.de> wrote:
> Hi Blue / Aurelien,
>
> This is my current patch queue for ppc. Please pull.
Thanks, pulled.
>
> Alex
>
>
> The following changes since commit 0bc472a9d6b80567c212023c5eae413f4dfb53ad:
> Kuo-Jung Su (1):
> hw/nand.c: correct the sense of the BUSY/READY status bit
>
> are available in the git repository at:
>
> git://github.com/agraf/qemu.git ppc-for-upstream
>
> Amadeusz Sławiński (2):
> PPC: Fix dma interrupt
> PPC: xnu kernel expects FLUSH to be cleared on STOP
>
> Andreas Färber (58):
> target-ppc: Fix CPU_POWERPC_MPC8547E
> target-ppc: Fix "G2leGP3" PVR
> target-ppc: Update error handling in ppc_cpu_realize()
> target-ppc: Drop nested TARGET_PPC64 guard for POWER7
> target-ppc: Inline comma into POWERPC_DEF_SVR() macro
> target-ppc: Extract aliases from definitions list
> target-ppc: Make -cpu "ppc" an alias to "ppc32"
> target-ppc: Extract MPC5xx aliases
> target-ppc: Extract MGT823/MPC8xx as aliases
> target-ppc: Extract 40x aliases
> target-ppc: Extract 440 aliases
> target-ppc: Turn "ppc32" and "ppc64" CPUs into aliases
> target-ppc: Extract 74x7[A] aliases
> target-ppc: Extract 74x5 as aliases
> target-ppc: Extract 74x1 aliases
> target-ppc: Extract 7450 alias
> target-ppc: Extract 7448 alias
> target-ppc: Extract 7410 alias
> target-ppc: Extract 7400 alias
> target-ppc: Extract 7x5 aliases
> target-ppc: Extract 750 aliases
> target-ppc: Extract 740/750 aliases
> target-ppc: Extract 603e alias
> target-ppc: Extract 603r alias
> target-ppc: Extract 601/601v aliases
> target-ppc: Extract 604e alias
> target-ppc: Extract MPC85xx aliases
> target-ppc: Extract e500v1/e500v2 aliases
> target-ppc: Extract MPC83xx aliases
> target-ppc: Extract e300 alias
> target-ppc: Extract e200 alias
> target-ppc: Extract MPC82xx alias
> target-ppc: Extract MPC8247/MPC8248/MPC8270-80 aliases
> target-ppc: Extract MPC82xx aliases to *_HiP4
> target-ppc: Extract MPC82xx_HiP{3, 4} aliases
> target-ppc: Extract MPC52xx alias
> target-ppc: Extract MPC5200/MPC5200B aliases
> target-ppc: Extract MPC8240 alias
> target-ppc: Extract 405GPe alias
> target-ppc: Extract 970 aliases
> target-ppc: Extract POWER7 alias
> target-ppc: Get model name from type name
> target-ppc: Convert CPU definitions
> target-ppc: Introduce abstract CPU family types
> target-ppc: Set instruction flags on CPU family classes
> target-ppc: Register all types for TARGET_PPCEMB
> target-ppc: Set remaining fields on CPU family classes
> target-ppc: Turn descriptive CPU family comments into device descriptions
> target-ppc: Turn descriptive CPU model comments into device descriptions
> target-ppc: Update Coding Style for CPU models
> target-ppc: Split model definitions out of translate_init.c
> target-ppc: Fix remaining microcontroller typos among models
> target-ppc: Change "POWER7" CPU alias
> target-ppc: Fix PPC_DUMP_SPR_ACCESS build
> target-ppc: Make host CPU a subclass of the host's CPU model
> target-ppc: List alias names alongside CPU models
> target-ppc: Report CPU aliases for QMP
> target-ppc: Move CPU aliases out of translate_init.c
>
> David Gibson (4):
> pseries: Add cleanup hook for PAPR virtual LAN device
> target-ppc: Add mechanism for synchronizing SPRs with KVM
> target-ppc: Synchronize FPU state with KVM
> pseries: Add compatible property to root of device tree
>
> Erlon Cruz (1):
> pseries: Implement h_read hcall
>
> Fabien Chouteau (1):
> Save memory allocation in the elf loader
>
> hw/elf_ops.h | 19 +-
> hw/loader.c | 75 +-
> hw/loader.h | 2 +
> hw/mac_dbdma.c | 4 +
> hw/ppc/mac_newworld.c | 2 +-
> hw/spapr.c | 1 +
> hw/spapr_hcall.c | 31 +
> hw/spapr_llan.c | 8 +
> target-ppc/Makefile.objs | 1 +
> target-ppc/cpu-models.c | 1419 ++++++++++++
> target-ppc/cpu-models.h | 741 ++++++
> target-ppc/cpu-qom.h | 17 +-
> target-ppc/cpu.h | 26 +-
> target-ppc/kvm.c | 311 +++-
> target-ppc/translate_init.c | 5275 +++++++++++++------------------------------
> 15 files changed, 4117 insertions(+), 3815 deletions(-)
> create mode 100644 target-ppc/cpu-models.c
> create mode 100644 target-ppc/cpu-models.h
^ permalink raw reply [flat|nested] 68+ messages in thread
end of thread, other threads:[~2013-03-09 12:10 UTC | newest]
Thread overview: 68+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-03-08 20:06 [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 01/66] pseries: Add cleanup hook for PAPR virtual LAN device Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 02/66] target-ppc: Fix CPU_POWERPC_MPC8547E Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 03/66] target-ppc: Fix "G2leGP3" PVR Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 04/66] target-ppc: Update error handling in ppc_cpu_realize() Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 05/66] target-ppc: Drop nested TARGET_PPC64 guard for POWER7 Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 06/66] target-ppc: Inline comma into POWERPC_DEF_SVR() macro Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 07/66] target-ppc: Extract aliases from definitions list Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 08/66] target-ppc: Make -cpu "ppc" an alias to "ppc32" Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 09/66] target-ppc: Extract MPC5xx aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 10/66] target-ppc: Extract MGT823/MPC8xx as aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 11/66] target-ppc: Extract 40x aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 12/66] target-ppc: Extract 440 aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 13/66] target-ppc: Turn "ppc32" and "ppc64" CPUs into aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 14/66] target-ppc: Extract 74x7[A] aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 15/66] target-ppc: Extract 74x5 as aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 16/66] target-ppc: Extract 74x1 aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 17/66] target-ppc: Extract 7450 alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 18/66] target-ppc: Extract 7448 alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 19/66] target-ppc: Extract 7410 alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 20/66] target-ppc: Extract 7400 alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 21/66] target-ppc: Extract 7x5 aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 22/66] target-ppc: Extract 750 aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 23/66] target-ppc: Extract 740/750 aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 24/66] target-ppc: Extract 603e alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 25/66] target-ppc: Extract 603r alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 26/66] target-ppc: Extract 601/601v aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 27/66] target-ppc: Extract 604e alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 28/66] target-ppc: Extract MPC85xx aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 29/66] target-ppc: Extract e500v1/e500v2 aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 30/66] target-ppc: Extract MPC83xx aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 31/66] target-ppc: Extract e300 alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 32/66] target-ppc: Extract e200 alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 33/66] target-ppc: Extract MPC82xx alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 34/66] target-ppc: Extract MPC8247/MPC8248/MPC8270-80 aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 35/66] target-ppc: Extract MPC82xx aliases to *_HiP4 Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 36/66] target-ppc: Extract MPC82xx_HiP{3, 4} aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 37/66] target-ppc: Extract MPC52xx alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 38/66] target-ppc: Extract MPC5200/MPC5200B aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 39/66] target-ppc: Extract MPC8240 alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 40/66] target-ppc: Extract 405GPe alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 41/66] target-ppc: Extract 970 aliases Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 42/66] target-ppc: Extract POWER7 alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 43/66] target-ppc: Get model name from type name Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 44/66] target-ppc: Convert CPU definitions Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 45/66] target-ppc: Introduce abstract CPU family types Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 46/66] target-ppc: Set instruction flags on CPU family classes Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 47/66] target-ppc: Register all types for TARGET_PPCEMB Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 48/66] target-ppc: Set remaining fields on CPU family classes Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 49/66] target-ppc: Turn descriptive CPU family comments into device descriptions Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 50/66] target-ppc: Turn descriptive CPU model " Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 51/66] target-ppc: Update Coding Style for CPU models Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 52/66] target-ppc: Split model definitions out of translate_init.c Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 53/66] target-ppc: Fix remaining microcontroller typos among models Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 54/66] target-ppc: Change "POWER7" CPU alias Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 55/66] pseries: Implement h_read hcall Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 56/66] Save memory allocation in the elf loader Alexander Graf
2013-03-08 20:06 ` [Qemu-devel] [PATCH 57/66] target-ppc: Add mechanism for synchronizing SPRs with KVM Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 58/66] target-ppc: Synchronize FPU state " Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 59/66] target-ppc: Fix PPC_DUMP_SPR_ACCESS build Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 60/66] PPC: Fix dma interrupt Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 61/66] PPC: xnu kernel expects FLUSH to be cleared on STOP Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 62/66] target-ppc: Make host CPU a subclass of the host's CPU model Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 63/66] target-ppc: List alias names alongside CPU models Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 64/66] target-ppc: Report CPU aliases for QMP Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 65/66] target-ppc: Move CPU aliases out of translate_init.c Alexander Graf
2013-03-08 20:07 ` [Qemu-devel] [PATCH 66/66] pseries: Add compatible property to root of device tree Alexander Graf
2013-03-09 12:09 ` [Qemu-devel] [PULL 00/66] ppc patch queue 2013-03-08 Blue Swirl
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