From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:48858) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UE3at-0000ew-26 for qemu-devel@nongnu.org; Fri, 08 Mar 2013 15:09:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UE3a8-0000dj-OI for qemu-devel@nongnu.org; Fri, 08 Mar 2013 15:08:42 -0500 From: Alexander Graf Date: Fri, 8 Mar 2013 21:06:54 +0100 Message-Id: <1362773228-1747-53-git-send-email-agraf@suse.de> In-Reply-To: <1362773228-1747-1-git-send-email-agraf@suse.de> References: <1362773228-1747-1-git-send-email-agraf@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 52/66] target-ppc: Split model definitions out of translate_init.c List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel qemu-devel Cc: Blue Swirl , "qemu-ppc@nongnu.org list:PowerPC" , =?utf-8?q?Andreas=20F=C3=A4rber?= , =?utf-8?q?Aur=C3=A9lien=20Jarno?= From: Andreas F=C3=A4rber Now that model definitions only reference their parent type, model definitions are independent of the family definitions and can be compiled independently of TCG translation. Keep all #if defined(TODO) code local to cpu-models.c. Signed-off-by: Andreas F=C3=A4rber Signed-off-by: Alexander Graf --- target-ppc/Makefile.objs | 1 + target-ppc/cpu-models.c | 1225 +++++++++++++++++++++++++++ target-ppc/cpu-models.h | 727 ++++++++++++++++ target-ppc/translate_init.c | 1907 +------------------------------------= ------ 4 files changed, 1955 insertions(+), 1905 deletions(-) create mode 100644 target-ppc/cpu-models.c create mode 100644 target-ppc/cpu-models.h diff --git a/target-ppc/Makefile.objs b/target-ppc/Makefile.objs index a028dcd..00ac4ad 100644 --- a/target-ppc/Makefile.objs +++ b/target-ppc/Makefile.objs @@ -1,3 +1,4 @@ +obj-y +=3D cpu-models.o obj-y +=3D translate.o obj-$(CONFIG_SOFTMMU) +=3D machine.o obj-$(CONFIG_KVM) +=3D kvm.o kvm_ppc.o diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c new file mode 100644 index 0000000..f0be585 --- /dev/null +++ b/target-ppc/cpu-models.c @@ -0,0 +1,1225 @@ +/* + * PowerPC CPU initialization for qemu. + * + * Copyright (c) 2003-2007 Jocelyn Mayer + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* A lot of PowerPC definition have been included here. + * Most of them are not usable for now but have been kept + * inside "#if defined(TODO) ... #endif" statements to make tests easier= . + */ + +#include "cpu.h" +#include "cpu-models.h" + +#if defined(CONFIG_USER_ONLY) +#define TODO_USER_ONLY 1 +#endif + +/***********************************************************************= ****/ +/* PowerPC CPU definitions = */ +#define POWERPC_DEF_PREFIX(pvr, svr, type) = \ + glue(glue(glue(glue(pvr, _), svr), _), type) +#define POWERPC_DEF_SVR(_name, _desc, _pvr, _svr, _type) = \ + static void = \ + glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init) = \ + (ObjectClass *oc, void *data) = \ + { = \ + DeviceClass *dc =3D DEVICE_CLASS(oc); = \ + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); = \ + = \ + pcc->pvr =3D _pvr; = \ + pcc->svr =3D _svr; = \ + dc->desc =3D _desc; = \ + } = \ + = \ + static const TypeInfo = \ + glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info) =3D { = \ + .name =3D _name "-" TYPE_POWERPC_CPU, = \ + .parent =3D stringify(_type) "-family-" TYPE_POWERPC_CPU, = \ + .class_init =3D = \ + glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init)= , \ + }; = \ + = \ + static void = \ + glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types)(voi= d) \ + { = \ + type_register_static( = \ + &glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info)= ); \ + } = \ + = \ + type_init( = \ + glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types)= ) + +#define POWERPC_DEF(_name, _pvr, _type, _desc) = \ + POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type) + + /* Embedded PowerPC = */ + /* PowerPC 401 family = */ + POWERPC_DEF("401", CPU_POWERPC_401, 401= , + "Generic PowerPC 401") + /* PowerPC 401 cores = */ + POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401= , + "PowerPC 401A1") + POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401= x2, + "PowerPC 401B2") +#if defined(TODO) + POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401= x3, + "PowerPC 401B3") +#endif + POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401= x2, + "PowerPC 401C2") + POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401= x2, + "PowerPC 401D2") + POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401= x2, + "PowerPC 401E2") + POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401= x2, + "PowerPC 401F2") + /* XXX: to be checked */ + POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401= x2, + "PowerPC 401G2") + /* PowerPC 401 microcontrolers = */ +#if defined(TODO) + POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401= , + "PowerPC 401GF") +#endif + POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP= 480, + "IOP480 (401 microcontroller)") + POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401= , + "IBM Processor for Network Resources") +#if defined(TODO) + POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401= , + NULL) +#endif + /* PowerPC 403 family = */ + /* PowerPC 403 microcontrolers = */ + POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403= , + "PowerPC 403 GA") + POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403= , + "PowerPC 403 GB") + POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403= , + "PowerPC 403 GC") + POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403= GCX, + "PowerPC 403 GCX") +#if defined(TODO) + POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403= , + "PowerPC 403 GP") +#endif + /* PowerPC 405 family = */ + /* PowerPC 405 cores = */ +#if defined(TODO) + POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405= , + "PowerPC 405 A3") +#endif +#if defined(TODO) + POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405= , + "PowerPC 405 A4") +#endif +#if defined(TODO) + POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405= , + "PowerPC 405 B3") +#endif +#if defined(TODO) + POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405= , + "PowerPC 405 B4") +#endif +#if defined(TODO) + POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405= , + "PowerPC 405 C3") +#endif +#if defined(TODO) + POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405= , + "PowerPC 405 C4") +#endif + POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405= , + "PowerPC 405 D2") +#if defined(TODO) + POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405= , + "PowerPC 405 D3") +#endif + POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405= , + "PowerPC 405 D4") +#if defined(TODO) + POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405= , + "PowerPC 405 D5") +#endif +#if defined(TODO) + POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405= , + "PowerPC 405 E4") +#endif +#if defined(TODO) + POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405= , + "PowerPC 405 F4") +#endif +#if defined(TODO) + POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405= , + "PowerPC 405 F5") +#endif +#if defined(TODO) + POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405= , + "PowerPC 405 F6") +#endif + /* PowerPC 405 microcontrolers = */ + POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405= , + "PowerPC 405 CRa") + POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405= , + "PowerPC 405 CRb") + POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405= , + "PowerPC 405 CRc") + POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405= , + "PowerPC 405 EP") +#if defined(TODO) + POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405= , + "PowerPC 405 EXr") +#endif + POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405= , + "PowerPC 405 EZ") +#if defined(TODO) + POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405= , + "PowerPC 405 FX") +#endif + POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405= , + "PowerPC 405 GPa") + POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405= , + "PowerPC 405 GPb") + POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405= , + "PowerPC 405 GPc") + POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405= , + "PowerPC 405 GPd") + POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405= , + "PowerPC 405 GPR") +#if defined(TODO) + POWERPC_DEF("405H", CPU_POWERPC_405H, 405= , + "PowerPC 405 H") +#endif +#if defined(TODO) + POWERPC_DEF("405L", CPU_POWERPC_405L, 405= , + "PowerPC 405 L") +#endif + POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405= , + "PowerPC 405 LP") +#if defined(TODO) + POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405= , + "PowerPC 405 PM") +#endif +#if defined(TODO) + POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405= , + "PowerPC 405 PS") +#endif +#if defined(TODO) + POWERPC_DEF("405S", CPU_POWERPC_405S, 405= , + "PowerPC 405 S") +#endif + POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405= , + "Npe405 H") + POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405= , + "Npe405 H2") + POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405= , + "Npe405 L") + POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405= , + "Npe4GS3") +#if defined(TODO) + POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405= , + NULL) +#endif +#if defined(TODO) + POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405= , + NULL) +#endif +#if defined(TODO) + POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405= , + "PowerPC LC77700 (Sanyo)") +#endif + /* PowerPC 401/403/405 based set-top-box microcontrolers = */ +#if defined(TODO) + POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401= x2, + "STB010000") +#endif +#if defined(TODO) + POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401= x2, + "STB01010") +#endif +#if defined(TODO) + POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401= x3, + "STB0210") +#endif + POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405= , + "STB03xx") +#if defined(TODO) + POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405= , + "STB043x") +#endif +#if defined(TODO) + POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405= , + "STB045x") +#endif + POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405= , + "STB04xx") + POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405= , + "STB25xx") +#if defined(TODO) + POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405= , + "STB130") +#endif + /* Xilinx PowerPC 405 cores = */ + POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405= , + NULL) + POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405= , + NULL) +#if defined(TODO) + POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405= , + "Zarlink ZL10310") +#endif +#if defined(TODO) + POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405= , + "Zarlink ZL10311") +#endif +#if defined(TODO) + POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405= , + "Zarlink ZL10320") +#endif +#if defined(TODO) + POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405= , + "Zarlink ZL10321") +#endif + /* PowerPC 440 family = */ +#if defined(TODO_USER_ONLY) + POWERPC_DEF("440", CPU_POWERPC_440, 440= GP, + "Generic PowerPC 440") +#endif + /* PowerPC 440 cores = */ +#if defined(TODO) + POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440= x4, + "PowerPC 440 A4") +#endif + POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440= x5, + "PowerPC 440 Xilinx 5") +#if defined(TODO) + POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440= x5, + "PowerPC 440 A5") +#endif +#if defined(TODO) + POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440= x4, + "PowerPC 440 B4") +#endif +#if defined(TODO) + POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440= x4, + "PowerPC 440 G4") +#endif +#if defined(TODO) + POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440= x5, + "PowerPC 440 F5") +#endif +#if defined(TODO) + POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440= x5, + "PowerPC 440 G5") +#endif +#if defined(TODO) + POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440= x4, + "PowerPC 440H4") +#endif +#if defined(TODO) + POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440= Gx5, + "PowerPC 440H6") +#endif + /* PowerPC 440 microcontrolers = */ + POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440= EP, + "PowerPC 440 EPa") + POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440= EP, + "PowerPC 440 EPb") + POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440= EP, + "PowerPC 440 EPX") +#if defined(TODO_USER_ONLY) + POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440= GP, + "PowerPC 440 GPb") +#endif +#if defined(TODO_USER_ONLY) + POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440= GP, + "PowerPC 440 GPc") +#endif +#if defined(TODO_USER_ONLY) + POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440= x5, + "PowerPC 440 GRa") +#endif +#if defined(TODO_USER_ONLY) + POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440= x5, + "PowerPC 440 GRX") +#endif +#if defined(TODO_USER_ONLY) + POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440= EP, + "PowerPC 440 GXa") +#endif +#if defined(TODO_USER_ONLY) + POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440= EP, + "PowerPC 440 GXb") +#endif +#if defined(TODO_USER_ONLY) + POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440= EP, + "PowerPC 440 GXc") +#endif +#if defined(TODO_USER_ONLY) + POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440= EP, + "PowerPC 440 GXf") +#endif +#if defined(TODO) + POWERPC_DEF("440S", CPU_POWERPC_440S, 440= , + "PowerPC 440 S") +#endif +#if defined(TODO_USER_ONLY) + POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440= EP, + "PowerPC 440 SP") +#endif +#if defined(TODO_USER_ONLY) + POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440= EP, + "PowerPC 440 SP2") +#endif +#if defined(TODO_USER_ONLY) + POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440= EP, + "PowerPC 440 SPE") +#endif + /* PowerPC 460 family = */ +#if defined(TODO) + POWERPC_DEF("464", CPU_POWERPC_464, 460= , + "Generic PowerPC 464") +#endif + /* PowerPC 464 microcontrolers = */ +#if defined(TODO) + POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460= , + "PowerPC 464H90") +#endif +#if defined(TODO) + POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460= F, + "PowerPC 464H90F") +#endif + /* Freescale embedded PowerPC cores = */ + /* MPC5xx family (aka RCPU) = */ +#if defined(TODO_USER_ONLY) + POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC= 5xx, + "Generic MPC5xx core") +#endif + /* MPC8xx family (aka PowerQUICC) = */ +#if defined(TODO_USER_ONLY) + POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC= 8xx, + "Generic MPC8xx core") +#endif + /* MPC82xx family (aka PowerQUICC-II) = */ + POWERPC_DEF("G2", CPU_POWERPC_G2, G2, + "PowerPC G2 core") + POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2, + "PowerPC G2 H4 core") + POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2, + "PowerPC G2 GP core") + POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2, + "PowerPC G2 LS core") + POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2, + "PowerPC G2 HiP3 core") + POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2, + "PowerPC G2 HiP4 core") + POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603= E, + "PowerPC MPC603 core") + POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2L= E, + "PowerPC G2le core (same as G2 plus little-endian mode support)"= ) + POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2L= E, + "PowerPC G2LE GP core") + POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2L= E, + "PowerPC G2LE LS core") + POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2L= E, + "PowerPC G2LE GP1 core") + POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2L= E, + "PowerPC G2LE GP3 core") + /* PowerPC G2 microcontrollers = */ +#if defined(TODO) + POWERPC_DEF_SVR("MPC5121", "MPC5121", + CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2L= E) +#endif + POWERPC_DEF_SVR("MPC5200_v10", "MPC5200 v1.0", + CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2L= E) + POWERPC_DEF_SVR("MPC5200_v11", "MPC5200 v1.1", + CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2L= E) + POWERPC_DEF_SVR("MPC5200_v12", "MPC5200 v1.2", + CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2L= E) + POWERPC_DEF_SVR("MPC5200B_v20", "MPC5200B v2.0", + CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2L= E) + POWERPC_DEF_SVR("MPC5200B_v21", "MPC5200B v2.1", + CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2L= E) + /* e200 family = */ +#if defined(TODO) + POWERPC_DEF_SVR("MPC55xx", "Generic MPC55xx core", + CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e20= 0, + "PowerPC e200z0 core") +#endif +#if defined(TODO) + POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e20= 0, + "PowerPC e200z1 core") +#endif +#if defined(TODO) + POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e20= 0, + "PowerPC e200z3 core") +#endif + POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e20= 0, + "PowerPC e200z5 core") + POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e20= 0, + "PowerPC e200z6 core") + /* PowerPC e200 microcontrollers = */ +#if defined(TODO) + POWERPC_DEF_SVR("MPC5514E", "MPC5514E", + CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5514E_v0", "MPC5514E v0", + CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5514E_v1", "MPC5514E v1", + CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5514G", "MPC5514G", + CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5514G_v0", "MPC5514G v0", + CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5514G_v1", "MPC5514G v1", + CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5515S", "MPC5515S", + CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5516E", "MPC5516E", + CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5516E_v0", "MPC5516E v0", + CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5516E_v1", "MPC5516E v1", + CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5516G", "MPC5516G", + CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5516G_v0", "MPC5516G v0", + CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5516G_v1", "MPC5516G v1", + CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5516S", "MPC5516S", + CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5533", "MPC5533", + CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5534", "MPC5534", + CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5553", "MPC5553", + CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5554", "MPC5554", + CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5561", "MPC5561", + CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5565", "MPC5565", + CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5566", "MPC5566", + CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e20= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC5567", "MPC5567", + CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e20= 0) +#endif + /* e300 family = */ + POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e30= 0, + "PowerPC e300c1 core") + POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e30= 0, + "PowerPC e300c2 core") + POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e30= 0, + "PowerPC e300c3 core") + POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e30= 0, + "PowerPC e300c4 core") + /* PowerPC e300 microcontrollers = */ +#if defined(TODO) + POWERPC_DEF_SVR("MPC8313", "MPC8313", + CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e30= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC8313E", "MPC8313E", + CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e30= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC8314", "MPC8314", + CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e30= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC8314E", "MPC8314E", + CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e30= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC8315", "MPC8315", + CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e30= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC8315E", "MPC8315E", + CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e30= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC8321", "MPC8321", + CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e30= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC8321E", "MPC8321E", + CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e30= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC8323", "MPC8323", + CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e30= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC8323E", "MPC8323E", + CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e30= 0) +#endif + POWERPC_DEF_SVR("MPC8343", "MPC8343", + CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e30= 0) + POWERPC_DEF_SVR("MPC8343A", "MPC8343A", + CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e30= 0) + POWERPC_DEF_SVR("MPC8343E", "MPC8343E", + CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e30= 0) + POWERPC_DEF_SVR("MPC8343EA", "MPC8343EA", + CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e30= 0) + POWERPC_DEF_SVR("MPC8347T", "MPC8347T", + CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e30= 0) + POWERPC_DEF_SVR("MPC8347P", "MPC8347P", + CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e30= 0) + POWERPC_DEF_SVR("MPC8347AT", "MPC8347AT", + CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e30= 0) + POWERPC_DEF_SVR("MPC8347AP", "MPC8347AP", + CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e30= 0) + POWERPC_DEF_SVR("MPC8347ET", "MPC8347ET", + CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e30= 0) + POWERPC_DEF_SVR("MPC8347EP", "MPC8343EP", + CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e30= 0) + POWERPC_DEF_SVR("MPC8347EAT", "MPC8347EAT", + CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e30= 0) + POWERPC_DEF_SVR("MPC8347EAP", "MPC8343EAP", + CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e30= 0) + POWERPC_DEF_SVR("MPC8349", "MPC8349", + CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e30= 0) + POWERPC_DEF_SVR("MPC8349A", "MPC8349A", + CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e30= 0) + POWERPC_DEF_SVR("MPC8349E", "MPC8349E", + CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e30= 0) + POWERPC_DEF_SVR("MPC8349EA", "MPC8349EA", + CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e30= 0) +#if defined(TODO) + POWERPC_DEF_SVR("MPC8358E", "MPC8358E", + CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e30= 0) +#endif +#if defined(TODO) + POWERPC_DEF_SVR("MPC8360E", "MPC8360E", + CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e30= 0) +#endif + POWERPC_DEF_SVR("MPC8377", "MPC8377", + CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e30= 0) + POWERPC_DEF_SVR("MPC8377E", "MPC8377E", + CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e30= 0) + POWERPC_DEF_SVR("MPC8378", "MPC8378", + CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e30= 0) + POWERPC_DEF_SVR("MPC8378E", "MPC8378E", + CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e30= 0) + POWERPC_DEF_SVR("MPC8379", "MPC8379", + CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e30= 0) + POWERPC_DEF_SVR("MPC8379E", "MPC8379E", + CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e30= 0) + /* e500 family = */ + POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e50= 0v1, + "PowerPC e500 v1.0 core") + POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e50= 0v1, + "PowerPC e500 v2.0 core") + POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e50= 0v2, + "PowerPC e500v2 v1.0 core") + POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e50= 0v2, + "PowerPC e500v2 v2.0 core") + POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e50= 0v2, + "PowerPC e500v2 v2.1 core") + POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e50= 0v2, + "PowerPC e500v2 v2.2 core") + POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e50= 0v2, + "PowerPC e500v2 v3.0 core") + POWERPC_DEF_SVR("e500mc", "e500mc", + CPU_POWERPC_e500mc, POWERPC_SVR_E500, e50= 0mc) +#ifdef TARGET_PPC64 + POWERPC_DEF_SVR("e5500", "e5500", + CPU_POWERPC_e5500, POWERPC_SVR_E500, e55= 00) +#endif + /* PowerPC e500 microcontrollers = */ + POWERPC_DEF_SVR("MPC8533_v10", "MPC8533 v1.0", + CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e50= 0v2) + POWERPC_DEF_SVR("MPC8533_v11", "MPC8533 v1.1", + CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e50= 0v2) + POWERPC_DEF_SVR("MPC8533E_v10", "MPC8533E v1.0", + CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e50= 0v2) + POWERPC_DEF_SVR("MPC8533E_v11", "MPC8533E v1.1", + CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e50= 0v2) + POWERPC_DEF_SVR("MPC8540_v10", "MPC8540 v1.0", + CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e50= 0v1) + POWERPC_DEF_SVR("MPC8540_v20", "MPC8540 v2.0", + CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e50= 0v1) + POWERPC_DEF_SVR("MPC8540_v21", "MPC8540 v2.1", + CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e50= 0v1) + POWERPC_DEF_SVR("MPC8541_v10", "MPC8541 v1.0", + CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e50= 0v1) + POWERPC_DEF_SVR("MPC8541_v11", "MPC8541 v1.1", + CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e50= 0v1) + POWERPC_DEF_SVR("MPC8541E_v10", "MPC8541E v1.0", + CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e50= 0v1) + POWERPC_DEF_SVR("MPC8541E_v11", "MPC8541E v1.1", + CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e50= 0v1) + POWERPC_DEF_SVR("MPC8543_v10", "MPC8543 v1.0", + CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e50= 0v2) + POWERPC_DEF_SVR("MPC8543_v11", "MPC8543 v1.1", + CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e50= 0v2) + POWERPC_DEF_SVR("MPC8543_v20", "MPC8543 v2.0", + CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e50= 0v2) + POWERPC_DEF_SVR("MPC8543_v21", "MPC8543 v2.1", + CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e50= 0v2) + POWERPC_DEF_SVR("MPC8543E_v10", "MPC8543E v1.0", + CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e50= 0v2) + POWERPC_DEF_SVR("MPC8543E_v11", "MPC8543E v1.1", + CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e50= 0v2) + POWERPC_DEF_SVR("MPC8543E_v20", "MPC8543E v2.0", + CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e50= 0v2) + POWERPC_DEF_SVR("MPC8543E_v21", "MPC8543E v2.1", + CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e50= 0v2) + POWERPC_DEF_SVR("MPC8544_v10", "MPC8544 v1.0", + CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e50= 0v2) + POWERPC_DEF_SVR("MPC8544_v11", "MPC8544 v1.1", + CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e50= 0v2) + POWERPC_DEF_SVR("MPC8544E_v10", "MPC8544E v1.0", + CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e50= 0v2) + POWERPC_DEF_SVR("MPC8544E_v11", "MPC8544E v1.1", + CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e50= 0v2) + POWERPC_DEF_SVR("MPC8545_v20", "MPC8545 v2.0", + CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e50= 0v2) + POWERPC_DEF_SVR("MPC8545_v21", "MPC8545 v2.1", + CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e50= 0v2) + POWERPC_DEF_SVR("MPC8545E_v20", "MPC8545E v2.0", + CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e50= 0v2) + POWERPC_DEF_SVR("MPC8545E_v21", "MPC8545E v2.1", + CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e50= 0v2) + POWERPC_DEF_SVR("MPC8547E_v20", "MPC8547E v2.0", + CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e50= 0v2) + POWERPC_DEF_SVR("MPC8547E_v21", "MPC8547E v2.1", + CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e50= 0v2) + POWERPC_DEF_SVR("MPC8548_v10", "MPC8548 v1.0", + CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e50= 0v2) + POWERPC_DEF_SVR("MPC8548_v11", "MPC8548 v1.1", + CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e50= 0v2) + POWERPC_DEF_SVR("MPC8548_v20", "MPC8548 v2.0", + CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e50= 0v2) + POWERPC_DEF_SVR("MPC8548_v21", "MPC8548 v2.1", + CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e50= 0v2) + POWERPC_DEF_SVR("MPC8548E_v10", "MPC8548E v1.0", + CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e50= 0v2) + POWERPC_DEF_SVR("MPC8548E_v11", "MPC8548E v1.1", + CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e50= 0v2) + POWERPC_DEF_SVR("MPC8548E_v20", "MPC8548E v2.0", + CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e50= 0v2) + POWERPC_DEF_SVR("MPC8548E_v21", "MPC8548E v2.1", + CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e50= 0v2) + POWERPC_DEF_SVR("MPC8555_v10", "MPC8555 v1.0", + CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e50= 0v2) + POWERPC_DEF_SVR("MPC8555_v11", "MPC8555 v1.1", + CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e50= 0v2) + POWERPC_DEF_SVR("MPC8555E_v10", "MPC8555E v1.0", + CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e50= 0v2) + POWERPC_DEF_SVR("MPC8555E_v11", "MPC8555E v1.1", + CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e50= 0v2) + POWERPC_DEF_SVR("MPC8560_v10", "MPC8560 v1.0", + CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e50= 0v2) + POWERPC_DEF_SVR("MPC8560_v20", "MPC8560 v2.0", + CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e50= 0v2) + POWERPC_DEF_SVR("MPC8560_v21", "MPC8560 v2.1", + CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e50= 0v2) + POWERPC_DEF_SVR("MPC8567", "MPC8567", + CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e50= 0v2) + POWERPC_DEF_SVR("MPC8567E", "MPC8567E", + CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e50= 0v2) + POWERPC_DEF_SVR("MPC8568", "MPC8568", + CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e50= 0v2) + POWERPC_DEF_SVR("MPC8568E", "MPC8568E", + CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e50= 0v2) + POWERPC_DEF_SVR("MPC8572", "MPC8572", + CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e50= 0v2) + POWERPC_DEF_SVR("MPC8572E", "MPC8572E", + CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e50= 0v2) + /* e600 family = */ + POWERPC_DEF("e600", CPU_POWERPC_e600, 740= 0, + "PowerPC e600 core") + /* PowerPC e600 microcontrollers = */ +#if defined(TODO) + POWERPC_DEF_SVR("MPC8610", "MPC8610", + CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 740= 0) +#endif + POWERPC_DEF_SVR("MPC8641", "MPC8641", + CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 740= 0) + POWERPC_DEF_SVR("MPC8641D", "MPC8641D", + CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 740= 0) + /* 32 bits "classic" PowerPC = */ + /* PowerPC 6xx family = */ + POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601= , + "PowerPC 601v0") + POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601= , + "PowerPC 601v1") + POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601= v, + "PowerPC 601v2") + POWERPC_DEF("602", CPU_POWERPC_602, 602= , + "PowerPC 602") + POWERPC_DEF("603", CPU_POWERPC_603, 603= , + "PowerPC 603") + POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603= E, + "PowerPC 603e v1.1") + POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603= E, + "PowerPC 603e v1.2") + POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603= E, + "PowerPC 603e v1.3") + POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603= E, + "PowerPC 603e v1.4") + POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603= E, + "PowerPC 603e v2.2") + POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603= E, + "PowerPC 603e v3") + POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603= E, + "PowerPC 603e v4") + POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603= E, + "PowerPC 603e v4.1") + POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603= E, + "PowerPC 603e (aka PID7)") + POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603= E, + "PowerPC 603e7t") + POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603= E, + "PowerPC 603e7v") + POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603= E, + "PowerPC 603e7v1") + POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603= E, + "PowerPC 603e7v2") + POWERPC_DEF("603p", CPU_POWERPC_603P, 603= E, + "PowerPC 603p (aka PID7v)") + POWERPC_DEF("604", CPU_POWERPC_604, 604= , + "PowerPC 604") + POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604= E, + "PowerPC 604e v1.0") + POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604= E, + "PowerPC 604e v2.2") + POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604= E, + "PowerPC 604e v2.4") + POWERPC_DEF("604r", CPU_POWERPC_604R, 604= E, + "PowerPC 604r (aka PIDA)") +#if defined(TODO) + POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604= E, + "PowerPC 604ev") +#endif + /* PowerPC 7xx family = */ + POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740= , + "PowerPC 740 v1.0 (G3)") + POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750= , + "PowerPC 750 v1.0 (G3)") + POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740= , + "PowerPC 740 v2.0 (G3)") + POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750= , + "PowerPC 750 v2.0 (G3)") + POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740= , + "PowerPC 740 v2.1 (G3)") + POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750= , + "PowerPC 750 v2.1 (G3)") + POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740= , + "PowerPC 740 v2.2 (G3)") + POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750= , + "PowerPC 750 v2.2 (G3)") + POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740= , + "PowerPC 740 v3.0 (G3)") + POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750= , + "PowerPC 750 v3.0 (G3)") + POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740= , + "PowerPC 740 v3.1 (G3)") + POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750= , + "PowerPC 750 v3.1 (G3)") + POWERPC_DEF("740e", CPU_POWERPC_740E, 740= , + "PowerPC 740E (G3)") + POWERPC_DEF("750e", CPU_POWERPC_750E, 750= , + "PowerPC 750E (G3)") + POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740= , + "PowerPC 740P (G3)") + POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750= , + "PowerPC 750P (G3)") + POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750= cl, + "PowerPC 750CL v1.0") + POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750= cl, + "PowerPC 750CL v2.0") + POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750= cx, + "PowerPC 750CX v1.0 (G3 embedded)") + POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750= cx, + "PowerPC 750CX v2.1 (G3 embedded)") + POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750= cx, + "PowerPC 750CX v2.1 (G3 embedded)") + POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750= cx, + "PowerPC 750CX v2.2 (G3 embedded)") + POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750= cx, + "PowerPC 750CXe v2.1 (G3 embedded)") + POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750= cx, + "PowerPC 750CXe v2.2 (G3 embedded)") + POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750= cx, + "PowerPC 750CXe v2.3 (G3 embedded)") + POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750= cx, + "PowerPC 750CXe v2.4 (G3 embedded)") + POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750= cx, + "PowerPC 750CXe v2.4b (G3 embedded)") + POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750= cx, + "PowerPC 750CXe v3.0 (G3 embedded)") + POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750= cx, + "PowerPC 750CXe v3.1 (G3 embedded)") + POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750= cx, + "PowerPC 750CXe v3.1b (G3 embedded)") + POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750= cx, + "PowerPC 750CXr (G3 embedded)") + POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750= fx, + "PowerPC 750FL (G3 embedded)") + POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750= fx, + "PowerPC 750FX v1.0 (G3 embedded)") + POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750= fx, + "PowerPC 750FX v2.0 (G3 embedded)") + POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750= fx, + "PowerPC 750FX v2.1 (G3 embedded)") + POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750= fx, + "PowerPC 750FX v2.2 (G3 embedded)") + POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750= fx, + "PowerPC 750FX v2.3 (G3 embedded)") + POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750= gx, + "PowerPC 750GL (G3 embedded)") + POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750= gx, + "PowerPC 750GX v1.0 (G3 embedded)") + POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750= gx, + "PowerPC 750GX v1.1 (G3 embedded)") + POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750= gx, + "PowerPC 750GX v1.2 (G3 embedded)") + POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750= , + "PowerPC 750L v2.0 (G3 embedded)") + POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750= , + "PowerPC 750L v2.1 (G3 embedded)") + POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750= , + "PowerPC 750L v2.2 (G3 embedded)") + POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750= , + "PowerPC 750L v3.0 (G3 embedded)") + POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750= , + "PowerPC 750L v3.2 (G3 embedded)") + POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745= , + "PowerPC 745 v1.0") + POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755= , + "PowerPC 755 v1.0") + POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745= , + "PowerPC 745 v1.1") + POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755= , + "PowerPC 755 v1.1") + POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745= , + "PowerPC 745 v2.0") + POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755= , + "PowerPC 755 v2.0") + POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745= , + "PowerPC 745 v2.1") + POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755= , + "PowerPC 755 v2.1") + POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745= , + "PowerPC 745 v2.2") + POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755= , + "PowerPC 755 v2.2") + POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745= , + "PowerPC 745 v2.3") + POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755= , + "PowerPC 755 v2.3") + POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745= , + "PowerPC 745 v2.4") + POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755= , + "PowerPC 755 v2.4") + POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745= , + "PowerPC 745 v2.5") + POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755= , + "PowerPC 755 v2.5") + POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745= , + "PowerPC 745 v2.6") + POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755= , + "PowerPC 755 v2.6") + POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745= , + "PowerPC 745 v2.7") + POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755= , + "PowerPC 755 v2.7") + POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745= , + "PowerPC 745 v2.8") + POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755= , + "PowerPC 755 v2.8") +#if defined(TODO) + POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745= , + "PowerPC 745P (G3)") + POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755= , + "PowerPC 755P (G3)") +#endif + /* PowerPC 74xx family = */ + POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 740= 0, + "PowerPC 7400 v1.0 (G4)") + POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 740= 0, + "PowerPC 7400 v1.1 (G4)") + POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 740= 0, + "PowerPC 7400 v2.0 (G4)") + POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 740= 0, + "PowerPC 7400 v2.1 (G4)") + POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 740= 0, + "PowerPC 7400 v2.2 (G4)") + POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 740= 0, + "PowerPC 7400 v2.6 (G4)") + POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 740= 0, + "PowerPC 7400 v2.7 (G4)") + POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 740= 0, + "PowerPC 7400 v2.8 (G4)") + POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 740= 0, + "PowerPC 7400 v2.9 (G4)") + POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 741= 0, + "PowerPC 7410 v1.0 (G4)") + POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 741= 0, + "PowerPC 7410 v1.1 (G4)") + POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 741= 0, + "PowerPC 7410 v1.2 (G4)") + POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 741= 0, + "PowerPC 7410 v1.3 (G4)") + POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 741= 0, + "PowerPC 7410 v1.4 (G4)") + POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 740= 0, + "PowerPC 7448 v1.0 (G4)") + POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 740= 0, + "PowerPC 7448 v1.1 (G4)") + POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 740= 0, + "PowerPC 7448 v2.0 (G4)") + POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 740= 0, + "PowerPC 7448 v2.1 (G4)") + POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 745= 0, + "PowerPC 7450 v1.0 (G4)") + POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 745= 0, + "PowerPC 7450 v1.1 (G4)") + POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 745= 0, + "PowerPC 7450 v1.2 (G4)") + POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 745= 0, + "PowerPC 7450 v2.0 (G4)") + POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 745= 0, + "PowerPC 7450 v2.1 (G4)") + POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 744= 0, + "PowerPC 7441 v2.1 (G4)") + POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 744= 0, + "PowerPC 7441 v2.3 (G4)") + POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 745= 0, + "PowerPC 7451 v2.3 (G4)") + POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 744= 0, + "PowerPC 7441 v2.10 (G4)") + POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 745= 0, + "PowerPC 7451 v2.10 (G4)") + POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 744= 5, + "PowerPC 7445 v1.0 (G4)") + POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 745= 5, + "PowerPC 7455 v1.0 (G4)") + POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 744= 5, + "PowerPC 7445 v2.1 (G4)") + POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 745= 5, + "PowerPC 7455 v2.1 (G4)") + POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 744= 5, + "PowerPC 7445 v3.2 (G4)") + POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 745= 5, + "PowerPC 7455 v3.2 (G4)") + POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 744= 5, + "PowerPC 7445 v3.3 (G4)") + POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 745= 5, + "PowerPC 7455 v3.3 (G4)") + POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 744= 5, + "PowerPC 7445 v3.4 (G4)") + POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 745= 5, + "PowerPC 7455 v3.4 (G4)") + POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 744= 5, + "PowerPC 7447 v1.0 (G4)") + POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 745= 5, + "PowerPC 7457 v1.0 (G4)") + POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 744= 5, + "PowerPC 7447 v1.1 (G4)") + POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 745= 5, + "PowerPC 7457 v1.1 (G4)") + POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 745= 5, + "PowerPC 7457 v1.2 (G4)") + POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 744= 5, + "PowerPC 7447A v1.0 (G4)") + POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 745= 5, + "PowerPC 7457A v1.0 (G4)") + POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 744= 5, + "PowerPC 7447A v1.1 (G4)") + POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 745= 5, + "PowerPC 7457A v1.1 (G4)") + POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 744= 5, + "PowerPC 7447A v1.2 (G4)") + POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 745= 5, + "PowerPC 7457A v1.2 (G4)") + /* 64 bits PowerPC = */ +#if defined (TARGET_PPC64) + POWERPC_DEF("620", CPU_POWERPC_620, 620= , + "PowerPC 620") +#if defined(TODO) + POWERPC_DEF("630", CPU_POWERPC_630, 630= , + "PowerPC 630 (POWER3)") +#endif +#if defined(TODO) + POWERPC_DEF("631", CPU_POWERPC_631, 631= , + "PowerPC 631 (Power 3+)") +#endif +#if defined(TODO) + POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POW= ER4, + "POWER4") +#endif +#if defined(TODO) + POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POW= ER4P, + "POWER4p") +#endif +#if defined(TODO) + POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POW= ER5, + "POWER5") + POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POW= ER5, + "POWER5GR") +#endif +#if defined(TODO) + POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POW= ER5P, + "POWER5+") + POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POW= ER5P, + "POWER5GS") +#endif +#if defined(TODO) + POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POW= ER6, + "POWER6") + POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POW= ER5, + "POWER6 running in POWER5 mode") + POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POW= ER6, + "POWER6A") +#endif + POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POW= ER7, + "POWER7 v2.0") + POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POW= ER7, + "POWER7 v2.1") + POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POW= ER7, + "POWER7 v2.3") + POWERPC_DEF("970", CPU_POWERPC_970, 970= , + "PowerPC 970") + POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970= FX, + "PowerPC 970FX v1.0 (G5)") + POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970= FX, + "PowerPC 970FX v2.0 (G5)") + POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970= FX, + "PowerPC 970FX v2.1 (G5)") + POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970= FX, + "PowerPC 970FX v3.0 (G5)") + POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970= FX, + "PowerPC 970FX v3.1 (G5)") + POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970= GX, + "PowerPC 970GX (G5)") + POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970= MP, + "PowerPC 970MP v1.0") + POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970= MP, + "PowerPC 970MP v1.1") +#if defined(TODO) + POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970= , + "PowerPC Cell") +#endif +#if defined(TODO) + POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970= , + "PowerPC Cell v1.0") +#endif +#if defined(TODO) + POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970= , + "PowerPC Cell v2.0") +#endif +#if defined(TODO) + POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970= , + "PowerPC Cell v3.0") +#endif +#if defined(TODO) + POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970= , + "PowerPC Cell v3.1") +#endif +#if defined(TODO) + POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970= , + "PowerPC Cell v3.2") +#endif +#if defined(TODO) + /* This one seems to support the whole POWER2 instruction set + * and the PowerPC 64 one. + */ + /* What about A10 & A30 ? */ + POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS6= 4, + "RS64 (Apache/A35)") +#endif +#if defined(TODO) + POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS6= 4, + "RS64-II (NorthStar/A50)") +#endif +#if defined(TODO) + POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS6= 4, + "RS64-III (Pulsar)") +#endif +#if defined(TODO) + POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS6= 4, + "RS64-IV (IceStar/IStar/SStar)") +#endif +#endif /* defined (TARGET_PPC64) */ + /* POWER = */ +#if defined(TODO) + POWERPC_DEF("POWER", CPU_POWERPC_POWER, POW= ER, + "Original POWER") +#endif +#if defined(TODO) + POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POW= ER, + "POWER2") +#endif + /* PA semi cores = */ +#if defined(TODO) + POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6= T, + "PA PA6T") +#endif + diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h new file mode 100644 index 0000000..edff0f4 --- /dev/null +++ b/target-ppc/cpu-models.h @@ -0,0 +1,727 @@ +/* + * PowerPC CPU initialization for qemu. + * + * Copyright (c) 2003-2007 Jocelyn Mayer + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#ifndef TARGET_PPC_CPU_MODELS_H +#define TARGET_PPC_CPU_MODELS_H + +/***********************************************************************= ******/ +/* PVR definitions for most known PowerPC = */ +enum { + /* PowerPC 401 family */ + /* Generic PowerPC 401 */ +#define CPU_POWERPC_401 CPU_POWERPC_401G2 + /* PowerPC 401 cores */ + CPU_POWERPC_401A1 =3D 0x00210000, + CPU_POWERPC_401B2 =3D 0x00220000, +#if 0 + CPU_POWERPC_401B3 =3D xxx, +#endif + CPU_POWERPC_401C2 =3D 0x00230000, + CPU_POWERPC_401D2 =3D 0x00240000, + CPU_POWERPC_401E2 =3D 0x00250000, + CPU_POWERPC_401F2 =3D 0x00260000, + CPU_POWERPC_401G2 =3D 0x00270000, + /* PowerPC 401 microcontrolers */ +#if 0 + CPU_POWERPC_401GF =3D xxx, +#endif +#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2 + /* IBM Processor for Network Resources */ + CPU_POWERPC_COBRA =3D 0x10100000, /* XXX: 405 ? */ +#if 0 + CPU_POWERPC_XIPCHIP =3D xxx, +#endif + /* PowerPC 403 family */ + /* PowerPC 403 microcontrollers */ + CPU_POWERPC_403GA =3D 0x00200011, + CPU_POWERPC_403GB =3D 0x00200100, + CPU_POWERPC_403GC =3D 0x00200200, + CPU_POWERPC_403GCX =3D 0x00201400, +#if 0 + CPU_POWERPC_403GP =3D xxx, +#endif + /* PowerPC 405 family */ + /* PowerPC 405 cores */ +#if 0 + CPU_POWERPC_405A3 =3D xxx, +#endif +#if 0 + CPU_POWERPC_405A4 =3D xxx, +#endif +#if 0 + CPU_POWERPC_405B3 =3D xxx, +#endif +#if 0 + CPU_POWERPC_405B4 =3D xxx, +#endif +#if 0 + CPU_POWERPC_405C3 =3D xxx, +#endif +#if 0 + CPU_POWERPC_405C4 =3D xxx, +#endif + CPU_POWERPC_405D2 =3D 0x20010000, +#if 0 + CPU_POWERPC_405D3 =3D xxx, +#endif + CPU_POWERPC_405D4 =3D 0x41810000, +#if 0 + CPU_POWERPC_405D5 =3D xxx, +#endif +#if 0 + CPU_POWERPC_405E4 =3D xxx, +#endif +#if 0 + CPU_POWERPC_405F4 =3D xxx, +#endif +#if 0 + CPU_POWERPC_405F5 =3D xxx, +#endif +#if 0 + CPU_POWERPC_405F6 =3D xxx, +#endif + /* PowerPC 405 microcontrolers */ + /* XXX: missing 0x200108a0 */ + CPU_POWERPC_405CRa =3D 0x40110041, + CPU_POWERPC_405CRb =3D 0x401100C5, + CPU_POWERPC_405CRc =3D 0x40110145, + CPU_POWERPC_405EP =3D 0x51210950, +#if 0 + CPU_POWERPC_405EXr =3D xxx, +#endif + CPU_POWERPC_405EZ =3D 0x41511460, /* 0x51210950 ? */ +#if 0 + CPU_POWERPC_405FX =3D xxx, +#endif + CPU_POWERPC_405GPa =3D 0x40110000, + CPU_POWERPC_405GPb =3D 0x40110040, + CPU_POWERPC_405GPc =3D 0x40110082, + CPU_POWERPC_405GPd =3D 0x401100C4, + CPU_POWERPC_405GPR =3D 0x50910951, +#if 0 + CPU_POWERPC_405H =3D xxx, +#endif +#if 0 + CPU_POWERPC_405L =3D xxx, +#endif + CPU_POWERPC_405LP =3D 0x41F10000, +#if 0 + CPU_POWERPC_405PM =3D xxx, +#endif +#if 0 + CPU_POWERPC_405PS =3D xxx, +#endif +#if 0 + CPU_POWERPC_405S =3D xxx, +#endif + /* IBM network processors */ + CPU_POWERPC_NPE405H =3D 0x414100C0, + CPU_POWERPC_NPE405H2 =3D 0x41410140, + CPU_POWERPC_NPE405L =3D 0x416100C0, + CPU_POWERPC_NPE4GS3 =3D 0x40B10000, +#if 0 + CPU_POWERPC_NPCxx1 =3D xxx, +#endif +#if 0 + CPU_POWERPC_NPR161 =3D xxx, +#endif +#if 0 + CPU_POWERPC_LC77700 =3D xxx, +#endif + /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */ +#if 0 + CPU_POWERPC_STB01000 =3D xxx, +#endif +#if 0 + CPU_POWERPC_STB01010 =3D xxx, +#endif +#if 0 + CPU_POWERPC_STB0210 =3D xxx, /* 401B3 */ +#endif + CPU_POWERPC_STB03 =3D 0x40310000, /* 0x40130000 ? */ +#if 0 + CPU_POWERPC_STB043 =3D xxx, +#endif +#if 0 + CPU_POWERPC_STB045 =3D xxx, +#endif + CPU_POWERPC_STB04 =3D 0x41810000, + CPU_POWERPC_STB25 =3D 0x51510950, +#if 0 + CPU_POWERPC_STB130 =3D xxx, +#endif + /* Xilinx cores */ + CPU_POWERPC_X2VP4 =3D 0x20010820, + CPU_POWERPC_X2VP20 =3D 0x20010860, +#if 0 + CPU_POWERPC_ZL10310 =3D xxx, +#endif +#if 0 + CPU_POWERPC_ZL10311 =3D xxx, +#endif +#if 0 + CPU_POWERPC_ZL10320 =3D xxx, +#endif +#if 0 + CPU_POWERPC_ZL10321 =3D xxx, +#endif + /* PowerPC 440 family */ + /* Generic PowerPC 440 */ +#define CPU_POWERPC_440 CPU_POWERPC_440GXf + /* PowerPC 440 cores */ +#if 0 + CPU_POWERPC_440A4 =3D xxx, +#endif + CPU_POWERPC_440_XILINX =3D 0x7ff21910, +#if 0 + CPU_POWERPC_440A5 =3D xxx, +#endif +#if 0 + CPU_POWERPC_440B4 =3D xxx, +#endif +#if 0 + CPU_POWERPC_440F5 =3D xxx, +#endif +#if 0 + CPU_POWERPC_440G5 =3D xxx, +#endif +#if 0 + CPU_POWERPC_440H4 =3D xxx, +#endif +#if 0 + CPU_POWERPC_440H6 =3D xxx, +#endif + /* PowerPC 440 microcontrolers */ + CPU_POWERPC_440EPa =3D 0x42221850, + CPU_POWERPC_440EPb =3D 0x422218D3, + CPU_POWERPC_440GPb =3D 0x40120440, + CPU_POWERPC_440GPc =3D 0x40120481, +#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb + CPU_POWERPC_440GRX =3D 0x200008D0, +#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX + CPU_POWERPC_440GXa =3D 0x51B21850, + CPU_POWERPC_440GXb =3D 0x51B21851, + CPU_POWERPC_440GXc =3D 0x51B21892, + CPU_POWERPC_440GXf =3D 0x51B21894, +#if 0 + CPU_POWERPC_440S =3D xxx, +#endif + CPU_POWERPC_440SP =3D 0x53221850, + CPU_POWERPC_440SP2 =3D 0x53221891, + CPU_POWERPC_440SPE =3D 0x53421890, + /* PowerPC 460 family */ +#if 0 + /* Generic PowerPC 464 */ +#define CPU_POWERPC_464 CPU_POWERPC_464H90 +#endif + /* PowerPC 464 microcontrolers */ +#if 0 + CPU_POWERPC_464H90 =3D xxx, +#endif +#if 0 + CPU_POWERPC_464H90FP =3D xxx, +#endif + /* Freescale embedded PowerPC cores */ + /* PowerPC MPC 5xx cores (aka RCPU) */ + CPU_POWERPC_MPC5xx =3D 0x00020020, + /* PowerPC MPC 8xx cores (aka PowerQUICC) */ + CPU_POWERPC_MPC8xx =3D 0x00500000, + /* G2 cores (aka PowerQUICC-II) */ + CPU_POWERPC_G2 =3D 0x00810011, + CPU_POWERPC_G2H4 =3D 0x80811010, + CPU_POWERPC_G2gp =3D 0x80821010, + CPU_POWERPC_G2ls =3D 0x90810010, + CPU_POWERPC_MPC603 =3D 0x00810100, + CPU_POWERPC_G2_HIP3 =3D 0x00810101, + CPU_POWERPC_G2_HIP4 =3D 0x80811014, + /* G2_LE core (aka PowerQUICC-II) */ + CPU_POWERPC_G2LE =3D 0x80820010, + CPU_POWERPC_G2LEgp =3D 0x80822010, + CPU_POWERPC_G2LEls =3D 0xA0822010, + CPU_POWERPC_G2LEgp1 =3D 0x80822011, + CPU_POWERPC_G2LEgp3 =3D 0x80822013, + /* MPC52xx microcontrollers */ + /* XXX: MPC 5121 ? */ +#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1 +#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1 +#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1 +#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1 +#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1 + /* e200 family */ + /* e200 cores */ +#if 0 + CPU_POWERPC_e200z0 =3D xxx, +#endif +#if 0 + CPU_POWERPC_e200z1 =3D xxx, +#endif +#if 0 /* ? */ + CPU_POWERPC_e200z3 =3D 0x81120000, +#endif + CPU_POWERPC_e200z5 =3D 0x81000000, + CPU_POWERPC_e200z6 =3D 0x81120000, + /* MPC55xx microcontrollers */ +#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567 +#if 0 +#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1 +#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0 +#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1 +#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1 +#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0 +#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1 +#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1 +#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1 +#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0 +#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1 +#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1 +#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0 +#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1 +#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1 +#endif +#if 0 +#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3 +#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3 +#endif +#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6 +#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6 +#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6 +#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6 +#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6 +#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6 + /* e300 family */ + /* e300 cores */ + CPU_POWERPC_e300c1 =3D 0x00830010, + CPU_POWERPC_e300c2 =3D 0x00840010, + CPU_POWERPC_e300c3 =3D 0x00850010, + CPU_POWERPC_e300c4 =3D 0x00860010, + /* MPC83xx microcontrollers */ +#define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3 +#define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2 +#define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1 +#define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1 +#define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1 +#define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4 + /* e500 family */ + /* e500 cores */ +#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22 + CPU_POWERPC_e500v1_v10 =3D 0x80200010, + CPU_POWERPC_e500v1_v20 =3D 0x80200020, + CPU_POWERPC_e500v2_v10 =3D 0x80210010, + CPU_POWERPC_e500v2_v11 =3D 0x80210011, + CPU_POWERPC_e500v2_v20 =3D 0x80210020, + CPU_POWERPC_e500v2_v21 =3D 0x80210021, + CPU_POWERPC_e500v2_v22 =3D 0x80210022, + CPU_POWERPC_e500v2_v30 =3D 0x80210030, + CPU_POWERPC_e500mc =3D 0x80230020, + CPU_POWERPC_e5500 =3D 0x80240020, + /* MPC85xx microcontrollers */ +#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21 +#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22 +#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21 +#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22 +#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10 +#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20 +#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20 +#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20 +#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20 +#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20 +#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20 +#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10 +#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11 +#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20 +#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21 +#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10 +#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11 +#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20 +#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21 +#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21 +#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22 +#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22 +#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21 +#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10 +#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20 +#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21 +#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10 +#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20 +#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21 +#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10 +#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20 +#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21 +#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10 +#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11 +#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20 +#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21 +#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10 +#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11 +#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20 +#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21 +#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10 +#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11 +#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10 +#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11 +#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10 +#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20 +#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21 +#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22 +#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22 +#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22 +#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22 +#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30 +#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30 + /* e600 family */ + /* e600 cores */ + CPU_POWERPC_e600 =3D 0x80040010, + /* MPC86xx microcontrollers */ +#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600 +#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600 +#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600 + /* PowerPC 6xx cores */ + CPU_POWERPC_601_v0 =3D 0x00010001, + CPU_POWERPC_601_v1 =3D 0x00010001, + CPU_POWERPC_601_v2 =3D 0x00010002, + CPU_POWERPC_602 =3D 0x00050100, + CPU_POWERPC_603 =3D 0x00030100, + CPU_POWERPC_603E_v11 =3D 0x00060101, + CPU_POWERPC_603E_v12 =3D 0x00060102, + CPU_POWERPC_603E_v13 =3D 0x00060103, + CPU_POWERPC_603E_v14 =3D 0x00060104, + CPU_POWERPC_603E_v22 =3D 0x00060202, + CPU_POWERPC_603E_v3 =3D 0x00060300, + CPU_POWERPC_603E_v4 =3D 0x00060400, + CPU_POWERPC_603E_v41 =3D 0x00060401, + CPU_POWERPC_603E7t =3D 0x00071201, + CPU_POWERPC_603E7v =3D 0x00070100, + CPU_POWERPC_603E7v1 =3D 0x00070101, + CPU_POWERPC_603E7v2 =3D 0x00070201, + CPU_POWERPC_603E7 =3D 0x00070200, + CPU_POWERPC_603P =3D 0x00070000, + /* XXX: missing 0x00040303 (604) */ + CPU_POWERPC_604 =3D 0x00040103, + /* XXX: missing 0x00091203 */ + /* XXX: missing 0x00092110 */ + /* XXX: missing 0x00092120 */ + CPU_POWERPC_604E_v10 =3D 0x00090100, + CPU_POWERPC_604E_v22 =3D 0x00090202, + CPU_POWERPC_604E_v24 =3D 0x00090204, + /* XXX: missing 0x000a0100 */ + /* XXX: missing 0x00093102 */ + CPU_POWERPC_604R =3D 0x000a0101, +#if 0 + CPU_POWERPC_604EV =3D xxx, /* XXX: same as 604R ? */ +#endif + /* PowerPC 740/750 cores (aka G3) */ + /* XXX: missing 0x00084202 */ + CPU_POWERPC_7x0_v10 =3D 0x00080100, + CPU_POWERPC_7x0_v20 =3D 0x00080200, + CPU_POWERPC_7x0_v21 =3D 0x00080201, + CPU_POWERPC_7x0_v22 =3D 0x00080202, + CPU_POWERPC_7x0_v30 =3D 0x00080300, + CPU_POWERPC_7x0_v31 =3D 0x00080301, + CPU_POWERPC_740E =3D 0x00080100, + CPU_POWERPC_750E =3D 0x00080200, + CPU_POWERPC_7x0P =3D 0x10080000, + /* XXX: missing 0x00087010 (CL ?) */ + CPU_POWERPC_750CL_v10 =3D 0x00087200, + CPU_POWERPC_750CL_v20 =3D 0x00087210, /* aka rev E */ + CPU_POWERPC_750CX_v10 =3D 0x00082100, + CPU_POWERPC_750CX_v20 =3D 0x00082200, + CPU_POWERPC_750CX_v21 =3D 0x00082201, + CPU_POWERPC_750CX_v22 =3D 0x00082202, + CPU_POWERPC_750CXE_v21 =3D 0x00082211, + CPU_POWERPC_750CXE_v22 =3D 0x00082212, + CPU_POWERPC_750CXE_v23 =3D 0x00082213, + CPU_POWERPC_750CXE_v24 =3D 0x00082214, + CPU_POWERPC_750CXE_v24b =3D 0x00083214, + CPU_POWERPC_750CXE_v30 =3D 0x00082310, + CPU_POWERPC_750CXE_v31 =3D 0x00082311, + CPU_POWERPC_750CXE_v31b =3D 0x00083311, + CPU_POWERPC_750CXR =3D 0x00083410, + CPU_POWERPC_750FL =3D 0x70000203, + CPU_POWERPC_750FX_v10 =3D 0x70000100, + CPU_POWERPC_750FX_v20 =3D 0x70000200, + CPU_POWERPC_750FX_v21 =3D 0x70000201, + CPU_POWERPC_750FX_v22 =3D 0x70000202, + CPU_POWERPC_750FX_v23 =3D 0x70000203, + CPU_POWERPC_750GL =3D 0x70020102, + CPU_POWERPC_750GX_v10 =3D 0x70020100, + CPU_POWERPC_750GX_v11 =3D 0x70020101, + CPU_POWERPC_750GX_v12 =3D 0x70020102, + CPU_POWERPC_750L_v20 =3D 0x00088200, + CPU_POWERPC_750L_v21 =3D 0x00088201, + CPU_POWERPC_750L_v22 =3D 0x00088202, + CPU_POWERPC_750L_v30 =3D 0x00088300, + CPU_POWERPC_750L_v32 =3D 0x00088302, + /* PowerPC 745/755 cores */ + CPU_POWERPC_7x5_v10 =3D 0x00083100, + CPU_POWERPC_7x5_v11 =3D 0x00083101, + CPU_POWERPC_7x5_v20 =3D 0x00083200, + CPU_POWERPC_7x5_v21 =3D 0x00083201, + CPU_POWERPC_7x5_v22 =3D 0x00083202, /* aka D */ + CPU_POWERPC_7x5_v23 =3D 0x00083203, /* aka E */ + CPU_POWERPC_7x5_v24 =3D 0x00083204, + CPU_POWERPC_7x5_v25 =3D 0x00083205, + CPU_POWERPC_7x5_v26 =3D 0x00083206, + CPU_POWERPC_7x5_v27 =3D 0x00083207, + CPU_POWERPC_7x5_v28 =3D 0x00083208, +#if 0 + CPU_POWERPC_7x5P =3D xxx, +#endif + /* PowerPC 74xx cores (aka G4) */ + /* XXX: missing 0x000C1101 */ + CPU_POWERPC_7400_v10 =3D 0x000C0100, + CPU_POWERPC_7400_v11 =3D 0x000C0101, + CPU_POWERPC_7400_v20 =3D 0x000C0200, + CPU_POWERPC_7400_v21 =3D 0x000C0201, + CPU_POWERPC_7400_v22 =3D 0x000C0202, + CPU_POWERPC_7400_v26 =3D 0x000C0206, + CPU_POWERPC_7400_v27 =3D 0x000C0207, + CPU_POWERPC_7400_v28 =3D 0x000C0208, + CPU_POWERPC_7400_v29 =3D 0x000C0209, + CPU_POWERPC_7410_v10 =3D 0x800C1100, + CPU_POWERPC_7410_v11 =3D 0x800C1101, + CPU_POWERPC_7410_v12 =3D 0x800C1102, /* aka C */ + CPU_POWERPC_7410_v13 =3D 0x800C1103, /* aka D */ + CPU_POWERPC_7410_v14 =3D 0x800C1104, /* aka E */ + CPU_POWERPC_7448_v10 =3D 0x80040100, + CPU_POWERPC_7448_v11 =3D 0x80040101, + CPU_POWERPC_7448_v20 =3D 0x80040200, + CPU_POWERPC_7448_v21 =3D 0x80040201, + CPU_POWERPC_7450_v10 =3D 0x80000100, + CPU_POWERPC_7450_v11 =3D 0x80000101, + CPU_POWERPC_7450_v12 =3D 0x80000102, + CPU_POWERPC_7450_v20 =3D 0x80000200, /* aka A, B, C, D: 2.= 04 */ + CPU_POWERPC_7450_v21 =3D 0x80000201, /* aka E */ + CPU_POWERPC_74x1_v23 =3D 0x80000203, /* aka G: 2.3 */ + /* XXX: this entry might be a bug in some documentation */ + CPU_POWERPC_74x1_v210 =3D 0x80000210, /* aka G: 2.3 ? */ + CPU_POWERPC_74x5_v10 =3D 0x80010100, + /* XXX: missing 0x80010200 */ + CPU_POWERPC_74x5_v21 =3D 0x80010201, /* aka C: 2.1 */ + CPU_POWERPC_74x5_v32 =3D 0x80010302, + CPU_POWERPC_74x5_v33 =3D 0x80010303, /* aka F: 3.3 */ + CPU_POWERPC_74x5_v34 =3D 0x80010304, /* aka G: 3.4 */ + CPU_POWERPC_74x7_v10 =3D 0x80020100, /* aka A: 1.0 */ + CPU_POWERPC_74x7_v11 =3D 0x80020101, /* aka B: 1.1 */ + CPU_POWERPC_74x7_v12 =3D 0x80020102, /* aka C: 1.2 */ + CPU_POWERPC_74x7A_v10 =3D 0x80030100, /* aka A: 1.0 */ + CPU_POWERPC_74x7A_v11 =3D 0x80030101, /* aka B: 1.1 */ + CPU_POWERPC_74x7A_v12 =3D 0x80030102, /* aka C: 1.2 */ + /* 64 bits PowerPC */ +#if defined(TARGET_PPC64) + CPU_POWERPC_620 =3D 0x00140000, + CPU_POWERPC_630 =3D 0x00400000, + CPU_POWERPC_631 =3D 0x00410104, + CPU_POWERPC_POWER4 =3D 0x00350000, + CPU_POWERPC_POWER4P =3D 0x00380000, + /* XXX: missing 0x003A0201 */ + CPU_POWERPC_POWER5 =3D 0x003A0203, +#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5 + CPU_POWERPC_POWER5P =3D 0x003B0000, +#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P + CPU_POWERPC_POWER6 =3D 0x003E0000, + CPU_POWERPC_POWER6_5 =3D 0x0F000001, /* POWER6 in POWER5 m= ode */ + CPU_POWERPC_POWER6A =3D 0x0F000002, + CPU_POWERPC_POWER7_v20 =3D 0x003F0200, + CPU_POWERPC_POWER7_v21 =3D 0x003F0201, + CPU_POWERPC_POWER7_v23 =3D 0x003F0203, + CPU_POWERPC_970 =3D 0x00390202, + CPU_POWERPC_970FX_v10 =3D 0x00391100, + CPU_POWERPC_970FX_v20 =3D 0x003C0200, + CPU_POWERPC_970FX_v21 =3D 0x003C0201, + CPU_POWERPC_970FX_v30 =3D 0x003C0300, + CPU_POWERPC_970FX_v31 =3D 0x003C0301, + CPU_POWERPC_970GX =3D 0x00450000, + CPU_POWERPC_970MP_v10 =3D 0x00440100, + CPU_POWERPC_970MP_v11 =3D 0x00440101, +#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32 + CPU_POWERPC_CELL_v10 =3D 0x00700100, + CPU_POWERPC_CELL_v20 =3D 0x00700400, + CPU_POWERPC_CELL_v30 =3D 0x00700500, + CPU_POWERPC_CELL_v31 =3D 0x00700501, +#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31 + CPU_POWERPC_RS64 =3D 0x00330000, + CPU_POWERPC_RS64II =3D 0x00340000, + CPU_POWERPC_RS64III =3D 0x00360000, + CPU_POWERPC_RS64IV =3D 0x00370000, +#endif /* defined(TARGET_PPC64) */ + /* Original POWER */ + /* XXX: should be POWER (RIOS), RSC3308, RSC4608, + * POWER2 (RIOS2) & RSC2 (P2SC) here + */ +#if 0 + CPU_POWER =3D xxx, /* 0x20000 ? 0x30000 for RSC= ? */ +#endif +#if 0 + CPU_POWER2 =3D xxx, /* 0x40000 ? */ +#endif + /* PA Semi core */ + CPU_POWERPC_PA6T =3D 0x00900000, +}; + +/* System version register (used on MPC 8xxx) = */ +enum { + POWERPC_SVR_NONE =3D 0x00000000, + POWERPC_SVR_5200_v10 =3D 0x80110010, + POWERPC_SVR_5200_v11 =3D 0x80110011, + POWERPC_SVR_5200_v12 =3D 0x80110012, + POWERPC_SVR_5200B_v20 =3D 0x80110020, + POWERPC_SVR_5200B_v21 =3D 0x80110021, +#define POWERPC_SVR_55xx POWERPC_SVR_5567 +#if 0 + POWERPC_SVR_5533 =3D xxx, +#endif +#if 0 + POWERPC_SVR_5534 =3D xxx, +#endif +#if 0 + POWERPC_SVR_5553 =3D xxx, +#endif +#if 0 + POWERPC_SVR_5554 =3D xxx, +#endif +#if 0 + POWERPC_SVR_5561 =3D xxx, +#endif +#if 0 + POWERPC_SVR_5565 =3D xxx, +#endif +#if 0 + POWERPC_SVR_5566 =3D xxx, +#endif +#if 0 + POWERPC_SVR_5567 =3D xxx, +#endif +#if 0 + POWERPC_SVR_8313 =3D xxx, +#endif +#if 0 + POWERPC_SVR_8313E =3D xxx, +#endif +#if 0 + POWERPC_SVR_8314 =3D xxx, +#endif +#if 0 + POWERPC_SVR_8314E =3D xxx, +#endif +#if 0 + POWERPC_SVR_8315 =3D xxx, +#endif +#if 0 + POWERPC_SVR_8315E =3D xxx, +#endif +#if 0 + POWERPC_SVR_8321 =3D xxx, +#endif +#if 0 + POWERPC_SVR_8321E =3D xxx, +#endif +#if 0 + POWERPC_SVR_8323 =3D xxx, +#endif +#if 0 + POWERPC_SVR_8323E =3D xxx, +#endif + POWERPC_SVR_8343 =3D 0x80570010, + POWERPC_SVR_8343A =3D 0x80570030, + POWERPC_SVR_8343E =3D 0x80560010, + POWERPC_SVR_8343EA =3D 0x80560030, + POWERPC_SVR_8347P =3D 0x80550010, /* PBGA package */ + POWERPC_SVR_8347T =3D 0x80530010, /* TBGA package */ + POWERPC_SVR_8347AP =3D 0x80550030, /* PBGA package */ + POWERPC_SVR_8347AT =3D 0x80530030, /* TBGA package */ + POWERPC_SVR_8347EP =3D 0x80540010, /* PBGA package */ + POWERPC_SVR_8347ET =3D 0x80520010, /* TBGA package */ + POWERPC_SVR_8347EAP =3D 0x80540030, /* PBGA package */ + POWERPC_SVR_8347EAT =3D 0x80520030, /* TBGA package */ + POWERPC_SVR_8349 =3D 0x80510010, + POWERPC_SVR_8349A =3D 0x80510030, + POWERPC_SVR_8349E =3D 0x80500010, + POWERPC_SVR_8349EA =3D 0x80500030, +#if 0 + POWERPC_SVR_8358E =3D xxx, +#endif +#if 0 + POWERPC_SVR_8360E =3D xxx, +#endif +#define POWERPC_SVR_E500 0x40000000 + POWERPC_SVR_8377 =3D 0x80C70010 | POWERPC_SVR_E500, + POWERPC_SVR_8377E =3D 0x80C60010 | POWERPC_SVR_E500, + POWERPC_SVR_8378 =3D 0x80C50010 | POWERPC_SVR_E500, + POWERPC_SVR_8378E =3D 0x80C40010 | POWERPC_SVR_E500, + POWERPC_SVR_8379 =3D 0x80C30010 | POWERPC_SVR_E500, + POWERPC_SVR_8379E =3D 0x80C00010 | POWERPC_SVR_E500, + POWERPC_SVR_8533_v10 =3D 0x80340010 | POWERPC_SVR_E500, + POWERPC_SVR_8533_v11 =3D 0x80340011 | POWERPC_SVR_E500, + POWERPC_SVR_8533E_v10 =3D 0x803C0010 | POWERPC_SVR_E500, + POWERPC_SVR_8533E_v11 =3D 0x803C0011 | POWERPC_SVR_E500, + POWERPC_SVR_8540_v10 =3D 0x80300010 | POWERPC_SVR_E500, + POWERPC_SVR_8540_v20 =3D 0x80300020 | POWERPC_SVR_E500, + POWERPC_SVR_8540_v21 =3D 0x80300021 | POWERPC_SVR_E500, + POWERPC_SVR_8541_v10 =3D 0x80720010 | POWERPC_SVR_E500, + POWERPC_SVR_8541_v11 =3D 0x80720011 | POWERPC_SVR_E500, + POWERPC_SVR_8541E_v10 =3D 0x807A0010 | POWERPC_SVR_E500, + POWERPC_SVR_8541E_v11 =3D 0x807A0011 | POWERPC_SVR_E500, + POWERPC_SVR_8543_v10 =3D 0x80320010 | POWERPC_SVR_E500, + POWERPC_SVR_8543_v11 =3D 0x80320011 | POWERPC_SVR_E500, + POWERPC_SVR_8543_v20 =3D 0x80320020 | POWERPC_SVR_E500, + POWERPC_SVR_8543_v21 =3D 0x80320021 | POWERPC_SVR_E500, + POWERPC_SVR_8543E_v10 =3D 0x803A0010 | POWERPC_SVR_E500, + POWERPC_SVR_8543E_v11 =3D 0x803A0011 | POWERPC_SVR_E500, + POWERPC_SVR_8543E_v20 =3D 0x803A0020 | POWERPC_SVR_E500, + POWERPC_SVR_8543E_v21 =3D 0x803A0021 | POWERPC_SVR_E500, + POWERPC_SVR_8544_v10 =3D 0x80340110 | POWERPC_SVR_E500, + POWERPC_SVR_8544_v11 =3D 0x80340111 | POWERPC_SVR_E500, + POWERPC_SVR_8544E_v10 =3D 0x803C0110 | POWERPC_SVR_E500, + POWERPC_SVR_8544E_v11 =3D 0x803C0111 | POWERPC_SVR_E500, + POWERPC_SVR_8545_v20 =3D 0x80310220 | POWERPC_SVR_E500, + POWERPC_SVR_8545_v21 =3D 0x80310221 | POWERPC_SVR_E500, + POWERPC_SVR_8545E_v20 =3D 0x80390220 | POWERPC_SVR_E500, + POWERPC_SVR_8545E_v21 =3D 0x80390221 | POWERPC_SVR_E500, + POWERPC_SVR_8547E_v20 =3D 0x80390120 | POWERPC_SVR_E500, + POWERPC_SVR_8547E_v21 =3D 0x80390121 | POWERPC_SVR_E500, + POWERPC_SVR_8548_v10 =3D 0x80310010 | POWERPC_SVR_E500, + POWERPC_SVR_8548_v11 =3D 0x80310011 | POWERPC_SVR_E500, + POWERPC_SVR_8548_v20 =3D 0x80310020 | POWERPC_SVR_E500, + POWERPC_SVR_8548_v21 =3D 0x80310021 | POWERPC_SVR_E500, + POWERPC_SVR_8548E_v10 =3D 0x80390010 | POWERPC_SVR_E500, + POWERPC_SVR_8548E_v11 =3D 0x80390011 | POWERPC_SVR_E500, + POWERPC_SVR_8548E_v20 =3D 0x80390020 | POWERPC_SVR_E500, + POWERPC_SVR_8548E_v21 =3D 0x80390021 | POWERPC_SVR_E500, + POWERPC_SVR_8555_v10 =3D 0x80710010 | POWERPC_SVR_E500, + POWERPC_SVR_8555_v11 =3D 0x80710011 | POWERPC_SVR_E500, + POWERPC_SVR_8555E_v10 =3D 0x80790010 | POWERPC_SVR_E500, + POWERPC_SVR_8555E_v11 =3D 0x80790011 | POWERPC_SVR_E500, + POWERPC_SVR_8560_v10 =3D 0x80700010 | POWERPC_SVR_E500, + POWERPC_SVR_8560_v20 =3D 0x80700020 | POWERPC_SVR_E500, + POWERPC_SVR_8560_v21 =3D 0x80700021 | POWERPC_SVR_E500, + POWERPC_SVR_8567 =3D 0x80750111 | POWERPC_SVR_E500, + POWERPC_SVR_8567E =3D 0x807D0111 | POWERPC_SVR_E500, + POWERPC_SVR_8568 =3D 0x80750011 | POWERPC_SVR_E500, + POWERPC_SVR_8568E =3D 0x807D0011 | POWERPC_SVR_E500, + POWERPC_SVR_8572 =3D 0x80E00010 | POWERPC_SVR_E500, + POWERPC_SVR_8572E =3D 0x80E80010 | POWERPC_SVR_E500, +#if 0 + POWERPC_SVR_8610 =3D xxx, +#endif + POWERPC_SVR_8641 =3D 0x80900021, + POWERPC_SVR_8641D =3D 0x80900121, +}; + +#endif diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 31566e0..b0d4357 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -18,24 +18,17 @@ * License along with this library; if not, see . */ =20 -/* A lot of PowerPC definition have been included here. - * Most of them are not usable for now but have been kept - * inside "#if defined(TODO) ... #endif" statements to make tests easier= . - */ - #include "disas/bfd.h" #include "exec/gdbstub.h" #include #include "kvm_ppc.h" #include "sysemu/arch_init.h" #include "sysemu/cpus.h" +#include "cpu-models.h" =20 //#define PPC_DUMP_CPU //#define PPC_DEBUG_SPR //#define PPC_DUMP_SPR_ACCESSES -#if defined(CONFIG_USER_ONLY) -#define TODO_USER_ONLY 1 -#endif =20 /* For user-mode emulation, we don't emulate any IRQ controller */ #if defined(CONFIG_USER_ONLY) @@ -4876,18 +4869,16 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data= ) /* Non-embedded PowerPC = */ =20 /* POWER : same as 601, without mfmsr, mfsr = */ -#if defined(TODO) POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); =20 dc->desc =3D "POWER"; - pcc->insns_flags =3D XXX_TODO; + /* pcc->insns_flags =3D XXX_TODO; */ /* POWER RSC (from RAD6000) */ pcc->msr_mask =3D 0x00000000FEF0ULL; } -#endif /* TODO */ =20 #define POWERPC_MSRR_601 (0x0000000000001040ULL) =20 @@ -7173,1900 +7164,6 @@ POWERPC_FAMILY(620)(ObjectClass *oc, void *data) =20 #endif /* defined (TARGET_PPC64) */ =20 -/***********************************************************************= ******/ -/* PVR definitions for most known PowerPC = */ -enum { - /* PowerPC 401 family */ - /* Generic PowerPC 401 */ -#define CPU_POWERPC_401 CPU_POWERPC_401G2 - /* PowerPC 401 cores */ - CPU_POWERPC_401A1 =3D 0x00210000, - CPU_POWERPC_401B2 =3D 0x00220000, -#if 0 - CPU_POWERPC_401B3 =3D xxx, -#endif - CPU_POWERPC_401C2 =3D 0x00230000, - CPU_POWERPC_401D2 =3D 0x00240000, - CPU_POWERPC_401E2 =3D 0x00250000, - CPU_POWERPC_401F2 =3D 0x00260000, - CPU_POWERPC_401G2 =3D 0x00270000, - /* PowerPC 401 microcontrolers */ -#if 0 - CPU_POWERPC_401GF =3D xxx, -#endif -#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2 - /* IBM Processor for Network Resources */ - CPU_POWERPC_COBRA =3D 0x10100000, /* XXX: 405 ? */ -#if 0 - CPU_POWERPC_XIPCHIP =3D xxx, -#endif - /* PowerPC 403 family */ - /* PowerPC 403 microcontrollers */ - CPU_POWERPC_403GA =3D 0x00200011, - CPU_POWERPC_403GB =3D 0x00200100, - CPU_POWERPC_403GC =3D 0x00200200, - CPU_POWERPC_403GCX =3D 0x00201400, -#if 0 - CPU_POWERPC_403GP =3D xxx, -#endif - /* PowerPC 405 family */ - /* PowerPC 405 cores */ -#if 0 - CPU_POWERPC_405A3 =3D xxx, -#endif -#if 0 - CPU_POWERPC_405A4 =3D xxx, -#endif -#if 0 - CPU_POWERPC_405B3 =3D xxx, -#endif -#if 0 - CPU_POWERPC_405B4 =3D xxx, -#endif -#if 0 - CPU_POWERPC_405C3 =3D xxx, -#endif -#if 0 - CPU_POWERPC_405C4 =3D xxx, -#endif - CPU_POWERPC_405D2 =3D 0x20010000, -#if 0 - CPU_POWERPC_405D3 =3D xxx, -#endif - CPU_POWERPC_405D4 =3D 0x41810000, -#if 0 - CPU_POWERPC_405D5 =3D xxx, -#endif -#if 0 - CPU_POWERPC_405E4 =3D xxx, -#endif -#if 0 - CPU_POWERPC_405F4 =3D xxx, -#endif -#if 0 - CPU_POWERPC_405F5 =3D xxx, -#endif -#if 0 - CPU_POWERPC_405F6 =3D xxx, -#endif - /* PowerPC 405 microcontrolers */ - /* XXX: missing 0x200108a0 */ - CPU_POWERPC_405CRa =3D 0x40110041, - CPU_POWERPC_405CRb =3D 0x401100C5, - CPU_POWERPC_405CRc =3D 0x40110145, - CPU_POWERPC_405EP =3D 0x51210950, -#if 0 - CPU_POWERPC_405EXr =3D xxx, -#endif - CPU_POWERPC_405EZ =3D 0x41511460, /* 0x51210950 ? */ -#if 0 - CPU_POWERPC_405FX =3D xxx, -#endif - CPU_POWERPC_405GPa =3D 0x40110000, - CPU_POWERPC_405GPb =3D 0x40110040, - CPU_POWERPC_405GPc =3D 0x40110082, - CPU_POWERPC_405GPd =3D 0x401100C4, - CPU_POWERPC_405GPR =3D 0x50910951, -#if 0 - CPU_POWERPC_405H =3D xxx, -#endif -#if 0 - CPU_POWERPC_405L =3D xxx, -#endif - CPU_POWERPC_405LP =3D 0x41F10000, -#if 0 - CPU_POWERPC_405PM =3D xxx, -#endif -#if 0 - CPU_POWERPC_405PS =3D xxx, -#endif -#if 0 - CPU_POWERPC_405S =3D xxx, -#endif - /* IBM network processors */ - CPU_POWERPC_NPE405H =3D 0x414100C0, - CPU_POWERPC_NPE405H2 =3D 0x41410140, - CPU_POWERPC_NPE405L =3D 0x416100C0, - CPU_POWERPC_NPE4GS3 =3D 0x40B10000, -#if 0 - CPU_POWERPC_NPCxx1 =3D xxx, -#endif -#if 0 - CPU_POWERPC_NPR161 =3D xxx, -#endif -#if 0 - CPU_POWERPC_LC77700 =3D xxx, -#endif - /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */ -#if 0 - CPU_POWERPC_STB01000 =3D xxx, -#endif -#if 0 - CPU_POWERPC_STB01010 =3D xxx, -#endif -#if 0 - CPU_POWERPC_STB0210 =3D xxx, /* 401B3 */ -#endif - CPU_POWERPC_STB03 =3D 0x40310000, /* 0x40130000 ? */ -#if 0 - CPU_POWERPC_STB043 =3D xxx, -#endif -#if 0 - CPU_POWERPC_STB045 =3D xxx, -#endif - CPU_POWERPC_STB04 =3D 0x41810000, - CPU_POWERPC_STB25 =3D 0x51510950, -#if 0 - CPU_POWERPC_STB130 =3D xxx, -#endif - /* Xilinx cores */ - CPU_POWERPC_X2VP4 =3D 0x20010820, - CPU_POWERPC_X2VP20 =3D 0x20010860, -#if 0 - CPU_POWERPC_ZL10310 =3D xxx, -#endif -#if 0 - CPU_POWERPC_ZL10311 =3D xxx, -#endif -#if 0 - CPU_POWERPC_ZL10320 =3D xxx, -#endif -#if 0 - CPU_POWERPC_ZL10321 =3D xxx, -#endif - /* PowerPC 440 family */ - /* Generic PowerPC 440 */ -#define CPU_POWERPC_440 CPU_POWERPC_440GXf - /* PowerPC 440 cores */ -#if 0 - CPU_POWERPC_440A4 =3D xxx, -#endif - CPU_POWERPC_440_XILINX =3D 0x7ff21910, -#if 0 - CPU_POWERPC_440A5 =3D xxx, -#endif -#if 0 - CPU_POWERPC_440B4 =3D xxx, -#endif -#if 0 - CPU_POWERPC_440F5 =3D xxx, -#endif -#if 0 - CPU_POWERPC_440G5 =3D xxx, -#endif -#if 0 - CPU_POWERPC_440H4 =3D xxx, -#endif -#if 0 - CPU_POWERPC_440H6 =3D xxx, -#endif - /* PowerPC 440 microcontrolers */ - CPU_POWERPC_440EPa =3D 0x42221850, - CPU_POWERPC_440EPb =3D 0x422218D3, - CPU_POWERPC_440GPb =3D 0x40120440, - CPU_POWERPC_440GPc =3D 0x40120481, -#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb - CPU_POWERPC_440GRX =3D 0x200008D0, -#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX - CPU_POWERPC_440GXa =3D 0x51B21850, - CPU_POWERPC_440GXb =3D 0x51B21851, - CPU_POWERPC_440GXc =3D 0x51B21892, - CPU_POWERPC_440GXf =3D 0x51B21894, -#if 0 - CPU_POWERPC_440S =3D xxx, -#endif - CPU_POWERPC_440SP =3D 0x53221850, - CPU_POWERPC_440SP2 =3D 0x53221891, - CPU_POWERPC_440SPE =3D 0x53421890, - /* PowerPC 460 family */ -#if 0 - /* Generic PowerPC 464 */ -#define CPU_POWERPC_464 CPU_POWERPC_464H90 -#endif - /* PowerPC 464 microcontrolers */ -#if 0 - CPU_POWERPC_464H90 =3D xxx, -#endif -#if 0 - CPU_POWERPC_464H90FP =3D xxx, -#endif - /* Freescale embedded PowerPC cores */ - /* PowerPC MPC 5xx cores (aka RCPU) */ - CPU_POWERPC_MPC5xx =3D 0x00020020, - /* PowerPC MPC 8xx cores (aka PowerQUICC) */ - CPU_POWERPC_MPC8xx =3D 0x00500000, - /* G2 cores (aka PowerQUICC-II) */ - CPU_POWERPC_G2 =3D 0x00810011, - CPU_POWERPC_G2H4 =3D 0x80811010, - CPU_POWERPC_G2gp =3D 0x80821010, - CPU_POWERPC_G2ls =3D 0x90810010, - CPU_POWERPC_MPC603 =3D 0x00810100, - CPU_POWERPC_G2_HIP3 =3D 0x00810101, - CPU_POWERPC_G2_HIP4 =3D 0x80811014, - /* G2_LE core (aka PowerQUICC-II) */ - CPU_POWERPC_G2LE =3D 0x80820010, - CPU_POWERPC_G2LEgp =3D 0x80822010, - CPU_POWERPC_G2LEls =3D 0xA0822010, - CPU_POWERPC_G2LEgp1 =3D 0x80822011, - CPU_POWERPC_G2LEgp3 =3D 0x80822013, - /* MPC52xx microcontrollers */ - /* XXX: MPC 5121 ? */ -#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1 -#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1 -#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1 -#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1 -#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1 - /* e200 family */ - /* e200 cores */ -#if 0 - CPU_POWERPC_e200z0 =3D xxx, -#endif -#if 0 - CPU_POWERPC_e200z1 =3D xxx, -#endif -#if 0 /* ? */ - CPU_POWERPC_e200z3 =3D 0x81120000, -#endif - CPU_POWERPC_e200z5 =3D 0x81000000, - CPU_POWERPC_e200z6 =3D 0x81120000, - /* MPC55xx microcontrollers */ -#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567 -#if 0 -#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1 -#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0 -#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1 -#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1 -#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0 -#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1 -#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1 -#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1 -#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0 -#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1 -#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1 -#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0 -#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1 -#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1 -#endif -#if 0 -#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3 -#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3 -#endif -#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6 -#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6 -#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6 -#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6 -#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6 -#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6 - /* e300 family */ - /* e300 cores */ - CPU_POWERPC_e300c1 =3D 0x00830010, - CPU_POWERPC_e300c2 =3D 0x00840010, - CPU_POWERPC_e300c3 =3D 0x00850010, - CPU_POWERPC_e300c4 =3D 0x00860010, - /* MPC83xx microcontrollers */ -#define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3 -#define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2 -#define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1 -#define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1 -#define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1 -#define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4 - /* e500 family */ - /* e500 cores */ -#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22 - CPU_POWERPC_e500v1_v10 =3D 0x80200010, - CPU_POWERPC_e500v1_v20 =3D 0x80200020, - CPU_POWERPC_e500v2_v10 =3D 0x80210010, - CPU_POWERPC_e500v2_v11 =3D 0x80210011, - CPU_POWERPC_e500v2_v20 =3D 0x80210020, - CPU_POWERPC_e500v2_v21 =3D 0x80210021, - CPU_POWERPC_e500v2_v22 =3D 0x80210022, - CPU_POWERPC_e500v2_v30 =3D 0x80210030, - CPU_POWERPC_e500mc =3D 0x80230020, - CPU_POWERPC_e5500 =3D 0x80240020, - /* MPC85xx microcontrollers */ -#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21 -#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22 -#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21 -#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22 -#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10 -#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20 -#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20 -#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20 -#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20 -#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20 -#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20 -#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10 -#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11 -#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20 -#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21 -#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10 -#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11 -#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20 -#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21 -#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21 -#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22 -#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22 -#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21 -#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10 -#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20 -#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21 -#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10 -#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20 -#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21 -#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10 -#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20 -#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21 -#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10 -#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11 -#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20 -#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21 -#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10 -#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11 -#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20 -#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21 -#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10 -#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11 -#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10 -#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11 -#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10 -#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20 -#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21 -#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22 -#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22 -#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22 -#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22 -#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30 -#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30 - /* e600 family */ - /* e600 cores */ - CPU_POWERPC_e600 =3D 0x80040010, - /* MPC86xx microcontrollers */ -#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600 -#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600 -#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600 - /* PowerPC 6xx cores */ - CPU_POWERPC_601_v0 =3D 0x00010001, - CPU_POWERPC_601_v1 =3D 0x00010001, - CPU_POWERPC_601_v2 =3D 0x00010002, - CPU_POWERPC_602 =3D 0x00050100, - CPU_POWERPC_603 =3D 0x00030100, - CPU_POWERPC_603E_v11 =3D 0x00060101, - CPU_POWERPC_603E_v12 =3D 0x00060102, - CPU_POWERPC_603E_v13 =3D 0x00060103, - CPU_POWERPC_603E_v14 =3D 0x00060104, - CPU_POWERPC_603E_v22 =3D 0x00060202, - CPU_POWERPC_603E_v3 =3D 0x00060300, - CPU_POWERPC_603E_v4 =3D 0x00060400, - CPU_POWERPC_603E_v41 =3D 0x00060401, - CPU_POWERPC_603E7t =3D 0x00071201, - CPU_POWERPC_603E7v =3D 0x00070100, - CPU_POWERPC_603E7v1 =3D 0x00070101, - CPU_POWERPC_603E7v2 =3D 0x00070201, - CPU_POWERPC_603E7 =3D 0x00070200, - CPU_POWERPC_603P =3D 0x00070000, - /* XXX: missing 0x00040303 (604) */ - CPU_POWERPC_604 =3D 0x00040103, - /* XXX: missing 0x00091203 */ - /* XXX: missing 0x00092110 */ - /* XXX: missing 0x00092120 */ - CPU_POWERPC_604E_v10 =3D 0x00090100, - CPU_POWERPC_604E_v22 =3D 0x00090202, - CPU_POWERPC_604E_v24 =3D 0x00090204, - /* XXX: missing 0x000a0100 */ - /* XXX: missing 0x00093102 */ - CPU_POWERPC_604R =3D 0x000a0101, -#if 0 - CPU_POWERPC_604EV =3D xxx, /* XXX: same as 604R ? */ -#endif - /* PowerPC 740/750 cores (aka G3) */ - /* XXX: missing 0x00084202 */ - CPU_POWERPC_7x0_v10 =3D 0x00080100, - CPU_POWERPC_7x0_v20 =3D 0x00080200, - CPU_POWERPC_7x0_v21 =3D 0x00080201, - CPU_POWERPC_7x0_v22 =3D 0x00080202, - CPU_POWERPC_7x0_v30 =3D 0x00080300, - CPU_POWERPC_7x0_v31 =3D 0x00080301, - CPU_POWERPC_740E =3D 0x00080100, - CPU_POWERPC_750E =3D 0x00080200, - CPU_POWERPC_7x0P =3D 0x10080000, - /* XXX: missing 0x00087010 (CL ?) */ - CPU_POWERPC_750CL_v10 =3D 0x00087200, - CPU_POWERPC_750CL_v20 =3D 0x00087210, /* aka rev E */ - CPU_POWERPC_750CX_v10 =3D 0x00082100, - CPU_POWERPC_750CX_v20 =3D 0x00082200, - CPU_POWERPC_750CX_v21 =3D 0x00082201, - CPU_POWERPC_750CX_v22 =3D 0x00082202, - CPU_POWERPC_750CXE_v21 =3D 0x00082211, - CPU_POWERPC_750CXE_v22 =3D 0x00082212, - CPU_POWERPC_750CXE_v23 =3D 0x00082213, - CPU_POWERPC_750CXE_v24 =3D 0x00082214, - CPU_POWERPC_750CXE_v24b =3D 0x00083214, - CPU_POWERPC_750CXE_v30 =3D 0x00082310, - CPU_POWERPC_750CXE_v31 =3D 0x00082311, - CPU_POWERPC_750CXE_v31b =3D 0x00083311, - CPU_POWERPC_750CXR =3D 0x00083410, - CPU_POWERPC_750FL =3D 0x70000203, - CPU_POWERPC_750FX_v10 =3D 0x70000100, - CPU_POWERPC_750FX_v20 =3D 0x70000200, - CPU_POWERPC_750FX_v21 =3D 0x70000201, - CPU_POWERPC_750FX_v22 =3D 0x70000202, - CPU_POWERPC_750FX_v23 =3D 0x70000203, - CPU_POWERPC_750GL =3D 0x70020102, - CPU_POWERPC_750GX_v10 =3D 0x70020100, - CPU_POWERPC_750GX_v11 =3D 0x70020101, - CPU_POWERPC_750GX_v12 =3D 0x70020102, - CPU_POWERPC_750L_v20 =3D 0x00088200, - CPU_POWERPC_750L_v21 =3D 0x00088201, - CPU_POWERPC_750L_v22 =3D 0x00088202, - CPU_POWERPC_750L_v30 =3D 0x00088300, - CPU_POWERPC_750L_v32 =3D 0x00088302, - /* PowerPC 745/755 cores */ - CPU_POWERPC_7x5_v10 =3D 0x00083100, - CPU_POWERPC_7x5_v11 =3D 0x00083101, - CPU_POWERPC_7x5_v20 =3D 0x00083200, - CPU_POWERPC_7x5_v21 =3D 0x00083201, - CPU_POWERPC_7x5_v22 =3D 0x00083202, /* aka D */ - CPU_POWERPC_7x5_v23 =3D 0x00083203, /* aka E */ - CPU_POWERPC_7x5_v24 =3D 0x00083204, - CPU_POWERPC_7x5_v25 =3D 0x00083205, - CPU_POWERPC_7x5_v26 =3D 0x00083206, - CPU_POWERPC_7x5_v27 =3D 0x00083207, - CPU_POWERPC_7x5_v28 =3D 0x00083208, -#if 0 - CPU_POWERPC_7x5P =3D xxx, -#endif - /* PowerPC 74xx cores (aka G4) */ - /* XXX: missing 0x000C1101 */ - CPU_POWERPC_7400_v10 =3D 0x000C0100, - CPU_POWERPC_7400_v11 =3D 0x000C0101, - CPU_POWERPC_7400_v20 =3D 0x000C0200, - CPU_POWERPC_7400_v21 =3D 0x000C0201, - CPU_POWERPC_7400_v22 =3D 0x000C0202, - CPU_POWERPC_7400_v26 =3D 0x000C0206, - CPU_POWERPC_7400_v27 =3D 0x000C0207, - CPU_POWERPC_7400_v28 =3D 0x000C0208, - CPU_POWERPC_7400_v29 =3D 0x000C0209, - CPU_POWERPC_7410_v10 =3D 0x800C1100, - CPU_POWERPC_7410_v11 =3D 0x800C1101, - CPU_POWERPC_7410_v12 =3D 0x800C1102, /* aka C */ - CPU_POWERPC_7410_v13 =3D 0x800C1103, /* aka D */ - CPU_POWERPC_7410_v14 =3D 0x800C1104, /* aka E */ - CPU_POWERPC_7448_v10 =3D 0x80040100, - CPU_POWERPC_7448_v11 =3D 0x80040101, - CPU_POWERPC_7448_v20 =3D 0x80040200, - CPU_POWERPC_7448_v21 =3D 0x80040201, - CPU_POWERPC_7450_v10 =3D 0x80000100, - CPU_POWERPC_7450_v11 =3D 0x80000101, - CPU_POWERPC_7450_v12 =3D 0x80000102, - CPU_POWERPC_7450_v20 =3D 0x80000200, /* aka A, B, C, D: 2.= 04 */ - CPU_POWERPC_7450_v21 =3D 0x80000201, /* aka E */ - CPU_POWERPC_74x1_v23 =3D 0x80000203, /* aka G: 2.3 */ - /* XXX: this entry might be a bug in some documentation */ - CPU_POWERPC_74x1_v210 =3D 0x80000210, /* aka G: 2.3 ? */ - CPU_POWERPC_74x5_v10 =3D 0x80010100, - /* XXX: missing 0x80010200 */ - CPU_POWERPC_74x5_v21 =3D 0x80010201, /* aka C: 2.1 */ - CPU_POWERPC_74x5_v32 =3D 0x80010302, - CPU_POWERPC_74x5_v33 =3D 0x80010303, /* aka F: 3.3 */ - CPU_POWERPC_74x5_v34 =3D 0x80010304, /* aka G: 3.4 */ - CPU_POWERPC_74x7_v10 =3D 0x80020100, /* aka A: 1.0 */ - CPU_POWERPC_74x7_v11 =3D 0x80020101, /* aka B: 1.1 */ - CPU_POWERPC_74x7_v12 =3D 0x80020102, /* aka C: 1.2 */ - CPU_POWERPC_74x7A_v10 =3D 0x80030100, /* aka A: 1.0 */ - CPU_POWERPC_74x7A_v11 =3D 0x80030101, /* aka B: 1.1 */ - CPU_POWERPC_74x7A_v12 =3D 0x80030102, /* aka C: 1.2 */ - /* 64 bits PowerPC */ -#if defined(TARGET_PPC64) - CPU_POWERPC_620 =3D 0x00140000, - CPU_POWERPC_630 =3D 0x00400000, - CPU_POWERPC_631 =3D 0x00410104, - CPU_POWERPC_POWER4 =3D 0x00350000, - CPU_POWERPC_POWER4P =3D 0x00380000, - /* XXX: missing 0x003A0201 */ - CPU_POWERPC_POWER5 =3D 0x003A0203, -#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5 - CPU_POWERPC_POWER5P =3D 0x003B0000, -#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P - CPU_POWERPC_POWER6 =3D 0x003E0000, - CPU_POWERPC_POWER6_5 =3D 0x0F000001, /* POWER6 in POWER5 m= ode */ - CPU_POWERPC_POWER6A =3D 0x0F000002, - CPU_POWERPC_POWER7_v20 =3D 0x003F0200, - CPU_POWERPC_POWER7_v21 =3D 0x003F0201, - CPU_POWERPC_POWER7_v23 =3D 0x003F0203, - CPU_POWERPC_970 =3D 0x00390202, - CPU_POWERPC_970FX_v10 =3D 0x00391100, - CPU_POWERPC_970FX_v20 =3D 0x003C0200, - CPU_POWERPC_970FX_v21 =3D 0x003C0201, - CPU_POWERPC_970FX_v30 =3D 0x003C0300, - CPU_POWERPC_970FX_v31 =3D 0x003C0301, - CPU_POWERPC_970GX =3D 0x00450000, - CPU_POWERPC_970MP_v10 =3D 0x00440100, - CPU_POWERPC_970MP_v11 =3D 0x00440101, -#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32 - CPU_POWERPC_CELL_v10 =3D 0x00700100, - CPU_POWERPC_CELL_v20 =3D 0x00700400, - CPU_POWERPC_CELL_v30 =3D 0x00700500, - CPU_POWERPC_CELL_v31 =3D 0x00700501, -#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31 - CPU_POWERPC_RS64 =3D 0x00330000, - CPU_POWERPC_RS64II =3D 0x00340000, - CPU_POWERPC_RS64III =3D 0x00360000, - CPU_POWERPC_RS64IV =3D 0x00370000, -#endif /* defined(TARGET_PPC64) */ - /* Original POWER */ - /* XXX: should be POWER (RIOS), RSC3308, RSC4608, - * POWER2 (RIOS2) & RSC2 (P2SC) here - */ -#if 0 - CPU_POWER =3D xxx, /* 0x20000 ? 0x30000 for RSC= ? */ -#endif -#if 0 - CPU_POWER2 =3D xxx, /* 0x40000 ? */ -#endif - /* PA Semi core */ - CPU_POWERPC_PA6T =3D 0x00900000, -}; - -/* System version register (used on MPC 8xxx) = */ -enum { - POWERPC_SVR_NONE =3D 0x00000000, - POWERPC_SVR_5200_v10 =3D 0x80110010, - POWERPC_SVR_5200_v11 =3D 0x80110011, - POWERPC_SVR_5200_v12 =3D 0x80110012, - POWERPC_SVR_5200B_v20 =3D 0x80110020, - POWERPC_SVR_5200B_v21 =3D 0x80110021, -#define POWERPC_SVR_55xx POWERPC_SVR_5567 -#if 0 - POWERPC_SVR_5533 =3D xxx, -#endif -#if 0 - POWERPC_SVR_5534 =3D xxx, -#endif -#if 0 - POWERPC_SVR_5553 =3D xxx, -#endif -#if 0 - POWERPC_SVR_5554 =3D xxx, -#endif -#if 0 - POWERPC_SVR_5561 =3D xxx, -#endif -#if 0 - POWERPC_SVR_5565 =3D xxx, -#endif -#if 0 - POWERPC_SVR_5566 =3D xxx, -#endif -#if 0 - POWERPC_SVR_5567 =3D xxx, -#endif -#if 0 - POWERPC_SVR_8313 =3D xxx, -#endif -#if 0 - POWERPC_SVR_8313E =3D xxx, -#endif -#if 0 - POWERPC_SVR_8314 =3D xxx, -#endif -#if 0 - POWERPC_SVR_8314E =3D xxx, -#endif -#if 0 - POWERPC_SVR_8315 =3D xxx, -#endif -#if 0 - POWERPC_SVR_8315E =3D xxx, -#endif -#if 0 - POWERPC_SVR_8321 =3D xxx, -#endif -#if 0 - POWERPC_SVR_8321E =3D xxx, -#endif -#if 0 - POWERPC_SVR_8323 =3D xxx, -#endif -#if 0 - POWERPC_SVR_8323E =3D xxx, -#endif - POWERPC_SVR_8343 =3D 0x80570010, - POWERPC_SVR_8343A =3D 0x80570030, - POWERPC_SVR_8343E =3D 0x80560010, - POWERPC_SVR_8343EA =3D 0x80560030, - POWERPC_SVR_8347P =3D 0x80550010, /* PBGA package */ - POWERPC_SVR_8347T =3D 0x80530010, /* TBGA package */ - POWERPC_SVR_8347AP =3D 0x80550030, /* PBGA package */ - POWERPC_SVR_8347AT =3D 0x80530030, /* TBGA package */ - POWERPC_SVR_8347EP =3D 0x80540010, /* PBGA package */ - POWERPC_SVR_8347ET =3D 0x80520010, /* TBGA package */ - POWERPC_SVR_8347EAP =3D 0x80540030, /* PBGA package */ - POWERPC_SVR_8347EAT =3D 0x80520030, /* TBGA package */ - POWERPC_SVR_8349 =3D 0x80510010, - POWERPC_SVR_8349A =3D 0x80510030, - POWERPC_SVR_8349E =3D 0x80500010, - POWERPC_SVR_8349EA =3D 0x80500030, -#if 0 - POWERPC_SVR_8358E =3D xxx, -#endif -#if 0 - POWERPC_SVR_8360E =3D xxx, -#endif -#define POWERPC_SVR_E500 0x40000000 - POWERPC_SVR_8377 =3D 0x80C70010 | POWERPC_SVR_E500, - POWERPC_SVR_8377E =3D 0x80C60010 | POWERPC_SVR_E500, - POWERPC_SVR_8378 =3D 0x80C50010 | POWERPC_SVR_E500, - POWERPC_SVR_8378E =3D 0x80C40010 | POWERPC_SVR_E500, - POWERPC_SVR_8379 =3D 0x80C30010 | POWERPC_SVR_E500, - POWERPC_SVR_8379E =3D 0x80C00010 | POWERPC_SVR_E500, - POWERPC_SVR_8533_v10 =3D 0x80340010 | POWERPC_SVR_E500, - POWERPC_SVR_8533_v11 =3D 0x80340011 | POWERPC_SVR_E500, - POWERPC_SVR_8533E_v10 =3D 0x803C0010 | POWERPC_SVR_E500, - POWERPC_SVR_8533E_v11 =3D 0x803C0011 | POWERPC_SVR_E500, - POWERPC_SVR_8540_v10 =3D 0x80300010 | POWERPC_SVR_E500, - POWERPC_SVR_8540_v20 =3D 0x80300020 | POWERPC_SVR_E500, - POWERPC_SVR_8540_v21 =3D 0x80300021 | POWERPC_SVR_E500, - POWERPC_SVR_8541_v10 =3D 0x80720010 | POWERPC_SVR_E500, - POWERPC_SVR_8541_v11 =3D 0x80720011 | POWERPC_SVR_E500, - POWERPC_SVR_8541E_v10 =3D 0x807A0010 | POWERPC_SVR_E500, - POWERPC_SVR_8541E_v11 =3D 0x807A0011 | POWERPC_SVR_E500, - POWERPC_SVR_8543_v10 =3D 0x80320010 | POWERPC_SVR_E500, - POWERPC_SVR_8543_v11 =3D 0x80320011 | POWERPC_SVR_E500, - POWERPC_SVR_8543_v20 =3D 0x80320020 | POWERPC_SVR_E500, - POWERPC_SVR_8543_v21 =3D 0x80320021 | POWERPC_SVR_E500, - POWERPC_SVR_8543E_v10 =3D 0x803A0010 | POWERPC_SVR_E500, - POWERPC_SVR_8543E_v11 =3D 0x803A0011 | POWERPC_SVR_E500, - POWERPC_SVR_8543E_v20 =3D 0x803A0020 | POWERPC_SVR_E500, - POWERPC_SVR_8543E_v21 =3D 0x803A0021 | POWERPC_SVR_E500, - POWERPC_SVR_8544_v10 =3D 0x80340110 | POWERPC_SVR_E500, - POWERPC_SVR_8544_v11 =3D 0x80340111 | POWERPC_SVR_E500, - POWERPC_SVR_8544E_v10 =3D 0x803C0110 | POWERPC_SVR_E500, - POWERPC_SVR_8544E_v11 =3D 0x803C0111 | POWERPC_SVR_E500, - POWERPC_SVR_8545_v20 =3D 0x80310220 | POWERPC_SVR_E500, - POWERPC_SVR_8545_v21 =3D 0x80310221 | POWERPC_SVR_E500, - POWERPC_SVR_8545E_v20 =3D 0x80390220 | POWERPC_SVR_E500, - POWERPC_SVR_8545E_v21 =3D 0x80390221 | POWERPC_SVR_E500, - POWERPC_SVR_8547E_v20 =3D 0x80390120 | POWERPC_SVR_E500, - POWERPC_SVR_8547E_v21 =3D 0x80390121 | POWERPC_SVR_E500, - POWERPC_SVR_8548_v10 =3D 0x80310010 | POWERPC_SVR_E500, - POWERPC_SVR_8548_v11 =3D 0x80310011 | POWERPC_SVR_E500, - POWERPC_SVR_8548_v20 =3D 0x80310020 | POWERPC_SVR_E500, - POWERPC_SVR_8548_v21 =3D 0x80310021 | POWERPC_SVR_E500, - POWERPC_SVR_8548E_v10 =3D 0x80390010 | POWERPC_SVR_E500, - POWERPC_SVR_8548E_v11 =3D 0x80390011 | POWERPC_SVR_E500, - POWERPC_SVR_8548E_v20 =3D 0x80390020 | POWERPC_SVR_E500, - POWERPC_SVR_8548E_v21 =3D 0x80390021 | POWERPC_SVR_E500, - POWERPC_SVR_8555_v10 =3D 0x80710010 | POWERPC_SVR_E500, - POWERPC_SVR_8555_v11 =3D 0x80710011 | POWERPC_SVR_E500, - POWERPC_SVR_8555E_v10 =3D 0x80790010 | POWERPC_SVR_E500, - POWERPC_SVR_8555E_v11 =3D 0x80790011 | POWERPC_SVR_E500, - POWERPC_SVR_8560_v10 =3D 0x80700010 | POWERPC_SVR_E500, - POWERPC_SVR_8560_v20 =3D 0x80700020 | POWERPC_SVR_E500, - POWERPC_SVR_8560_v21 =3D 0x80700021 | POWERPC_SVR_E500, - POWERPC_SVR_8567 =3D 0x80750111 | POWERPC_SVR_E500, - POWERPC_SVR_8567E =3D 0x807D0111 | POWERPC_SVR_E500, - POWERPC_SVR_8568 =3D 0x80750011 | POWERPC_SVR_E500, - POWERPC_SVR_8568E =3D 0x807D0011 | POWERPC_SVR_E500, - POWERPC_SVR_8572 =3D 0x80E00010 | POWERPC_SVR_E500, - POWERPC_SVR_8572E =3D 0x80E80010 | POWERPC_SVR_E500, -#if 0 - POWERPC_SVR_8610 =3D xxx, -#endif - POWERPC_SVR_8641 =3D 0x80900021, - POWERPC_SVR_8641D =3D 0x80900121, -}; - -/***********************************************************************= ****/ -/* PowerPC CPU definitions = */ -#define POWERPC_DEF_PREFIX(pvr, svr, type) = \ - glue(glue(glue(glue(pvr, _), svr), _), type) -#define POWERPC_DEF_SVR(_name, _desc, _pvr, _svr, _type) = \ - static void = \ - glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init) = \ - (ObjectClass *oc, void *data) = \ - { = \ - DeviceClass *dc =3D DEVICE_CLASS(oc); = \ - PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); = \ - = \ - pcc->pvr =3D _pvr; = \ - pcc->svr =3D _svr; = \ - dc->desc =3D _desc; = \ - } = \ - = \ - static const TypeInfo = \ - glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info) =3D { = \ - .name =3D _name "-" TYPE_POWERPC_CPU, = \ - .parent =3D stringify(_type) "-family-" TYPE_POWERPC_CPU, = \ - .class_init =3D = \ - glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init)= , \ - }; = \ - = \ - static void = \ - glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types)(voi= d) \ - { = \ - type_register_static( = \ - &glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info)= ); \ - } = \ - = \ - type_init( = \ - glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types)= ) - -#define POWERPC_DEF(_name, _pvr, _type, _desc) = \ - POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type) - - /* Embedded PowerPC = */ - /* PowerPC 401 family = */ - POWERPC_DEF("401", CPU_POWERPC_401, 401= , - "Generic PowerPC 401") - /* PowerPC 401 cores = */ - POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401= , - "PowerPC 401A1") - POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401= x2, - "PowerPC 401B2") -#if defined(TODO) - POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401= x3, - "PowerPC 401B3") -#endif - POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401= x2, - "PowerPC 401C2") - POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401= x2, - "PowerPC 401D2") - POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401= x2, - "PowerPC 401E2") - POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401= x2, - "PowerPC 401F2") - /* XXX: to be checked */ - POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401= x2, - "PowerPC 401G2") - /* PowerPC 401 microcontrolers = */ -#if defined(TODO) - POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401= , - "PowerPC 401GF") -#endif - POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP= 480, - "IOP480 (401 microcontroller)") - POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401= , - "IBM Processor for Network Resources") -#if defined(TODO) - POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401= , - NULL) -#endif - /* PowerPC 403 family = */ - /* PowerPC 403 microcontrolers = */ - POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403= , - "PowerPC 403 GA") - POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403= , - "PowerPC 403 GB") - POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403= , - "PowerPC 403 GC") - POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403= GCX, - "PowerPC 403 GCX") -#if defined(TODO) - POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403= , - "PowerPC 403 GP") -#endif - /* PowerPC 405 family = */ - /* PowerPC 405 cores = */ -#if defined(TODO) - POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405= , - "PowerPC 405 A3") -#endif -#if defined(TODO) - POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405= , - "PowerPC 405 A4") -#endif -#if defined(TODO) - POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405= , - "PowerPC 405 B3") -#endif -#if defined(TODO) - POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405= , - "PowerPC 405 B4") -#endif -#if defined(TODO) - POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405= , - "PowerPC 405 C3") -#endif -#if defined(TODO) - POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405= , - "PowerPC 405 C4") -#endif - POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405= , - "PowerPC 405 D2") -#if defined(TODO) - POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405= , - "PowerPC 405 D3") -#endif - POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405= , - "PowerPC 405 D4") -#if defined(TODO) - POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405= , - "PowerPC 405 D5") -#endif -#if defined(TODO) - POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405= , - "PowerPC 405 E4") -#endif -#if defined(TODO) - POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405= , - "PowerPC 405 F4") -#endif -#if defined(TODO) - POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405= , - "PowerPC 405 F5") -#endif -#if defined(TODO) - POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405= , - "PowerPC 405 F6") -#endif - /* PowerPC 405 microcontrolers = */ - POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405= , - "PowerPC 405 CRa") - POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405= , - "PowerPC 405 CRb") - POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405= , - "PowerPC 405 CRc") - POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405= , - "PowerPC 405 EP") -#if defined(TODO) - POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405= , - "PowerPC 405 EXr") -#endif - POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405= , - "PowerPC 405 EZ") -#if defined(TODO) - POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405= , - "PowerPC 405 FX") -#endif - POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405= , - "PowerPC 405 GPa") - POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405= , - "PowerPC 405 GPb") - POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405= , - "PowerPC 405 GPc") - POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405= , - "PowerPC 405 GPd") - POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405= , - "PowerPC 405 GPR") -#if defined(TODO) - POWERPC_DEF("405H", CPU_POWERPC_405H, 405= , - "PowerPC 405 H") -#endif -#if defined(TODO) - POWERPC_DEF("405L", CPU_POWERPC_405L, 405= , - "PowerPC 405 L") -#endif - POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405= , - "PowerPC 405 LP") -#if defined(TODO) - POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405= , - "PowerPC 405 PM") -#endif -#if defined(TODO) - POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405= , - "PowerPC 405 PS") -#endif -#if defined(TODO) - POWERPC_DEF("405S", CPU_POWERPC_405S, 405= , - "PowerPC 405 S") -#endif - POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405= , - "Npe405 H") - POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405= , - "Npe405 H2") - POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405= , - "Npe405 L") - POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405= , - "Npe4GS3") -#if defined(TODO) - POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405= , - NULL) -#endif -#if defined(TODO) - POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405= , - NULL) -#endif -#if defined(TODO) - POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405= , - "PowerPC LC77700 (Sanyo)") -#endif - /* PowerPC 401/403/405 based set-top-box microcontrolers = */ -#if defined(TODO) - POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401= x2, - "STB010000") -#endif -#if defined(TODO) - POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401= x2, - "STB01010") -#endif -#if defined(TODO) - POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401= x3, - "STB0210") -#endif - POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405= , - "STB03xx") -#if defined(TODO) - POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405= , - "STB043x") -#endif -#if defined(TODO) - POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405= , - "STB045x") -#endif - POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405= , - "STB04xx") - POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405= , - "STB25xx") -#if defined(TODO) - POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405= , - "STB130") -#endif - /* Xilinx PowerPC 405 cores = */ - POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405= , - NULL) - POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405= , - NULL) -#if defined(TODO) - POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405= , - "Zarlink ZL10310") -#endif -#if defined(TODO) - POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405= , - "Zarlink ZL10311") -#endif -#if defined(TODO) - POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405= , - "Zarlink ZL10320") -#endif -#if defined(TODO) - POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405= , - "Zarlink ZL10321") -#endif - /* PowerPC 440 family = */ -#if defined(TODO_USER_ONLY) - POWERPC_DEF("440", CPU_POWERPC_440, 440= GP, - "Generic PowerPC 440") -#endif - /* PowerPC 440 cores = */ -#if defined(TODO) - POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440= x4, - "PowerPC 440 A4") -#endif - POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440= x5, - "PowerPC 440 Xilinx 5") -#if defined(TODO) - POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440= x5, - "PowerPC 440 A5") -#endif -#if defined(TODO) - POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440= x4, - "PowerPC 440 B4") -#endif -#if defined(TODO) - POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440= x4, - "PowerPC 440 G4") -#endif -#if defined(TODO) - POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440= x5, - "PowerPC 440 F5") -#endif -#if defined(TODO) - POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440= x5, - "PowerPC 440 G5") -#endif -#if defined(TODO) - POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440= x4, - "PowerPC 440H4") -#endif -#if defined(TODO) - POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440= Gx5, - "PowerPC 440H6") -#endif - /* PowerPC 440 microcontrolers = */ - POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440= EP, - "PowerPC 440 EPa") - POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440= EP, - "PowerPC 440 EPb") - POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440= EP, - "PowerPC 440 EPX") -#if defined(TODO_USER_ONLY) - POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440= GP, - "PowerPC 440 GPb") -#endif -#if defined(TODO_USER_ONLY) - POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440= GP, - "PowerPC 440 GPc") -#endif -#if defined(TODO_USER_ONLY) - POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440= x5, - "PowerPC 440 GRa") -#endif -#if defined(TODO_USER_ONLY) - POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440= x5, - "PowerPC 440 GRX") -#endif -#if defined(TODO_USER_ONLY) - POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440= EP, - "PowerPC 440 GXa") -#endif -#if defined(TODO_USER_ONLY) - POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440= EP, - "PowerPC 440 GXb") -#endif -#if defined(TODO_USER_ONLY) - POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440= EP, - "PowerPC 440 GXc") -#endif -#if defined(TODO_USER_ONLY) - POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440= EP, - "PowerPC 440 GXf") -#endif -#if defined(TODO) - POWERPC_DEF("440S", CPU_POWERPC_440S, 440= , - "PowerPC 440 S") -#endif -#if defined(TODO_USER_ONLY) - POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440= EP, - "PowerPC 440 SP") -#endif -#if defined(TODO_USER_ONLY) - POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440= EP, - "PowerPC 440 SP2") -#endif -#if defined(TODO_USER_ONLY) - POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440= EP, - "PowerPC 440 SPE") -#endif - /* PowerPC 460 family = */ -#if defined(TODO) - POWERPC_DEF("464", CPU_POWERPC_464, 460= , - "Generic PowerPC 464") -#endif - /* PowerPC 464 microcontrolers = */ -#if defined(TODO) - POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460= , - "PowerPC 464H90") -#endif -#if defined(TODO) - POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460= F, - "PowerPC 464H90F") -#endif - /* Freescale embedded PowerPC cores = */ - /* MPC5xx family (aka RCPU) = */ -#if defined(TODO_USER_ONLY) - POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC= 5xx, - "Generic MPC5xx core") -#endif - /* MPC8xx family (aka PowerQUICC) = */ -#if defined(TODO_USER_ONLY) - POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC= 8xx, - "Generic MPC8xx core") -#endif - /* MPC82xx family (aka PowerQUICC-II) = */ - POWERPC_DEF("G2", CPU_POWERPC_G2, G2, - "PowerPC G2 core") - POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2, - "PowerPC G2 H4 core") - POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2, - "PowerPC G2 GP core") - POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2, - "PowerPC G2 LS core") - POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2, - "PowerPC G2 HiP3 core") - POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2, - "PowerPC G2 HiP4 core") - POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603= E, - "PowerPC MPC603 core") - POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2L= E, - "PowerPC G2le core (same as G2 plus little-endian mode support)"= ) - POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2L= E, - "PowerPC G2LE GP core") - POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2L= E, - "PowerPC G2LE LS core") - POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2L= E, - "PowerPC G2LE GP1 core") - POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2L= E, - "PowerPC G2LE GP3 core") - /* PowerPC G2 microcontrollers = */ -#if defined(TODO) - POWERPC_DEF_SVR("MPC5121", "MPC5121", - CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2L= E) -#endif - POWERPC_DEF_SVR("MPC5200_v10", "MPC5200 v1.0", - CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2L= E) - POWERPC_DEF_SVR("MPC5200_v11", "MPC5200 v1.1", - CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2L= E) - POWERPC_DEF_SVR("MPC5200_v12", "MPC5200 v1.2", - CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2L= E) - POWERPC_DEF_SVR("MPC5200B_v20", "MPC5200B v2.0", - CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2L= E) - POWERPC_DEF_SVR("MPC5200B_v21", "MPC5200B v2.1", - CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2L= E) - /* e200 family = */ -#if defined(TODO) - POWERPC_DEF_SVR("MPC55xx", "Generic MPC55xx core", - CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e20= 0, - "PowerPC e200z0 core") -#endif -#if defined(TODO) - POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e20= 0, - "PowerPC e200z1 core") -#endif -#if defined(TODO) - POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e20= 0, - "PowerPC e200z3 core") -#endif - POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e20= 0, - "PowerPC e200z5 core") - POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e20= 0, - "PowerPC e200z6 core") - /* PowerPC e200 microcontrollers = */ -#if defined(TODO) - POWERPC_DEF_SVR("MPC5514E", "MPC5514E", - CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5514E_v0", "MPC5514E v0", - CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5514E_v1", "MPC5514E v1", - CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5514G", "MPC5514G", - CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5514G_v0", "MPC5514G v0", - CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5514G_v1", "MPC5514G v1", - CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5515S", "MPC5515S", - CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5516E", "MPC5516E", - CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5516E_v0", "MPC5516E v0", - CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5516E_v1", "MPC5516E v1", - CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5516G", "MPC5516G", - CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5516G_v0", "MPC5516G v0", - CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5516G_v1", "MPC5516G v1", - CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5516S", "MPC5516S", - CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5533", "MPC5533", - CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5534", "MPC5534", - CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5553", "MPC5553", - CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5554", "MPC5554", - CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5561", "MPC5561", - CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5565", "MPC5565", - CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5566", "MPC5566", - CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e20= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC5567", "MPC5567", - CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e20= 0) -#endif - /* e300 family = */ - POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e30= 0, - "PowerPC e300c1 core") - POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e30= 0, - "PowerPC e300c2 core") - POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e30= 0, - "PowerPC e300c3 core") - POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e30= 0, - "PowerPC e300c4 core") - /* PowerPC e300 microcontrollers = */ -#if defined(TODO) - POWERPC_DEF_SVR("MPC8313", "MPC8313", - CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e30= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC8313E", "MPC8313E", - CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e30= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC8314", "MPC8314", - CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e30= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC8314E", "MPC8314E", - CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e30= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC8315", "MPC8315", - CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e30= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC8315E", "MPC8315E", - CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e30= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC8321", "MPC8321", - CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e30= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC8321E", "MPC8321E", - CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e30= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC8323", "MPC8323", - CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e30= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC8323E", "MPC8323E", - CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e30= 0) -#endif - POWERPC_DEF_SVR("MPC8343", "MPC8343", - CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e30= 0) - POWERPC_DEF_SVR("MPC8343A", "MPC8343A", - CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e30= 0) - POWERPC_DEF_SVR("MPC8343E", "MPC8343E", - CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e30= 0) - POWERPC_DEF_SVR("MPC8343EA", "MPC8343EA", - CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e30= 0) - POWERPC_DEF_SVR("MPC8347T", "MPC8347T", - CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e30= 0) - POWERPC_DEF_SVR("MPC8347P", "MPC8347P", - CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e30= 0) - POWERPC_DEF_SVR("MPC8347AT", "MPC8347AT", - CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e30= 0) - POWERPC_DEF_SVR("MPC8347AP", "MPC8347AP", - CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e30= 0) - POWERPC_DEF_SVR("MPC8347ET", "MPC8347ET", - CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e30= 0) - POWERPC_DEF_SVR("MPC8347EP", "MPC8343EP", - CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e30= 0) - POWERPC_DEF_SVR("MPC8347EAT", "MPC8347EAT", - CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e30= 0) - POWERPC_DEF_SVR("MPC8347EAP", "MPC8343EAP", - CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e30= 0) - POWERPC_DEF_SVR("MPC8349", "MPC8349", - CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e30= 0) - POWERPC_DEF_SVR("MPC8349A", "MPC8349A", - CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e30= 0) - POWERPC_DEF_SVR("MPC8349E", "MPC8349E", - CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e30= 0) - POWERPC_DEF_SVR("MPC8349EA", "MPC8349EA", - CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e30= 0) -#if defined(TODO) - POWERPC_DEF_SVR("MPC8358E", "MPC8358E", - CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e30= 0) -#endif -#if defined(TODO) - POWERPC_DEF_SVR("MPC8360E", "MPC8360E", - CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e30= 0) -#endif - POWERPC_DEF_SVR("MPC8377", "MPC8377", - CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e30= 0) - POWERPC_DEF_SVR("MPC8377E", "MPC8377E", - CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e30= 0) - POWERPC_DEF_SVR("MPC8378", "MPC8378", - CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e30= 0) - POWERPC_DEF_SVR("MPC8378E", "MPC8378E", - CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e30= 0) - POWERPC_DEF_SVR("MPC8379", "MPC8379", - CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e30= 0) - POWERPC_DEF_SVR("MPC8379E", "MPC8379E", - CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e30= 0) - /* e500 family = */ - POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e50= 0v1, - "PowerPC e500 v1.0 core") - POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e50= 0v1, - "PowerPC e500 v2.0 core") - POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e50= 0v2, - "PowerPC e500v2 v1.0 core") - POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e50= 0v2, - "PowerPC e500v2 v2.0 core") - POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e50= 0v2, - "PowerPC e500v2 v2.1 core") - POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e50= 0v2, - "PowerPC e500v2 v2.2 core") - POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e50= 0v2, - "PowerPC e500v2 v3.0 core") - POWERPC_DEF_SVR("e500mc", "e500mc", - CPU_POWERPC_e500mc, POWERPC_SVR_E500, e50= 0mc) -#ifdef TARGET_PPC64 - POWERPC_DEF_SVR("e5500", "e5500", - CPU_POWERPC_e5500, POWERPC_SVR_E500, e55= 00) -#endif - /* PowerPC e500 microcontrollers = */ - POWERPC_DEF_SVR("MPC8533_v10", "MPC8533 v1.0", - CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e50= 0v2) - POWERPC_DEF_SVR("MPC8533_v11", "MPC8533 v1.1", - CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e50= 0v2) - POWERPC_DEF_SVR("MPC8533E_v10", "MPC8533E v1.0", - CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e50= 0v2) - POWERPC_DEF_SVR("MPC8533E_v11", "MPC8533E v1.1", - CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e50= 0v2) - POWERPC_DEF_SVR("MPC8540_v10", "MPC8540 v1.0", - CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e50= 0v1) - POWERPC_DEF_SVR("MPC8540_v20", "MPC8540 v2.0", - CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e50= 0v1) - POWERPC_DEF_SVR("MPC8540_v21", "MPC8540 v2.1", - CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e50= 0v1) - POWERPC_DEF_SVR("MPC8541_v10", "MPC8541 v1.0", - CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e50= 0v1) - POWERPC_DEF_SVR("MPC8541_v11", "MPC8541 v1.1", - CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e50= 0v1) - POWERPC_DEF_SVR("MPC8541E_v10", "MPC8541E v1.0", - CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e50= 0v1) - POWERPC_DEF_SVR("MPC8541E_v11", "MPC8541E v1.1", - CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e50= 0v1) - POWERPC_DEF_SVR("MPC8543_v10", "MPC8543 v1.0", - CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e50= 0v2) - POWERPC_DEF_SVR("MPC8543_v11", "MPC8543 v1.1", - CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e50= 0v2) - POWERPC_DEF_SVR("MPC8543_v20", "MPC8543 v2.0", - CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e50= 0v2) - POWERPC_DEF_SVR("MPC8543_v21", "MPC8543 v2.1", - CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e50= 0v2) - POWERPC_DEF_SVR("MPC8543E_v10", "MPC8543E v1.0", - CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e50= 0v2) - POWERPC_DEF_SVR("MPC8543E_v11", "MPC8543E v1.1", - CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e50= 0v2) - POWERPC_DEF_SVR("MPC8543E_v20", "MPC8543E v2.0", - CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e50= 0v2) - POWERPC_DEF_SVR("MPC8543E_v21", "MPC8543E v2.1", - CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e50= 0v2) - POWERPC_DEF_SVR("MPC8544_v10", "MPC8544 v1.0", - CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e50= 0v2) - POWERPC_DEF_SVR("MPC8544_v11", "MPC8544 v1.1", - CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e50= 0v2) - POWERPC_DEF_SVR("MPC8544E_v10", "MPC8544E v1.0", - CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e50= 0v2) - POWERPC_DEF_SVR("MPC8544E_v11", "MPC8544E v1.1", - CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e50= 0v2) - POWERPC_DEF_SVR("MPC8545_v20", "MPC8545 v2.0", - CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e50= 0v2) - POWERPC_DEF_SVR("MPC8545_v21", "MPC8545 v2.1", - CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e50= 0v2) - POWERPC_DEF_SVR("MPC8545E_v20", "MPC8545E v2.0", - CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e50= 0v2) - POWERPC_DEF_SVR("MPC8545E_v21", "MPC8545E v2.1", - CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e50= 0v2) - POWERPC_DEF_SVR("MPC8547E_v20", "MPC8547E v2.0", - CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e50= 0v2) - POWERPC_DEF_SVR("MPC8547E_v21", "MPC8547E v2.1", - CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e50= 0v2) - POWERPC_DEF_SVR("MPC8548_v10", "MPC8548 v1.0", - CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e50= 0v2) - POWERPC_DEF_SVR("MPC8548_v11", "MPC8548 v1.1", - CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e50= 0v2) - POWERPC_DEF_SVR("MPC8548_v20", "MPC8548 v2.0", - CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e50= 0v2) - POWERPC_DEF_SVR("MPC8548_v21", "MPC8548 v2.1", - CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e50= 0v2) - POWERPC_DEF_SVR("MPC8548E_v10", "MPC8548E v1.0", - CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e50= 0v2) - POWERPC_DEF_SVR("MPC8548E_v11", "MPC8548E v1.1", - CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e50= 0v2) - POWERPC_DEF_SVR("MPC8548E_v20", "MPC8548E v2.0", - CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e50= 0v2) - POWERPC_DEF_SVR("MPC8548E_v21", "MPC8548E v2.1", - CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e50= 0v2) - POWERPC_DEF_SVR("MPC8555_v10", "MPC8555 v1.0", - CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e50= 0v2) - POWERPC_DEF_SVR("MPC8555_v11", "MPC8555 v1.1", - CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e50= 0v2) - POWERPC_DEF_SVR("MPC8555E_v10", "MPC8555E v1.0", - CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e50= 0v2) - POWERPC_DEF_SVR("MPC8555E_v11", "MPC8555E v1.1", - CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e50= 0v2) - POWERPC_DEF_SVR("MPC8560_v10", "MPC8560 v1.0", - CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e50= 0v2) - POWERPC_DEF_SVR("MPC8560_v20", "MPC8560 v2.0", - CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e50= 0v2) - POWERPC_DEF_SVR("MPC8560_v21", "MPC8560 v2.1", - CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e50= 0v2) - POWERPC_DEF_SVR("MPC8567", "MPC8567", - CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e50= 0v2) - POWERPC_DEF_SVR("MPC8567E", "MPC8567E", - CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e50= 0v2) - POWERPC_DEF_SVR("MPC8568", "MPC8568", - CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e50= 0v2) - POWERPC_DEF_SVR("MPC8568E", "MPC8568E", - CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e50= 0v2) - POWERPC_DEF_SVR("MPC8572", "MPC8572", - CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e50= 0v2) - POWERPC_DEF_SVR("MPC8572E", "MPC8572E", - CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e50= 0v2) - /* e600 family = */ - POWERPC_DEF("e600", CPU_POWERPC_e600, 740= 0, - "PowerPC e600 core") - /* PowerPC e600 microcontrollers = */ -#if defined(TODO) - POWERPC_DEF_SVR("MPC8610", "MPC8610", - CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 740= 0) -#endif - POWERPC_DEF_SVR("MPC8641", "MPC8641", - CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 740= 0) - POWERPC_DEF_SVR("MPC8641D", "MPC8641D", - CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 740= 0) - /* 32 bits "classic" PowerPC = */ - /* PowerPC 6xx family = */ - POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601= , - "PowerPC 601v0") - POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601= , - "PowerPC 601v1") - POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601= v, - "PowerPC 601v2") - POWERPC_DEF("602", CPU_POWERPC_602, 602= , - "PowerPC 602") - POWERPC_DEF("603", CPU_POWERPC_603, 603= , - "PowerPC 603") - POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603= E, - "PowerPC 603e v1.1") - POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603= E, - "PowerPC 603e v1.2") - POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603= E, - "PowerPC 603e v1.3") - POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603= E, - "PowerPC 603e v1.4") - POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603= E, - "PowerPC 603e v2.2") - POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603= E, - "PowerPC 603e v3") - POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603= E, - "PowerPC 603e v4") - POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603= E, - "PowerPC 603e v4.1") - POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603= E, - "PowerPC 603e (aka PID7)") - POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603= E, - "PowerPC 603e7t") - POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603= E, - "PowerPC 603e7v") - POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603= E, - "PowerPC 603e7v1") - POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603= E, - "PowerPC 603e7v2") - POWERPC_DEF("603p", CPU_POWERPC_603P, 603= E, - "PowerPC 603p (aka PID7v)") - POWERPC_DEF("604", CPU_POWERPC_604, 604= , - "PowerPC 604") - POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604= E, - "PowerPC 604e v1.0") - POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604= E, - "PowerPC 604e v2.2") - POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604= E, - "PowerPC 604e v2.4") - POWERPC_DEF("604r", CPU_POWERPC_604R, 604= E, - "PowerPC 604r (aka PIDA)") -#if defined(TODO) - POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604= E, - "PowerPC 604ev") -#endif - /* PowerPC 7xx family = */ - POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740= , - "PowerPC 740 v1.0 (G3)") - POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750= , - "PowerPC 750 v1.0 (G3)") - POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740= , - "PowerPC 740 v2.0 (G3)") - POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750= , - "PowerPC 750 v2.0 (G3)") - POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740= , - "PowerPC 740 v2.1 (G3)") - POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750= , - "PowerPC 750 v2.1 (G3)") - POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740= , - "PowerPC 740 v2.2 (G3)") - POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750= , - "PowerPC 750 v2.2 (G3)") - POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740= , - "PowerPC 740 v3.0 (G3)") - POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750= , - "PowerPC 750 v3.0 (G3)") - POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740= , - "PowerPC 740 v3.1 (G3)") - POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750= , - "PowerPC 750 v3.1 (G3)") - POWERPC_DEF("740e", CPU_POWERPC_740E, 740= , - "PowerPC 740E (G3)") - POWERPC_DEF("750e", CPU_POWERPC_750E, 750= , - "PowerPC 750E (G3)") - POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740= , - "PowerPC 740P (G3)") - POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750= , - "PowerPC 750P (G3)") - POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750= cl, - "PowerPC 750CL v1.0") - POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750= cl, - "PowerPC 750CL v2.0") - POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750= cx, - "PowerPC 750CX v1.0 (G3 embedded)") - POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750= cx, - "PowerPC 750CX v2.1 (G3 embedded)") - POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750= cx, - "PowerPC 750CX v2.1 (G3 embedded)") - POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750= cx, - "PowerPC 750CX v2.2 (G3 embedded)") - POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750= cx, - "PowerPC 750CXe v2.1 (G3 embedded)") - POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750= cx, - "PowerPC 750CXe v2.2 (G3 embedded)") - POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750= cx, - "PowerPC 750CXe v2.3 (G3 embedded)") - POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750= cx, - "PowerPC 750CXe v2.4 (G3 embedded)") - POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750= cx, - "PowerPC 750CXe v2.4b (G3 embedded)") - POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750= cx, - "PowerPC 750CXe v3.0 (G3 embedded)") - POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750= cx, - "PowerPC 750CXe v3.1 (G3 embedded)") - POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750= cx, - "PowerPC 750CXe v3.1b (G3 embedded)") - POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750= cx, - "PowerPC 750CXr (G3 embedded)") - POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750= fx, - "PowerPC 750FL (G3 embedded)") - POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750= fx, - "PowerPC 750FX v1.0 (G3 embedded)") - POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750= fx, - "PowerPC 750FX v2.0 (G3 embedded)") - POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750= fx, - "PowerPC 750FX v2.1 (G3 embedded)") - POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750= fx, - "PowerPC 750FX v2.2 (G3 embedded)") - POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750= fx, - "PowerPC 750FX v2.3 (G3 embedded)") - POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750= gx, - "PowerPC 750GL (G3 embedded)") - POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750= gx, - "PowerPC 750GX v1.0 (G3 embedded)") - POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750= gx, - "PowerPC 750GX v1.1 (G3 embedded)") - POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750= gx, - "PowerPC 750GX v1.2 (G3 embedded)") - POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750= , - "PowerPC 750L v2.0 (G3 embedded)") - POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750= , - "PowerPC 750L v2.1 (G3 embedded)") - POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750= , - "PowerPC 750L v2.2 (G3 embedded)") - POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750= , - "PowerPC 750L v3.0 (G3 embedded)") - POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750= , - "PowerPC 750L v3.2 (G3 embedded)") - POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745= , - "PowerPC 745 v1.0") - POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755= , - "PowerPC 755 v1.0") - POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745= , - "PowerPC 745 v1.1") - POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755= , - "PowerPC 755 v1.1") - POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745= , - "PowerPC 745 v2.0") - POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755= , - "PowerPC 755 v2.0") - POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745= , - "PowerPC 745 v2.1") - POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755= , - "PowerPC 755 v2.1") - POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745= , - "PowerPC 745 v2.2") - POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755= , - "PowerPC 755 v2.2") - POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745= , - "PowerPC 745 v2.3") - POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755= , - "PowerPC 755 v2.3") - POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745= , - "PowerPC 745 v2.4") - POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755= , - "PowerPC 755 v2.4") - POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745= , - "PowerPC 745 v2.5") - POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755= , - "PowerPC 755 v2.5") - POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745= , - "PowerPC 745 v2.6") - POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755= , - "PowerPC 755 v2.6") - POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745= , - "PowerPC 745 v2.7") - POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755= , - "PowerPC 755 v2.7") - POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745= , - "PowerPC 745 v2.8") - POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755= , - "PowerPC 755 v2.8") -#if defined(TODO) - POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745= , - "PowerPC 745P (G3)") - POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755= , - "PowerPC 755P (G3)") -#endif - /* PowerPC 74xx family = */ - POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 740= 0, - "PowerPC 7400 v1.0 (G4)") - POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 740= 0, - "PowerPC 7400 v1.1 (G4)") - POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 740= 0, - "PowerPC 7400 v2.0 (G4)") - POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 740= 0, - "PowerPC 7400 v2.1 (G4)") - POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 740= 0, - "PowerPC 7400 v2.2 (G4)") - POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 740= 0, - "PowerPC 7400 v2.6 (G4)") - POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 740= 0, - "PowerPC 7400 v2.7 (G4)") - POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 740= 0, - "PowerPC 7400 v2.8 (G4)") - POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 740= 0, - "PowerPC 7400 v2.9 (G4)") - POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 741= 0, - "PowerPC 7410 v1.0 (G4)") - POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 741= 0, - "PowerPC 7410 v1.1 (G4)") - POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 741= 0, - "PowerPC 7410 v1.2 (G4)") - POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 741= 0, - "PowerPC 7410 v1.3 (G4)") - POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 741= 0, - "PowerPC 7410 v1.4 (G4)") - POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 740= 0, - "PowerPC 7448 v1.0 (G4)") - POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 740= 0, - "PowerPC 7448 v1.1 (G4)") - POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 740= 0, - "PowerPC 7448 v2.0 (G4)") - POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 740= 0, - "PowerPC 7448 v2.1 (G4)") - POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 745= 0, - "PowerPC 7450 v1.0 (G4)") - POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 745= 0, - "PowerPC 7450 v1.1 (G4)") - POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 745= 0, - "PowerPC 7450 v1.2 (G4)") - POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 745= 0, - "PowerPC 7450 v2.0 (G4)") - POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 745= 0, - "PowerPC 7450 v2.1 (G4)") - POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 744= 0, - "PowerPC 7441 v2.1 (G4)") - POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 744= 0, - "PowerPC 7441 v2.3 (G4)") - POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 745= 0, - "PowerPC 7451 v2.3 (G4)") - POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 744= 0, - "PowerPC 7441 v2.10 (G4)") - POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 745= 0, - "PowerPC 7451 v2.10 (G4)") - POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 744= 5, - "PowerPC 7445 v1.0 (G4)") - POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 745= 5, - "PowerPC 7455 v1.0 (G4)") - POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 744= 5, - "PowerPC 7445 v2.1 (G4)") - POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 745= 5, - "PowerPC 7455 v2.1 (G4)") - POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 744= 5, - "PowerPC 7445 v3.2 (G4)") - POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 745= 5, - "PowerPC 7455 v3.2 (G4)") - POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 744= 5, - "PowerPC 7445 v3.3 (G4)") - POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 745= 5, - "PowerPC 7455 v3.3 (G4)") - POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 744= 5, - "PowerPC 7445 v3.4 (G4)") - POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 745= 5, - "PowerPC 7455 v3.4 (G4)") - POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 744= 5, - "PowerPC 7447 v1.0 (G4)") - POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 745= 5, - "PowerPC 7457 v1.0 (G4)") - POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 744= 5, - "PowerPC 7447 v1.1 (G4)") - POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 745= 5, - "PowerPC 7457 v1.1 (G4)") - POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 745= 5, - "PowerPC 7457 v1.2 (G4)") - POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 744= 5, - "PowerPC 7447A v1.0 (G4)") - POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 745= 5, - "PowerPC 7457A v1.0 (G4)") - POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 744= 5, - "PowerPC 7447A v1.1 (G4)") - POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 745= 5, - "PowerPC 7457A v1.1 (G4)") - POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 744= 5, - "PowerPC 7447A v1.2 (G4)") - POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 745= 5, - "PowerPC 7457A v1.2 (G4)") - /* 64 bits PowerPC = */ -#if defined (TARGET_PPC64) - POWERPC_DEF("620", CPU_POWERPC_620, 620= , - "PowerPC 620") -#if defined(TODO) - POWERPC_DEF("630", CPU_POWERPC_630, 630= , - "PowerPC 630 (POWER3)") -#endif -#if defined(TODO) - POWERPC_DEF("631", CPU_POWERPC_631, 631= , - "PowerPC 631 (Power 3+)") -#endif -#if defined(TODO) - POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POW= ER4, - "POWER4") -#endif -#if defined(TODO) - POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POW= ER4P, - "POWER4p") -#endif -#if defined(TODO) - POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POW= ER5, - "POWER5") - POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POW= ER5, - "POWER5GR") -#endif -#if defined(TODO) - POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POW= ER5P, - "POWER5+") - POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POW= ER5P, - "POWER5GS") -#endif -#if defined(TODO) - POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POW= ER6, - "POWER6") - POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POW= ER5, - "POWER6 running in POWER5 mode") - POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POW= ER6, - "POWER6A") -#endif - POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POW= ER7, - "POWER7 v2.0") - POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POW= ER7, - "POWER7 v2.1") - POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POW= ER7, - "POWER7 v2.3") - POWERPC_DEF("970", CPU_POWERPC_970, 970= , - "PowerPC 970") - POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970= FX, - "PowerPC 970FX v1.0 (G5)") - POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970= FX, - "PowerPC 970FX v2.0 (G5)") - POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970= FX, - "PowerPC 970FX v2.1 (G5)") - POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970= FX, - "PowerPC 970FX v3.0 (G5)") - POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970= FX, - "PowerPC 970FX v3.1 (G5)") - POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970= GX, - "PowerPC 970GX (G5)") - POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970= MP, - "PowerPC 970MP v1.0") - POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970= MP, - "PowerPC 970MP v1.1") -#if defined(TODO) - POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970= , - "PowerPC Cell") -#endif -#if defined(TODO) - POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970= , - "PowerPC Cell v1.0") -#endif -#if defined(TODO) - POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970= , - "PowerPC Cell v2.0") -#endif -#if defined(TODO) - POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970= , - "PowerPC Cell v3.0") -#endif -#if defined(TODO) - POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970= , - "PowerPC Cell v3.1") -#endif -#if defined(TODO) - POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970= , - "PowerPC Cell v3.2") -#endif -#if defined(TODO) - /* This one seems to support the whole POWER2 instruction set - * and the PowerPC 64 one. - */ - /* What about A10 & A30 ? */ - POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS6= 4, - "RS64 (Apache/A35)") -#endif -#if defined(TODO) - POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS6= 4, - "RS64-II (NorthStar/A50)") -#endif -#if defined(TODO) - POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS6= 4, - "RS64-III (Pulsar)") -#endif -#if defined(TODO) - POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS6= 4, - "RS64-IV (IceStar/IStar/SStar)") -#endif -#endif /* defined (TARGET_PPC64) */ - /* POWER = */ -#if defined(TODO) - POWERPC_DEF("POWER", CPU_POWERPC_POWER, POW= ER, - "Original POWER") -#endif -#if defined(TODO) - POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POW= ER, - "POWER2") -#endif - /* PA semi cores = */ -#if defined(TODO) - POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6= T, - "PA PA6T") -#endif =20 typedef struct PowerPCCPUAlias { const char *alias; --=20 1.6.0.2