From: David Gibson <david@gibson.dropbear.id.au>
To: agraf@suse.de
Cc: David Gibson <david@gibson.dropbear.id.au>,
qemu-ppc@nongnu.org, afaerber@suse.de, qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 09/48] target-ppc: Disentangle get_physical_address() paths
Date: Tue, 12 Mar 2013 21:31:11 +1100 [thread overview]
Message-ID: <1363084310-4115-10-git-send-email-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <1363084310-4115-1-git-send-email-david@gibson.dropbear.id.au>
Depending on the MSR state, for 64-bit hash MMUs, get_physical_address
can either call check_physical (which has further tests for mmu type)
or get_segment64. Similarly for 32-bit hash MMUs we can either call
check_physucal or get_bat() and get_segment32().
This patch splits off the whole get_physical_addresss() path for hash
MMUs into 32-bit and 64-bit versions, handling real mode correctly for
such MMUs without going to check_physical and rechecking the mmu type.
Correspondingly, the hash MMU specific paths in check_physical() are
removed.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/cpu.h | 2 ++
target-ppc/mmu-hash32.c | 29 +++++++++++++++++++++++++++--
target-ppc/mmu-hash32.h | 4 ++--
target-ppc/mmu-hash64.c | 19 +++++++++++++++++--
target-ppc/mmu-hash64.h | 4 ++--
target-ppc/mmu_helper.c | 46 ++++++++--------------------------------------
6 files changed, 58 insertions(+), 46 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index a9994cb..b76b09a 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1138,6 +1138,8 @@ int pp_check(int key, int pp, int nx);
int check_prot(int prot, int rw, int access_type);
int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p, int ret, int rw);
hwaddr get_pteg_offset(CPUPPCState *env, hwaddr hash, int pte_size);
+int get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong virtual, int rw, int type);
#endif /* !defined(CONFIG_USER_ONLY) */
void ppc_store_msr (CPUPPCState *env, target_ulong value);
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index 4bae72a..3998d63 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -158,8 +158,8 @@ static int find_pte32(CPUPPCState *env, mmu_ctx_t *ctx, int h,
return ret;
}
-int get_segment32(CPUPPCState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw, int type)
+static int get_segment32(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int type)
{
hwaddr hash;
target_ulong vsid;
@@ -302,3 +302,28 @@ int get_segment32(CPUPPCState *env, mmu_ctx_t *ctx,
return ret;
}
+
+int ppc_hash32_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int access_type)
+{
+ bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
+ || (access_type != ACCESS_CODE && msr_dr == 0);
+
+ if (real_mode) {
+ ctx->raddr = eaddr;
+ ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
+ return 0;
+ } else {
+ int ret = -1;
+
+ /* Try to find a BAT */
+ if (env->nb_BATs != 0) {
+ ret = get_bat(env, ctx, eaddr, rw, access_type);
+ }
+ if (ret < 0) {
+ /* We didn't match any BAT entry or don't have BATs */
+ ret = get_segment32(env, ctx, eaddr, rw, access_type);
+ }
+ return ret;
+ }
+}
diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h
index 6f9a0c2..1318562 100644
--- a/target-ppc/mmu-hash32.h
+++ b/target-ppc/mmu-hash32.h
@@ -4,8 +4,8 @@
#ifndef CONFIG_USER_ONLY
int pte32_is_valid(target_ulong pte0);
-int get_segment32(CPUPPCState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw, int type);
+int ppc_hash32_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int access_type);
#endif /* CONFIG_USER_ONLY */
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 23eb480..c727298 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -350,8 +350,8 @@ static int find_pte64(CPUPPCState *env, mmu_ctx_t *ctx, int h,
return ret;
}
-int get_segment64(CPUPPCState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw, int type)
+static int get_segment64(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int type)
{
hwaddr hash;
target_ulong vsid;
@@ -435,3 +435,18 @@ int get_segment64(CPUPPCState *env, mmu_ctx_t *ctx,
return ret;
}
+
+int ppc_hash64_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int access_type)
+{
+ bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
+ || (access_type != ACCESS_CODE && msr_dr == 0);
+
+ if (real_mode) {
+ ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
+ ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
+ return 0;
+ } else {
+ return get_segment64(env, ctx, eaddr, rw, access_type);
+ }
+}
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 690c1d8..d8eb8de 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -6,8 +6,8 @@
#ifdef TARGET_PPC64
void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
-int get_segment64(CPUPPCState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw, int type);
+int ppc_hash64_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int access_type);
#endif
#endif /* CONFIG_USER_ONLY */
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 5b82731..ce39f49 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -426,8 +426,8 @@ static inline void bat_601_size_prot(CPUPPCState *env, target_ulong *blp,
*protp = prot;
}
-static inline int get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
- target_ulong virtual, int rw, int type)
+int get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong virtual, int rw, int type)
{
target_ulong *BATlt, *BATut, *BATu, *BATl;
target_ulong BEPIl, BEPIu, bl;
@@ -1256,8 +1256,6 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx,
ctx->prot = PAGE_READ | PAGE_EXEC;
ret = 0;
switch (env->mmu_model) {
- case POWERPC_MMU_32B:
- case POWERPC_MMU_601:
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
case POWERPC_MMU_SOFT_4xx:
@@ -1265,15 +1263,7 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx,
case POWERPC_MMU_BOOKE:
ctx->prot |= PAGE_WRITE;
break;
-#if defined(TARGET_PPC64)
- case POWERPC_MMU_64B:
- case POWERPC_MMU_2_06:
- case POWERPC_MMU_2_06d:
- /* Real address are 60 bits long */
- ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
- ctx->prot |= PAGE_WRITE;
- break;
-#endif
+
case POWERPC_MMU_SOFT_4xx_Z:
if (unlikely(msr_pe != 0)) {
/* 403 family add some particular protections,
@@ -1298,15 +1288,10 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx,
}
}
break;
- case POWERPC_MMU_MPC8xx:
- /* XXX: TODO */
- cpu_abort(env, "MPC8xx MMU model is not implemented\n");
- break;
- case POWERPC_MMU_BOOKE206:
- cpu_abort(env, "BookE 2.06 MMU doesn't have physical real mode\n");
- break;
+
default:
- cpu_abort(env, "Unknown or invalid MMU model\n");
+ /* Caller's checks mean we should never get here for other models */
+ abort();
return -1;
}
@@ -1327,18 +1312,7 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
switch (env->mmu_model) {
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
- if (real_mode) {
- ret = check_physical(env, ctx, eaddr, rw);
- } else {
- /* Try to find a BAT */
- if (env->nb_BATs != 0) {
- ret = get_bat(env, ctx, eaddr, rw, access_type);
- }
- if (ret < 0) {
- /* We didn't match any BAT entry or don't have BATs */
- ret = get_segment32(env, ctx, eaddr, rw, access_type);
- }
- }
+ ret = ppc_hash32_get_physical_address(env, ctx, eaddr, rw, access_type);
break;
case POWERPC_MMU_SOFT_6xx:
@@ -1361,11 +1335,7 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
case POWERPC_MMU_64B:
case POWERPC_MMU_2_06:
case POWERPC_MMU_2_06d:
- if (real_mode) {
- ret = check_physical(env, ctx, eaddr, rw);
- } else {
- ret = get_segment64(env, ctx, eaddr, rw, access_type);
- }
+ ret = ppc_hash64_get_physical_address(env, ctx, eaddr, rw, access_type);
break;
#endif
--
1.7.10.4
next prev parent reply other threads:[~2013-03-12 10:32 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-12 10:31 [Qemu-devel] [0/48] target-ppc: MMU implementation cleanup for hash MMUs David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 01/48] target-ppc: Remove vestigial PowerPC 620 support David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 02/48] target-ppc: Trivial cleanups in mmu_helper.c David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 03/48] target-ppc: Remove address check for logging David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 04/48] target-ppc: Move SLB handling into a mmu-hash64.c David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 05/48] target-ppc: Disentangle pte_check() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 06/48] target-ppc: Disentangle find_pte() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 07/48] target-ppc: Disentangle get_segment() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 08/48] target-ppc: Rework get_physical_address() David Gibson
2013-03-12 10:31 ` David Gibson [this message]
2013-03-12 10:31 ` [Qemu-devel] [PATCH 10/48] target-ppc: Disentangle hash mmu paths for cpu_ppc_handle_mmu_fault David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 11/48] target-ppc: Disentangle hash mmu versions of cpu_get_phys_page_debug() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 12/48] target-ppc: Disentangle hash mmu helper functions David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 13/48] target-ppc: Don't share get_pteg_offset() between 32 and 64-bit David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 14/48] target-ppc: Disentangle BAT code for 32-bit hash MMUs David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 15/48] target-ppc: mmu_ctx_t should not be a global type David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 16/48] mmu-hash*: Add header file for definitions David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 17/48] mmu-hash*: Add hash pte load/store helpers David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 18/48] mmu-hash*: Reduce use of access_type David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 19/48] mmu-hash64: Remove nx from mmu_ctx_hash64 David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 20/48] mmu-hash*: Remove eaddr field from mmu_ctx_hash{32, 64} David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 21/48] mmu-hash*: Combine ppc_hash{32, 64}_get_physical_address and get_segment{32, 64}() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 22/48] mmu-hash32: Split out handling of direct store segments David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 23/48] mmu-hash32: Split direct store segment handling into a helper David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 24/48] mmu-hash*: Cleanup segment-level NX check David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 25/48] mmu-hash*: Don't keep looking for PTEs after we find a match David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 26/48] mmu-hash*: Separate PTEG searching from permissions checking David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 27/48] mmu-hash*: Make find_pte{32, 64} do more of the job of finding ptes David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 28/48] mmu-hash*: Remove permission checking from find_pte{32, 64}() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 29/48] mmu-hash64: Clean up ppc_hash64_htab_lookup() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 30/48] mmu-hash*: Fold pte_check*() logic into caller David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 31/48] mmu-hash32: Remove odd pointer usage from BAT code David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 32/48] mmu-hash32: Split BAT size logic from permissions logic David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 33/48] mmu-hash32: Clean up BAT matching logic David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 34/48] mmu-hash32: Cleanup BAT lookup David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 35/48] mmu-hash32: Don't look up page tables on BAT permission error David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 36/48] mmu-hash*: Don't update PTE flags when permission is denied David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 37/48] mmu-hash32: Remove nx from context structure David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 38/48] mmu-hash*: Clean up permission checking David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 39/48] mmu-hash64: Factor SLB N bit into permissions bits David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 40/48] mmu-hash*: Clean up PTE flags update David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 41/48] mmu-hash*: Clean up real address calculation David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 42/48] mmu-hash*: Correctly mask RPN from hash PTE David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 43/48] mmu-hash*: Don't use full ppc_hash{32, 64}_translate() path for get_phys_page_debug() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 44/48] mmu-hash*: Merge translate and fault handling functions David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 45/48] mmu-hash64: Implement Virtual Page Class Key Protection David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 46/48] target-ppc: Split user only code out of mmu_helper.c David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 47/48] target-ppc: Move ppc tlb_fill implementation into mmu_helper.c David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 48/48] target-ppc: Use QOM method dispatch for MMU fault handling David Gibson
2013-03-13 0:42 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2013-03-21 13:43 ` [Qemu-devel] [0/48] target-ppc: MMU implementation cleanup for hash MMUs Alexander Graf
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