qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: David Gibson <david@gibson.dropbear.id.au>
To: agraf@suse.de
Cc: David Gibson <david@gibson.dropbear.id.au>,
	qemu-ppc@nongnu.org, afaerber@suse.de, qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 08/48] target-ppc: Rework get_physical_address()
Date: Tue, 12 Mar 2013 21:31:10 +1100	[thread overview]
Message-ID: <1363084310-4115-9-git-send-email-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <1363084310-4115-1-git-send-email-david@gibson.dropbear.id.au>

Currently get_physical_address() first checks to see if translation is
enabled in the MSR, then in the translation on case switches on the mmu
type.  Except that for BookE MMUs, translation is always on, and so it
has to switch in the "translation off" case as well and do the same thing
as the translation on path for those MMUs.  Plus, even translation off
doesn't behave exactly the same on the various MMU types so there are
further mmu type checks in the "translation off" path.

As a first step to cleaning this up, this patch moves the switch on mmu
type to the top level, then makes the translation on/off check just for
those mmu types where it is meaningful.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 target-ppc/mmu_helper.c |   98 +++++++++++++++++++++++++----------------------
 1 file changed, 52 insertions(+), 46 deletions(-)

diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index db5c15a..5b82731 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1316,30 +1316,20 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx,
 static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
                                 target_ulong eaddr, int rw, int access_type)
 {
-    int ret;
+    int ret = -1;
+    bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
+        || (access_type != ACCESS_CODE && msr_dr == 0);
 
 #if 0
     qemu_log("%s\n", __func__);
 #endif
-    if ((access_type == ACCESS_CODE && msr_ir == 0) ||
-        (access_type != ACCESS_CODE && msr_dr == 0)) {
-        if (env->mmu_model == POWERPC_MMU_BOOKE) {
-            /* The BookE MMU always performs address translation. The
-               IS and DS bits only affect the address space.  */
-            ret = mmubooke_get_physical_address(env, ctx, eaddr,
-                                                rw, access_type);
-        } else if (env->mmu_model == POWERPC_MMU_BOOKE206) {
-            ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw,
-                                                   access_type);
-        } else {
-            /* No address translation.  */
+
+    switch (env->mmu_model) {
+    case POWERPC_MMU_32B:
+    case POWERPC_MMU_601:
+        if (real_mode) {
             ret = check_physical(env, ctx, eaddr, rw);
-        }
-    } else {
-        ret = -1;
-        switch (env->mmu_model) {
-        case POWERPC_MMU_32B:
-        case POWERPC_MMU_601:
+        } else {
             /* Try to find a BAT */
             if (env->nb_BATs != 0) {
                 ret = get_bat(env, ctx, eaddr, rw, access_type);
@@ -1348,10 +1338,14 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
                 /* We didn't match any BAT entry or don't have BATs */
                 ret = get_segment32(env, ctx, eaddr, rw, access_type);
             }
-            break;
+        }
+        break;
 
-        case POWERPC_MMU_SOFT_6xx:
-        case POWERPC_MMU_SOFT_74xx:
+    case POWERPC_MMU_SOFT_6xx:
+    case POWERPC_MMU_SOFT_74xx:
+        if (real_mode) {
+            ret = check_physical(env, ctx, eaddr, rw);
+        } else {
             /* Try to find a BAT */
             if (env->nb_BATs != 0) {
                 ret = get_bat(env, ctx, eaddr, rw, access_type);
@@ -1360,40 +1354,52 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
                 /* We didn't match any BAT entry or don't have BATs */
                 ret = get_segment_6xx_tlb(env, ctx, eaddr, rw, access_type);
             }
-            break;
+        }
+        break;
 
 #if defined(TARGET_PPC64)
-        case POWERPC_MMU_64B:
-        case POWERPC_MMU_2_06:
-        case POWERPC_MMU_2_06d:
+    case POWERPC_MMU_64B:
+    case POWERPC_MMU_2_06:
+    case POWERPC_MMU_2_06d:
+        if (real_mode) {
+            ret = check_physical(env, ctx, eaddr, rw);
+        } else {
             ret = get_segment64(env, ctx, eaddr, rw, access_type);
-            break;
+        }
+        break;
 #endif
 
-        case POWERPC_MMU_SOFT_4xx:
-        case POWERPC_MMU_SOFT_4xx_Z:
+    case POWERPC_MMU_SOFT_4xx:
+    case POWERPC_MMU_SOFT_4xx_Z:
+        if (real_mode) {
+            ret = check_physical(env, ctx, eaddr, rw);
+        } else {
             ret = mmu40x_get_physical_address(env, ctx, eaddr,
                                               rw, access_type);
-            break;
-        case POWERPC_MMU_BOOKE:
-            ret = mmubooke_get_physical_address(env, ctx, eaddr,
-                                                rw, access_type);
-            break;
-        case POWERPC_MMU_BOOKE206:
-            ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw,
+        }
+        break;
+    case POWERPC_MMU_BOOKE:
+        ret = mmubooke_get_physical_address(env, ctx, eaddr,
+                                            rw, access_type);
+        break;
+    case POWERPC_MMU_BOOKE206:
+        ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw,
                                                access_type);
-            break;
-        case POWERPC_MMU_MPC8xx:
-            /* XXX: TODO */
-            cpu_abort(env, "MPC8xx MMU model is not implemented\n");
-            break;
-        case POWERPC_MMU_REAL:
+        break;
+    case POWERPC_MMU_MPC8xx:
+        /* XXX: TODO */
+        cpu_abort(env, "MPC8xx MMU model is not implemented\n");
+        break;
+    case POWERPC_MMU_REAL:
+        if (real_mode) {
+            ret = check_physical(env, ctx, eaddr, rw);
+        } else {
             cpu_abort(env, "PowerPC in real mode do not do any translation\n");
-            return -1;
-        default:
-            cpu_abort(env, "Unknown or invalid MMU model\n");
-            return -1;
         }
+        return -1;
+    default:
+        cpu_abort(env, "Unknown or invalid MMU model\n");
+        return -1;
     }
 #if 0
     qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n",
-- 
1.7.10.4

  parent reply	other threads:[~2013-03-12 10:33 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-03-12 10:31 [Qemu-devel] [0/48] target-ppc: MMU implementation cleanup for hash MMUs David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 01/48] target-ppc: Remove vestigial PowerPC 620 support David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 02/48] target-ppc: Trivial cleanups in mmu_helper.c David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 03/48] target-ppc: Remove address check for logging David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 04/48] target-ppc: Move SLB handling into a mmu-hash64.c David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 05/48] target-ppc: Disentangle pte_check() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 06/48] target-ppc: Disentangle find_pte() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 07/48] target-ppc: Disentangle get_segment() David Gibson
2013-03-12 10:31 ` David Gibson [this message]
2013-03-12 10:31 ` [Qemu-devel] [PATCH 09/48] target-ppc: Disentangle get_physical_address() paths David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 10/48] target-ppc: Disentangle hash mmu paths for cpu_ppc_handle_mmu_fault David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 11/48] target-ppc: Disentangle hash mmu versions of cpu_get_phys_page_debug() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 12/48] target-ppc: Disentangle hash mmu helper functions David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 13/48] target-ppc: Don't share get_pteg_offset() between 32 and 64-bit David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 14/48] target-ppc: Disentangle BAT code for 32-bit hash MMUs David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 15/48] target-ppc: mmu_ctx_t should not be a global type David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 16/48] mmu-hash*: Add header file for definitions David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 17/48] mmu-hash*: Add hash pte load/store helpers David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 18/48] mmu-hash*: Reduce use of access_type David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 19/48] mmu-hash64: Remove nx from mmu_ctx_hash64 David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 20/48] mmu-hash*: Remove eaddr field from mmu_ctx_hash{32, 64} David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 21/48] mmu-hash*: Combine ppc_hash{32, 64}_get_physical_address and get_segment{32, 64}() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 22/48] mmu-hash32: Split out handling of direct store segments David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 23/48] mmu-hash32: Split direct store segment handling into a helper David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 24/48] mmu-hash*: Cleanup segment-level NX check David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 25/48] mmu-hash*: Don't keep looking for PTEs after we find a match David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 26/48] mmu-hash*: Separate PTEG searching from permissions checking David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 27/48] mmu-hash*: Make find_pte{32, 64} do more of the job of finding ptes David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 28/48] mmu-hash*: Remove permission checking from find_pte{32, 64}() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 29/48] mmu-hash64: Clean up ppc_hash64_htab_lookup() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 30/48] mmu-hash*: Fold pte_check*() logic into caller David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 31/48] mmu-hash32: Remove odd pointer usage from BAT code David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 32/48] mmu-hash32: Split BAT size logic from permissions logic David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 33/48] mmu-hash32: Clean up BAT matching logic David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 34/48] mmu-hash32: Cleanup BAT lookup David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 35/48] mmu-hash32: Don't look up page tables on BAT permission error David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 36/48] mmu-hash*: Don't update PTE flags when permission is denied David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 37/48] mmu-hash32: Remove nx from context structure David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 38/48] mmu-hash*: Clean up permission checking David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 39/48] mmu-hash64: Factor SLB N bit into permissions bits David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 40/48] mmu-hash*: Clean up PTE flags update David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 41/48] mmu-hash*: Clean up real address calculation David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 42/48] mmu-hash*: Correctly mask RPN from hash PTE David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 43/48] mmu-hash*: Don't use full ppc_hash{32, 64}_translate() path for get_phys_page_debug() David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 44/48] mmu-hash*: Merge translate and fault handling functions David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 45/48] mmu-hash64: Implement Virtual Page Class Key Protection David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 46/48] target-ppc: Split user only code out of mmu_helper.c David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 47/48] target-ppc: Move ppc tlb_fill implementation into mmu_helper.c David Gibson
2013-03-12 10:31 ` [Qemu-devel] [PATCH 48/48] target-ppc: Use QOM method dispatch for MMU fault handling David Gibson
2013-03-13  0:42   ` [Qemu-devel] [Qemu-ppc] " David Gibson
2013-03-21 13:43 ` [Qemu-devel] [0/48] target-ppc: MMU implementation cleanup for hash MMUs Alexander Graf

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1363084310-4115-9-git-send-email-david@gibson.dropbear.id.au \
    --to=david@gibson.dropbear.id.au \
    --cc=afaerber@suse.de \
    --cc=agraf@suse.de \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).