From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:32800) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UGGN1-0001UE-2w for qemu-devel@nongnu.org; Thu, 14 Mar 2013 18:11:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UGGMz-0004pG-5H for qemu-devel@nongnu.org; Thu, 14 Mar 2013 18:11:31 -0400 Received: from smtp1-g21.free.fr ([2a01:e0c:1:1599::10]:39096) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UGGMy-0004p0-FU for qemu-devel@nongnu.org; Thu, 14 Mar 2013 18:11:29 -0400 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Thu, 14 Mar 2013 23:12:07 +0100 Message-Id: <1363299128-8494-7-git-send-email-hpoussin@reactos.org> In-Reply-To: <1363299128-8494-1-git-send-email-hpoussin@reactos.org> References: <1363299128-8494-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [RFC 6/6] prep: QOM'ify System I/O List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= Most of the functionality is extracted from hw/ppc/prep.c. Also add support for board identification/equipment registers. Document it for the IBM 43p emulation. Signed-off-by: Herv=C3=A9 Poussineau --- docs/ibm_43p.cfg | 5 + hw/ppc/Makefile.objs | 1 + hw/ppc/prep_systemio.c | 290 ++++++++++++++++++++++++++++++++++++++++++= ++++++ trace-events | 4 + 4 files changed, 300 insertions(+) create mode 100644 hw/ppc/prep_systemio.c diff --git a/docs/ibm_43p.cfg b/docs/ibm_43p.cfg index 55329e3..2a97e3f 100644 --- a/docs/ibm_43p.cfg +++ b/docs/ibm_43p.cfg @@ -41,3 +41,8 @@ =20 [device] driver =3D "rs6000-debug" + +[device] + driver =3D "prep-systemio800" + ibm-planar-id =3D "0xc0" + equipment =3D "0xff" diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs index 8be8264..b584902 100644 --- a/hw/ppc/Makefile.objs +++ b/hw/ppc/Makefile.objs @@ -23,6 +23,7 @@ obj-$(CONFIG_PSERIES) +=3D spapr_hcall.o spapr_iommu.o = spapr_rtas.o obj-y +=3D ppc405_boards.o ppc4xx_devs.o ppc405_uc.o ppc440_bamboo.o # PReP obj-y +=3D prep.o +obj-y +=3D prep_systemio.o obj-y +=3D rs6000_debug.o # OldWorld PowerMac obj-y +=3D mac_oldworld.o diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c new file mode 100644 index 0000000..ddd54d1 --- /dev/null +++ b/hw/ppc/prep_systemio.c @@ -0,0 +1,290 @@ +/* + * QEMU PReP System I/O emulation + * + * Copyright (c) 2003-2007 Jocelyn Mayer + * Copyright (c) 2010-2012 Herve Poussineau + * Copyright (c) 2010-2011 Andreas Faerber + * + * Permission is hereby granted, free of charge, to any person obtaining= a copy + * of this software and associated documentation files (the "Software"),= to deal + * in the Software without restriction, including without limitation the= rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or = sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be includ= ed in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRE= SS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILI= TY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHA= LL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR = OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISI= NG FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALING= S IN + * THE SOFTWARE. + */ + +#include "hw/isa.h" +#include "exec/address-spaces.h" +#include "qemu/error-report.h" /* for error_report() */ +#include "sysemu/sysemu.h" /* for vm_stop() */ +#include "trace.h" + +/* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132= */ +#define BIT(n) (1 << (7 - (n))) + +typedef struct PrepIo800State { + ISADevice dev; + MemoryRegion ppc_parity_mem; + + qemu_irq non_contiguous_io_map_irq; + uint8_t equipment; /* 0x080c */ + uint8_t system_control; /* 0x081c */ + uint8_t iomap_type; /* 0x0850 */ + uint8_t ibm_planar_id; /* 0x0852 */ + qemu_irq softreset_irq; +} PrepIo800State; + +/* PORT 0092 -- Special Port 92 (Read/Write) */ + +enum { + PORT0092_SOFTRESET =3D BIT(7), + PORT0092_LE_MODE =3D BIT(6), +}; + +static void prep_port0092_write(void *opaque, uint32_t addr, uint32_t va= l) +{ + PrepIo800State *s =3D opaque; + + trace_prep_systemio_write(addr, val); + + if ((val & PORT0092_SOFTRESET) !=3D 0) { + qemu_irq_raise(s->softreset_irq); + } else { + qemu_irq_lower(s->softreset_irq); + } + + if ((val & PORT0092_LE_MODE) !=3D 0) { + /* XXX Not supported yet */ + error_report("little-endian mode not supported"); + vm_stop(RUN_STATE_PAUSED); + } else { + /* Nothing to do */ + } +} + +static uint32_t prep_port0092_read(void *opaque, uint32_t addr) +{ + /* XXX LE mode unsupported */ + trace_prep_systemio_read(addr, 0); + return 0; +} + +/* PORT 0808 -- Hardfile Light Register (Write Only) */ + +enum { + PORT0808_HARDFILE_LIGHT_ON =3D BIT(7), +}; + +static void prep_port0808_write(void *opaque, uint32_t addr, uint32_t va= l) +{ + trace_prep_systemio_write(addr, val); +} + +/* PORT 0810 -- Password Protect 1 Register (Write Only) */ + +/* reset by port 0x4D in the SIO */ +static void prep_port0810_write(void *opaque, uint32_t addr, uint32_t va= l) +{ + trace_prep_systemio_write(addr, val); +} + +/* PORT 0812 -- Password Protect 2 Register (Write Only) */ + +/* reset by port 0x4D in the SIO */ +static void prep_port0812_write(void *opaque, uint32_t addr, uint32_t va= l) +{ + trace_prep_systemio_write(addr, val); +} + +/* PORT 0814 -- L2 Invalidate Register (Write Only) */ + +static void prep_port0814_write(void *opaque, uint32_t addr, uint32_t va= l) +{ + trace_prep_systemio_write(addr, val); +} + +/* PORT 0818 -- Reserved for Keylock (Read Only) */ + +enum { + PORT0818_KEYLOCK_SIGNAL_HIGH =3D BIT(7), +}; + +static uint32_t prep_port0818_read(void *opaque, uint32_t addr) +{ + uint32_t val =3D 0; + trace_prep_systemio_read(addr, val); + return val; +} + +/* PORT 080C -- Equipment */ + +enum { + PORT080C_SCSIFUSE =3D BIT(1), + PORT080C_L2_COPYBACK =3D BIT(4), + PORT080C_L2_256 =3D BIT(5), + PORT080C_UPGRADE_CPU =3D BIT(6), + PORT080C_L2 =3D BIT(7), +}; + +static uint32_t prep_port080c_read(void *opaque, uint32_t addr) +{ + PrepIo800State *s =3D opaque; + trace_prep_systemio_read(addr, s->equipment); + return s->equipment; +} + +/* PORT 081C -- System Control Register (Read/Write) */ + +enum { + PORT081C_FLOPPY_MOTOR_INHIBIT =3D BIT(3), + PORT081C_MASK_TEA =3D BIT(2), + PORT081C_L2_UPDATE_INHIBIT =3D BIT(1), + PORT081C_L2_CACHEMISS_INHIBIT =3D BIT(0), +}; + +static void prep_port081c_write(void *opaque, uint32_t addr, uint32_t va= l) +{ + PrepIo800State *s =3D opaque; + trace_prep_systemio_write(addr, val); + s->system_control =3D val; +} + +static uint32_t prep_port081c_read(void *opaque, uint32_t addr) +{ + PrepIo800State *s =3D opaque; + trace_prep_systemio_read(addr, s->system_control); + return s->system_control; +} + +/* System Board Identification */ + +static uint32_t prep_port0852_read(void *opaque, uint32_t addr) +{ + PrepIo800State *s =3D opaque; + trace_prep_systemio_read(addr, s->ibm_planar_id); + return s->ibm_planar_id; +} + +/* PORT 0850 -- I/O Map Type Register (Read/Write) */ + +enum { + PORT0850_IOMAP_NONCONTIGUOUS =3D BIT(7), +}; + +static uint32_t prep_port0850_read(void *opaque, uint32_t addr) +{ + PrepIo800State *s =3D opaque; + trace_prep_systemio_read(addr, s->iomap_type); + return s->iomap_type; +} + +static void prep_port0850_write(void *opaque, uint32_t addr, uint32_t va= l) +{ + PrepIo800State *s =3D opaque; + + trace_prep_systemio_write(addr, val); + qemu_set_irq(s->non_contiguous_io_map_irq, + val & PORT0850_IOMAP_NONCONTIGUOUS ? 1 : 0); + s->iomap_type =3D val; +} + +static const MemoryRegionPortio ppc_io800_port_list[] =3D { + { 0x092, 1, 1, .read =3D prep_port0092_read, + .write =3D prep_port0092_write, }, + { 0x808, 1, 1, .write =3D prep_port0808_write, }, + { 0x80c, 1, 1, .read =3D prep_port080c_read, }, + { 0x810, 1, 1, .write =3D prep_port0810_write, }, + { 0x812, 1, 1, .write =3D prep_port0812_write, }, + { 0x814, 1, 1, .write =3D prep_port0814_write, }, + { 0x818, 1, 1, .read =3D prep_port0818_read, }, + { 0x81c, 1, 1, .read =3D prep_port081c_read, + .write =3D prep_port081c_write, }, + { 0x850, 1, 1, .read =3D prep_port0850_read, + .write =3D prep_port0850_write, }, + { 0x852, 1, 1, .read =3D prep_port0852_read, }, + PORTIO_END_OF_LIST() +}; + +static uint64_t ppc_parity_error_readl(void *opaque, hwaddr addr, + unsigned int size) +{ + uint32_t val =3D 0; + trace_prep_systemio_read((unsigned int)addr, val); + return val; +} + +static const MemoryRegionOps ppc_parity_error_ops =3D { + .read =3D ppc_parity_error_readl, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static int prep_systemio_init(ISADevice *dev) +{ + PrepIo800State *s =3D DO_UPCAST(PrepIo800State, dev, dev); + qdev_init_gpio_out(&dev->qdev, &s->non_contiguous_io_map_irq, 1); + s->iomap_type =3D 0; /* contiguous mode XXX 0x1? */ + s->softreset_irq =3D first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; + + isa_register_portio_list(dev, 0x0, ppc_io800_port_list, s, "systemio= 800"); + + memory_region_init_io(&s->ppc_parity_mem, &ppc_parity_error_ops, s, + "ppc-parity", 0x4); + memory_region_add_subregion(get_system_memory(), 0xbfffeff0, + &s->ppc_parity_mem); + return 0; +} + +static const VMStateDescription vmstate_prep_systemio =3D { + .name =3D "prep_systemio", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(system_control, PrepIo800State), + VMSTATE_UINT8(iomap_type, PrepIo800State), + VMSTATE_END_OF_LIST() + }, +}; + +static Property prep_systemio_properties[] =3D { + DEFINE_PROP_UINT8("ibm-planar-id", PrepIo800State, ibm_planar_id, 0)= , + DEFINE_PROP_UINT8("equipment", PrepIo800State, equipment, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void prep_systemio_class_initfn(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ISADeviceClass *ic =3D ISA_DEVICE_CLASS(klass); + ic->init =3D prep_systemio_init; + dc->vmsd =3D &vmstate_prep_systemio; + dc->props =3D prep_systemio_properties; + dc->no_user =3D 1; +} + +static TypeInfo prep_systemio800_info =3D { + .name =3D "prep-systemio800", + .parent =3D TYPE_ISA_DEVICE, + .instance_size =3D sizeof(PrepIo800State), + .class_init =3D prep_systemio_class_initfn, +}; + +static void prep_systemio_register_types(void) +{ + type_register_static(&prep_systemio800_info); +} + +type_init(prep_systemio_register_types) diff --git a/trace-events b/trace-events index 49ab9d5..8173da4 100644 --- a/trace-events +++ b/trace-events @@ -757,6 +757,10 @@ pc87312_info_ide(uint32_t base) "base 0x%x" pc87312_info_parallel(uint32_t base, uint32_t irq) "base 0x%x, irq %u" pc87312_info_serial(int n, uint32_t base, uint32_t irq) "id=3D%d, base 0= x%x, irq %u" =20 +# hw/ppc/prep_systemio.c +prep_systemio_read(uint32_t addr, uint32_t val) "read addr=3D%x val=3D%x= " +prep_systemio_write(uint32_t addr, uint32_t val) "write addr=3D%x val=3D= %x" + # hw/mpc105.c mpc105_unassigned_mem_read(uint64_t addr) "Unassigned mem read %" PRIx64 mpc105_unassigned_mem_write(uint64_t addr, uint64_t val) "Unassigned mem= write %" PRIx64 " =3D 0x%" PRIx64 --=20 1.7.10.4