From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:57217) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULEpO-0000kp-Jc for qemu-devel@nongnu.org; Thu, 28 Mar 2013 11:33:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ULEpL-0003VE-Cs for qemu-devel@nongnu.org; Thu, 28 Mar 2013 11:33:22 -0400 Received: from mail-pb0-f49.google.com ([209.85.160.49]:63030) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULEpL-0003V3-3w for qemu-devel@nongnu.org; Thu, 28 Mar 2013 11:33:19 -0400 Received: by mail-pb0-f49.google.com with SMTP id um15so2087689pbc.22 for ; Thu, 28 Mar 2013 08:33:18 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 28 Mar 2013 08:32:45 -0700 Message-Id: <1364484781-15561-5-git-send-email-rth@twiddle.net> In-Reply-To: <1364484781-15561-1-git-send-email-rth@twiddle.net> References: <1364484781-15561-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v3 04/20] tcg-arm: Use tcg_out_dat_rIN for compares List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Aurelien Jarno This allows us to emit CMN instructions. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 7475142..3152798 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1655,10 +1655,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, /* Constraints mean that v2 is always in the same register as dest, * so we only need to do "if condition passed, move v1 to dest". */ - tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, - args[1], args[2], const_args[2]); - tcg_out_dat_rI(s, tcg_cond_to_arm_cond[args[5]], - ARITH_MOV, args[0], 0, args[3], const_args[3]); + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, + args[1], args[2], const_args[2]); + tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV, + ARITH_MVN, args[0], 0, args[3], const_args[3]); break; case INDEX_op_add_i32: tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, @@ -1755,7 +1755,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_brcond_i32: - tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, args[0], args[1], const_args[1]); tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]); break; @@ -1768,15 +1768,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3), * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3, */ - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, - args[1], args[3], SHIFT_IMM_LSL(0)); - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, - args[0], args[2], SHIFT_IMM_LSL(0)); + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, + args[1], args[3], const_args[3]); + tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, + args[0], args[2], const_args[2]); tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]); break; case INDEX_op_setcond_i32: - tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, - args[1], args[2], const_args[2]); + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, + args[1], args[2], const_args[2]); tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], ARITH_MOV, args[0], 0, 1); tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], @@ -1784,10 +1784,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_setcond2_i32: /* See brcond2_i32 comment */ - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, - args[2], args[4], SHIFT_IMM_LSL(0)); - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, - args[1], args[3], SHIFT_IMM_LSL(0)); + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, + args[2], args[4], const_args[4]); + tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, + args[1], args[3], const_args[3]); tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV, args[0], 0, 1); tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])], @@ -1885,15 +1885,15 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_rotl_i32, { "r", "r", "ri" } }, { INDEX_op_rotr_i32, { "r", "r", "ri" } }, - { INDEX_op_brcond_i32, { "r", "rI" } }, - { INDEX_op_setcond_i32, { "r", "r", "rI" } }, - { INDEX_op_movcond_i32, { "r", "r", "rI", "rI", "0" } }, + { INDEX_op_brcond_i32, { "r", "rIN" } }, + { INDEX_op_setcond_i32, { "r", "r", "rIN" } }, + { INDEX_op_movcond_i32, { "r", "r", "rIN", "rIK", "0" } }, /* TODO: "r", "r", "r", "r", "ri", "ri" */ { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } }, { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } }, - { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } }, - { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } }, + { INDEX_op_brcond2_i32, { "r", "r", "rIN", "rIN" } }, + { INDEX_op_setcond2_i32, { "r", "r", "r", "rIN", "rIN" } }, #if TARGET_LONG_BITS == 32 { INDEX_op_qemu_ld8u, { "r", "l" } }, -- 1.8.1.4