From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:45969) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULlLX-0005Vc-NP for qemu-devel@nongnu.org; Fri, 29 Mar 2013 22:16:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ULlLV-0008Sz-Bo for qemu-devel@nongnu.org; Fri, 29 Mar 2013 22:16:43 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:40208) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULlLV-0008Sr-4w for qemu-devel@nongnu.org; Fri, 29 Mar 2013 22:16:41 -0400 From: Aurelien Jarno Date: Sat, 30 Mar 2013 03:16:31 +0100 Message-Id: <1364609794-16753-3-git-send-email-aurelien@aurel32.net> In-Reply-To: <1364609794-16753-1-git-send-email-aurelien@aurel32.net> References: <1364609794-16753-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH 2/5] target-i386: enable PCLMULQDQ on Westmere CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno The PCLMULQDQ instruction has been introduced on the Westmere CPU. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 41382c5..5941d40 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -687,7 +687,7 @@ static x86_def_t builtin_x86_defs[] = { CPUID_DE | CPUID_FP87, .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | - CPUID_EXT_SSE3, + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .ext3_features = CPUID_EXT3_LAHF_LM, .xlevel = 0x8000000A, -- 1.7.10.4