From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:32813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMQqW-0000BX-D6 for qemu-devel@nongnu.org; Sun, 31 Mar 2013 18:35:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UMQqS-0007lt-U1 for qemu-devel@nongnu.org; Sun, 31 Mar 2013 18:35:28 -0400 Received: from mail-da0-x232.google.com ([2607:f8b0:400e:c00::232]:41242) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMQqS-0007lj-Ow for qemu-devel@nongnu.org; Sun, 31 Mar 2013 18:35:24 -0400 Received: by mail-da0-f50.google.com with SMTP id t1so823869dae.9 for ; Sun, 31 Mar 2013 15:35:24 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Sun, 31 Mar 2013 15:34:51 -0700 Message-Id: <1364769305-3687-6-git-send-email-rth@twiddle.net> In-Reply-To: <1364769305-3687-1-git-send-email-rth@twiddle.net> References: <1364769305-3687-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v5 05/19] tcg-arm: Allow constant first argument to sub List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno This allows the generation of RSB instructions. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index f34828b..a430f1b 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1625,8 +1625,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, args[0], args[1], args[2], const_args[2]); break; case INDEX_op_sub_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, - args[0], args[1], args[2], const_args[2]); + if (const_args[1]) { + if (const_args[2]) { + tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); + } else { + tcg_out_dat_rI(s, COND_AL, ARITH_RSB, + args[0], args[2], args[1], 1); + } + } else { + tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, + args[0], args[1], args[2], const_args[2]); + } break; case INDEX_op_and_i32: tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, @@ -1819,7 +1828,7 @@ static const TCGTargetOpDef arm_op_defs[] = { /* TODO: "r", "r", "ri" */ { INDEX_op_add_i32, { "r", "r", "rIN" } }, - { INDEX_op_sub_i32, { "r", "r", "rIN" } }, + { INDEX_op_sub_i32, { "r", "rI", "rIN" } }, { INDEX_op_mul_i32, { "r", "r", "r" } }, { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, { INDEX_op_muls2_i32, { "r", "r", "r", "r" } }, -- 1.8.1.4