From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:57909) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMslg-0002zq-65 for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UMsld-0007Ns-LB for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:20 -0400 Received: from mail-gg0-x233.google.com ([2607:f8b0:4002:c02::233]:56600) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMsld-0007Nm-Gp for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:17 -0400 Received: by mail-gg0-f179.google.com with SMTP id i2so2543ggm.38 for ; Mon, 01 Apr 2013 21:24:17 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 1 Apr 2013 21:23:15 -0700 Message-Id: <1364876610-3933-13-git-send-email-rth@twiddle.net> In-Reply-To: <1364876610-3933-1-git-send-email-rth@twiddle.net> References: <1364876610-3933-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v3 12/27] tcg-ppc64: Improve and_i32 with constant List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: av1474@comtv.ru, agraf@suse.de, aurelien@aurel32.net Use RLWINM Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 9718ef6..ad6db6c 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -527,6 +527,48 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, } } +static inline bool mask_operand(uint32_t c, int *mb, int *me) +{ + uint32_t lsb, test; + + /* Accept a bit pattern like: + 0....01....1 + 1....10....0 + 0..01..10..0 + Keep track of the transitions. */ + if (c == 0 || c == -1) { + return false; + } + test = c; + lsb = test & -test; + test += lsb; + if (test & (test - 1)) { + return false; + } + + *me = clz32(lsb); + *mb = test ? clz32(test & -test) + 1 : 0; + return true; +} + +static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) +{ + int mb, me; + + if ((c & 0xffff) == c) { + tcg_out32(s, ANDI | SAI(src, dst, c)); + return; + } else if ((c & 0xffff0000) == c) { + tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); + return; + } else if (mask_operand(c, &mb, &me)) { + tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); + } else { + tcg_out_movi(s, TCG_TYPE_I32, 0, c); + tcg_out32(s, AND | SAB(src, dst, 0)); + } +} + static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c, int op_lo, int op_hi) { @@ -1346,9 +1388,15 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; - case INDEX_op_and_i64: case INDEX_op_and_i32: if (const_args[2]) { + tcg_out_andi32(s, args[0], args[1], args[2]); + } else { + tcg_out32(s, AND | SAB(args[1], args[0], args[2])); + } + break; + case INDEX_op_and_i64: + if (const_args[2]) { if ((args[2] & 0xffff) == args[2]) { tcg_out32(s, ANDI | SAI(args[1], args[0], args[2])); } else if ((args[2] & 0xffff0000) == args[2]) { -- 1.8.1.4