From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:58040) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMslv-0003U1-OQ for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UMslr-0007ax-9v for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:35 -0400 Received: from mail-gg0-x232.google.com ([2607:f8b0:4002:c02::232]:46262) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMslr-0007ZT-3k for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:31 -0400 Received: by mail-gg0-f178.google.com with SMTP id e5so2708ggh.37 for ; Mon, 01 Apr 2013 21:24:30 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 1 Apr 2013 21:23:24 -0700 Message-Id: <1364876610-3933-22-git-send-email-rth@twiddle.net> In-Reply-To: <1364876610-3933-1-git-send-email-rth@twiddle.net> References: <1364876610-3933-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v3 21/27] tcg-ppc64: Use I constraint for mul List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: av1474@comtv.ru, agraf@suse.de, aurelien@aurel32.net The mul_i32 pattern was loading non-16-bit constants into a register, when we can get the middle-end to do that for us. The mul_i64 pattern was not considering that MULLI takes 64-bit inputs. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index bd12b5c..69e558d 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1465,17 +1465,12 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_mul_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - if (args[2] == (int16_t) args[2]) - tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1]) - | (args[2] & 0xffff)); - else { - tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]); - tcg_out32 (s, MULLW | TAB (args[0], args[1], 0)); - } + tcg_out32(s, MULLI | TAI(a0, a1, a2)); + } else { + tcg_out32(s, MULLW | TAB(a0, a1, a2)); } - else - tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2])); break; case INDEX_op_div_i32: @@ -1634,7 +1629,12 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_mul_i64: - tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2])); + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out32(s, MULLI | TAI(a0, a1, a2)); + } else { + tcg_out32(s, MULLD | TAB(a0, a1, a2)); + } break; case INDEX_op_div_i64: tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2])); @@ -1836,7 +1836,7 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_ld32s_i64, { "r", "r" } }, { INDEX_op_add_i32, { "r", "r", "ri" } }, - { INDEX_op_mul_i32, { "r", "r", "ri" } }, + { INDEX_op_mul_i32, { "r", "r", "rI" } }, { INDEX_op_div_i32, { "r", "r", "r" } }, { INDEX_op_divu_i32, { "r", "r", "r" } }, { INDEX_op_rem_i32, { "r", "r", "r" } }, @@ -1880,7 +1880,7 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_rotl_i64, { "r", "r", "ri" } }, { INDEX_op_rotr_i64, { "r", "r", "ri" } }, - { INDEX_op_mul_i64, { "r", "r", "r" } }, + { INDEX_op_mul_i64, { "r", "r", "rI" } }, { INDEX_op_div_i64, { "r", "r", "r" } }, { INDEX_op_divu_i64, { "r", "r", "r" } }, { INDEX_op_rem_i64, { "r", "r", "r" } }, -- 1.8.1.4