From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:58140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMsm5-0003kC-40 for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UMsm2-0007kg-GK for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:45 -0400 Received: from mail-gg0-x22d.google.com ([2607:f8b0:4002:c02::22d]:41501) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMsm2-0007kZ-Cq for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:42 -0400 Received: by mail-gg0-f173.google.com with SMTP id 21so3125ggh.4 for ; Mon, 01 Apr 2013 21:24:42 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 1 Apr 2013 21:23:30 -0700 Message-Id: <1364876610-3933-28-git-send-email-rth@twiddle.net> In-Reply-To: <1364876610-3933-1-git-send-email-rth@twiddle.net> References: <1364876610-3933-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v3 27/27] tcg-ppc64: Implement mulu2/muls2_i64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: av1474@comtv.ru, agraf@suse.de, aurelien@aurel32.net Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 27 +++++++++++++++++++++++++++ tcg/ppc64/tcg-target.h | 4 ++-- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 0e60589..cdfc07b 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -2012,6 +2012,31 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i64: + { + int oph = (opc == INDEX_op_mulu2_i64 ? MULHDU : MULHD); + TCGReg outl = args[0], outh = args[1]; + a0 = args[2], a1 = args[3]; + + if (outl == a0 || outl == a1) { + if (outh == a0 || outh == a1) { + outl = TCG_REG_R0; + } else { + tcg_out32(s, oph | TAB(outh, a0, a1)); + oph = 0; + } + } + tcg_out32(s, MULLD | TAB(outl, a0, a1)); + if (oph != 0) { + tcg_out32(s, oph | TAB(outh, a0, a1)); + } + if (outl != args[0]) { + tcg_out_mov(s, TCG_TYPE_I64, args[0], outl); + } + } + break; + default: tcg_dump_ops (s); tcg_abort (); @@ -2141,6 +2166,8 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_add2_i64, { "r", "r", "r", "rI", "r", "rZM" } }, { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } }, + { INDEX_op_muls2_i64, { "r", "r", "r", "r" } }, + { INDEX_op_mulu2_i64, { "r", "r", "r", "r" } }, { -1 }, }; diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index b8cc97c..d4b0763 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -114,8 +114,8 @@ typedef enum { #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 -#define TCG_TARGET_HAS_mulu2_i64 0 -#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_mulu2_i64 1 +#define TCG_TARGET_HAS_muls2_i64 1 #define TCG_AREG0 TCG_REG_R27 -- 1.8.1.4