From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:34837) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UN8z0-0008U7-Er for qemu-devel@nongnu.org; Tue, 02 Apr 2013 17:43:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UN8yx-0005l5-Ts for qemu-devel@nongnu.org; Tue, 02 Apr 2013 17:43:10 -0400 Received: from mail-qe0-f46.google.com ([209.85.128.46]:61618) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UN8yx-0005l1-Q4 for qemu-devel@nongnu.org; Tue, 02 Apr 2013 17:43:07 -0400 Received: by mail-qe0-f46.google.com with SMTP id a11so516889qen.19 for ; Tue, 02 Apr 2013 14:43:07 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 2 Apr 2013 14:42:34 -0700 Message-Id: <1364938954-1825-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [CFT] target-ppc: Fix narrow-mode add/sub carry output List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno Broken in b5a73f8d8a57e940f9bbeb399a9e47897522ee9a, the carry itself was fixed in 79482e5ab38a05ca8869040b0d8b8f451f16ff62. But we still need to produce the full 64-bit addition. Cc: Aurelien Jarno Signed-off-by: Richard Henderson --- Aurelien, you reported this bug, but I'm unable to reproduce it at the moment. That test program you sent along is broken, attempting to run insns in pages without the execute bit set. I don't have time to fix that today. But per IRC, I think we know what the problem is. And at least this runs the linux-user-0.3 ppc binaries properly. Hopefully it'll solve the real problem with your guest openssl. r~ --- target-ppc/translate.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 5e741d1..1feadca 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -775,15 +775,19 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, if (compute_ca) { if (NARROW_MODE(ctx)) { + /* Caution: a non-obvious corner case of the spec is that we + must produce the *entire* 64-bit addition, but produce the + carry into bit 32. */ TCGv t1 = tcg_temp_new(); - tcg_gen_ext32u_tl(t1, arg2); - tcg_gen_ext32u_tl(t0, arg1); - tcg_gen_add_tl(t0, t0, t1); - tcg_temp_free(t1); + tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ + tcg_gen_add_tl(t0, arg1, arg2); if (add_ca) { tcg_gen_add_tl(t0, t0, cpu_ca); } - tcg_gen_shri_tl(cpu_ca, t0, 32); + tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ + tcg_temp_free(t1); + tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ + tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); } else { TCGv zero = tcg_const_tl(0); if (add_ca) { @@ -1129,17 +1133,23 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, if (compute_ca) { /* dest = ~arg1 + arg2 [+ ca]. */ if (NARROW_MODE(ctx)) { + /* Caution: a non-obvious corner case of the spec is that we + must produce the *entire* 64-bit addition, but produce the + carry into bit 32. */ TCGv inv1 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); tcg_gen_not_tl(inv1, arg1); - tcg_gen_ext32u_tl(t0, arg2); - tcg_gen_ext32u_tl(inv1, inv1); if (add_ca) { - tcg_gen_add_tl(t0, t0, cpu_ca); + tcg_gen_add_tl(t0, arg2, cpu_ca); } else { - tcg_gen_addi_tl(t0, t0, 1); + tcg_gen_addi_tl(t0, arg2, 1); } + tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ tcg_gen_add_tl(t0, t0, inv1); - tcg_gen_shri_tl(cpu_ca, t0, 32); + tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ + tcg_temp_free(t1); + tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ + tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); } else if (add_ca) { TCGv zero, inv1 = tcg_temp_new(); tcg_gen_not_tl(inv1, arg1); -- 1.8.1.4