From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40502) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNKzM-0000nx-Mz for qemu-devel@nongnu.org; Wed, 03 Apr 2013 06:32:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UNKzL-0004GH-0d for qemu-devel@nongnu.org; Wed, 03 Apr 2013 06:32:20 -0400 Received: from mail-wi0-x235.google.com ([2a00:1450:400c:c05::235]:35304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNKzK-0004G3-QC for qemu-devel@nongnu.org; Wed, 03 Apr 2013 06:32:18 -0400 Received: by mail-wi0-f181.google.com with SMTP id hj8so1345952wib.14 for ; Wed, 03 Apr 2013 03:32:18 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Wed, 3 Apr 2013 12:32:00 +0200 Message-Id: <1364985128-23772-3-git-send-email-pbonzini@redhat.com> In-Reply-To: <1364985128-23772-1-git-send-email-pbonzini@redhat.com> References: <1364985128-23772-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH v2 02/10] elfload: fix size of registers for N32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net, pmaydell@linaro.org Registers are 64-bit in size for the MIPS n32 ABI. Define target_elf_greg_t accordingly, and use the correct function to do endian swaps. Signed-off-by: Paolo Bonzini --- linux-user/elfload.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index d3589ff..9d5dbb8 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -101,7 +101,14 @@ enum { #define ELF_DATA ELFDATA2LSB #endif +#ifdef TARGET_ABI_MIPSN32 typedef target_ulong target_elf_greg_t; +#define tswapreg(ptr) tswapl(ptr) +#else +typedef abi_ulong target_elf_greg_t; +#define tswapreg(ptr) tswapal(ptr) +#endif + #ifdef USE_UID16 typedef target_ushort target_uid_t; typedef target_ushort target_gid_t; @@ -747,17 +754,17 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMIPSState *e (*regs)[TARGET_EF_R0] = 0; for (i = 1; i < ARRAY_SIZE(env->active_tc.gpr); i++) { - (*regs)[TARGET_EF_R0 + i] = tswapl(env->active_tc.gpr[i]); + (*regs)[TARGET_EF_R0 + i] = tswapreg(env->active_tc.gpr[i]); } (*regs)[TARGET_EF_R26] = 0; (*regs)[TARGET_EF_R27] = 0; - (*regs)[TARGET_EF_LO] = tswapl(env->active_tc.LO[0]); - (*regs)[TARGET_EF_HI] = tswapl(env->active_tc.HI[0]); - (*regs)[TARGET_EF_CP0_EPC] = tswapl(env->active_tc.PC); - (*regs)[TARGET_EF_CP0_BADVADDR] = tswapl(env->CP0_BadVAddr); - (*regs)[TARGET_EF_CP0_STATUS] = tswapl(env->CP0_Status); - (*regs)[TARGET_EF_CP0_CAUSE] = tswapl(env->CP0_Cause); + (*regs)[TARGET_EF_LO] = tswapreg(env->active_tc.LO[0]); + (*regs)[TARGET_EF_HI] = tswapreg(env->active_tc.HI[0]); + (*regs)[TARGET_EF_CP0_EPC] = tswapreg(env->active_tc.PC); + (*regs)[TARGET_EF_CP0_BADVADDR] = tswapreg(env->CP0_BadVAddr); + (*regs)[TARGET_EF_CP0_STATUS] = tswapreg(env->CP0_Status); + (*regs)[TARGET_EF_CP0_CAUSE] = tswapreg(env->CP0_Cause); } #define USE_ELF_CORE_DUMP -- 1.8.1.4