From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47785) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNt6M-0006nv-77 for qemu-devel@nongnu.org; Thu, 04 Apr 2013 18:57:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UNt6F-0001Tl-Tw for qemu-devel@nongnu.org; Thu, 04 Apr 2013 18:57:50 -0400 Received: from mail-oa0-f54.google.com ([209.85.219.54]:37116) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNt6F-0001TZ-K3 for qemu-devel@nongnu.org; Thu, 04 Apr 2013 18:57:43 -0400 Received: by mail-oa0-f54.google.com with SMTP id n12so3440050oag.13 for ; Thu, 04 Apr 2013 15:57:43 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 4 Apr 2013 17:56:26 -0500 Message-Id: <1365116186-19382-34-git-send-email-rth@twiddle.net> In-Reply-To: <1365116186-19382-1-git-send-email-rth@twiddle.net> References: <1365116186-19382-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v4 33/33] tcg-ppc64: Handle deposit of zero List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: av1474@comtv.ru, Aurelien Jarno The TCG optimizer does great work when inserting constants, being able to fold the open-coded deposit expansion to just an AND or an OR. Avoid a bit the regression caused by having the deposit opcode by expanding deposit of zero as an AND. Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 9583cf9..772f4ac 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1928,12 +1928,22 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_deposit_i32: - tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], - 32 - args[3] - args[4], 31 - args[3]); + if (const_args[2]) { + uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; + tcg_out_andi32(s, args[0], args[0], ~mask); + } else { + tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], + 32 - args[3] - args[4], 31 - args[3]); + } break; case INDEX_op_deposit_i64: - tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], - 64 - args[3] - args[4]); + if (const_args[2]) { + uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; + tcg_out_andi64(s, args[0], args[0], ~mask); + } else { + tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], + 64 - args[3] - args[4]); + } break; case INDEX_op_movcond_i32: @@ -2136,8 +2146,8 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_bswap32_i64, { "r", "r" } }, { INDEX_op_bswap64_i64, { "r", "r" } }, - { INDEX_op_deposit_i32, { "r", "0", "r" } }, - { INDEX_op_deposit_i64, { "r", "0", "r" } }, + { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, + { INDEX_op_deposit_i64, { "r", "0", "rZ" } }, { INDEX_op_add2_i64, { "r", "r", "r", "rI", "r", "rZM" } }, { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } }, -- 1.8.1.4