From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:38033) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UOAk6-0006KG-VB for qemu-devel@nongnu.org; Fri, 05 Apr 2013 13:48:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UOAep-0005JU-DE for qemu-devel@nongnu.org; Fri, 05 Apr 2013 13:42:48 -0400 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:33552 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UOAep-0005Er-48 for qemu-devel@nongnu.org; Fri, 05 Apr 2013 13:42:35 -0400 From: Peter Maydell Date: Fri, 5 Apr 2013 18:13:18 +0100 Message-Id: <1365181999-15387-14-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1365181999-15387-1-git-send-email-peter.maydell@linaro.org> References: <1365181999-15387-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 13/14] cadence_uart: Flush queued characters on reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori , Blue Swirl Cc: qemu-devel@nongnu.org, Paul Brook From: Peter Crosthwaite Reset can be used to empty the rx-fifo. As the fifo full condition is used to return false from can_receive, queued rx data should be flushed on reset accordingly. Cc: Wendy Liang Cc: Jason Wu Signed-off-by: Peter Crosthwaite Reported-by: Jason Wu Message-id: 494c1e005e225c915d295ddfd75d992ad2dabc3c.1364964526.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/cadence_uart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c index 5426f10..421ec99 100644 --- a/hw/cadence_uart.c +++ b/hw/cadence_uart.c @@ -157,6 +157,7 @@ static void uart_rx_reset(UartState *s) { s->rx_wpos = 0; s->rx_count = 0; + qemu_chr_accept_input(s->chr); s->r[R_SR] |= UART_SR_INTR_REMPTY; s->r[R_SR] &= ~UART_SR_INTR_RFUL; -- 1.7.9.5