qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: av1474@comtv.ru, aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v5 10/33] tcg-ppc64: Rearrange integer constant constraints
Date: Mon, 15 Apr 2013 20:40:49 +0200	[thread overview]
Message-ID: <1366051272-12979-11-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1366051272-12979-1-git-send-email-rth@twiddle.net>

We'll need a zero, and Z makes more sense for that.  Make sure we
have a full compliment of signed and unsigned 16 and 32-bit tests.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ppc64/tcg-target.c | 43 +++++++++++++++++++++++++++++++++----------
 1 file changed, 33 insertions(+), 10 deletions(-)

diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index c6ff75b..6ba09ab 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -22,7 +22,11 @@
  * THE SOFTWARE.
  */
 
-#define TCG_CT_CONST_U32 0x100
+#define TCG_CT_CONST_S16  0x100
+#define TCG_CT_CONST_U16  0x200
+#define TCG_CT_CONST_S32  0x400
+#define TCG_CT_CONST_U32  0x800
+#define TCG_CT_CONST_ZERO 0x1000
 
 static uint8_t *tb_ret_addr;
 
@@ -242,9 +246,21 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
         tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6);
 #endif
         break;
-    case 'Z':
+    case 'I':
+        ct->ct |= TCG_CT_CONST_S16;
+        break;
+    case 'J':
+        ct->ct |= TCG_CT_CONST_U16;
+        break;
+    case 'T':
+        ct->ct |= TCG_CT_CONST_S32;
+        break;
+    case 'U':
         ct->ct |= TCG_CT_CONST_U32;
         break;
+    case 'Z':
+        ct->ct |= TCG_CT_CONST_ZERO;
+        break;
     default:
         return -1;
     }
@@ -257,13 +273,20 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
 static int tcg_target_const_match (tcg_target_long val,
                                    const TCGArgConstraint *arg_ct)
 {
-    int ct;
-
-    ct = arg_ct->ct;
-    if (ct & TCG_CT_CONST)
+    int ct = arg_ct->ct;
+    if (ct & TCG_CT_CONST) {
+        return 1;
+    } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
+        return 1;
+    } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
         return 1;
-    else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val))
+    } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
         return 1;
+    } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
+        return 1;
+    } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+        return 1;
+    }
     return 0;
 }
 
@@ -1613,9 +1636,9 @@ static const TCGTargetOpDef ppc_op_defs[] = {
 
     { INDEX_op_add_i64, { "r", "r", "ri" } },
     { INDEX_op_sub_i64, { "r", "r", "ri" } },
-    { INDEX_op_and_i64, { "r", "r", "rZ" } },
-    { INDEX_op_or_i64, { "r", "r", "rZ" } },
-    { INDEX_op_xor_i64, { "r", "r", "rZ" } },
+    { INDEX_op_and_i64, { "r", "r", "rU" } },
+    { INDEX_op_or_i64, { "r", "r", "rU" } },
+    { INDEX_op_xor_i64, { "r", "r", "rU" } },
 
     { INDEX_op_shl_i64, { "r", "r", "ri" } },
     { INDEX_op_shr_i64, { "r", "r", "ri" } },
-- 
1.8.1.4

  parent reply	other threads:[~2013-04-15 18:43 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-04-15 18:40 [Qemu-devel] [PATCH v5 00/33] Modernize tcg/ppc64 Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 01/33] disas: Disassemble all ppc insns for the host Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 02/33] tcg-ppc64: Use TCGReg everywhere Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 03/33] tcg-ppc64: Introduce and use tcg_out_rlw Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 04/33] tcg-ppc64: Introduce and use tcg_out_ext32u Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 05/33] tcg-ppc64: Introduce and use tcg_out_shli64 Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 06/33] tcg-ppc64: Introduce and use tcg_out_shri64 Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 07/33] tcg-ppc64: Introduce and use TAI and SAI Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 08/33] tcg-ppc64: Fix setcond_i32 Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 09/33] tcg-ppc64: Cleanup tcg_out_movi Richard Henderson
2013-04-15 18:40 ` Richard Henderson [this message]
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 11/33] tcg-ppc64: Improve constant add and sub ops Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 12/33] tcg-ppc64: Allow constant first argument to sub Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 13/33] tcg-ppc64: Tidy or and xor patterns Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 14/33] tcg-ppc64: Improve and_i32 with constant Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 15/33] tcg-ppc64: Improve and_i64 " Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 16/33] tcg-ppc64: Use automatic implementation of ext32u_i64 Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 17/33] tcg-ppc64: Streamline qemu_ld/st insn selection Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 18/33] tcg-ppc64: Implement rotates Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 19/33] tcg-ppc64: Implement bswap16 and bswap32 Richard Henderson
2013-04-15 20:04   ` Aurelien Jarno
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 20/33] tcg-ppc64: Implement bswap64 Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 21/33] tcg-ppc64: Implement compound logicals Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 22/33] tcg-ppc64: Handle constant inputs for some " Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 23/33] tcg-ppc64: Implement deposit Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 24/33] tcg-ppc64: Use I constraint for mul Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 25/33] tcg-ppc64: Use TCGType throughout compares Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 26/33] tcg-ppc64: Cleanup i32 constants to tcg_out_cmp Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 27/33] tcg-ppc64: Use MFOCRF instead of MFCR Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 28/33] tcg-ppc64: Use ISEL for setcond Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 29/33] tcg-ppc64: Implement movcond Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 30/33] tcg-ppc64: Use getauxval for ISA detection Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 31/33] tcg-ppc64: Implement add2/sub2_i64 Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 32/33] tcg-ppc64: Implement mulu2/muls2_i64 Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 33/33] tcg-ppc64: Handle deposit of zero Richard Henderson
2013-04-15 20:52 ` [Qemu-devel] [PATCH v5 00/33] Modernize tcg/ppc64 Aurelien Jarno

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1366051272-12979-11-git-send-email-rth@twiddle.net \
    --to=rth@twiddle.net \
    --cc=aurelien@aurel32.net \
    --cc=av1474@comtv.ru \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).