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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: av1474@comtv.ru, aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v5 25/33] tcg-ppc64: Use TCGType throughout compares
Date: Mon, 15 Apr 2013 20:41:04 +0200	[thread overview]
Message-ID: <1366051272-12979-26-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1366051272-12979-1-git-send-email-rth@twiddle.net>

The optimization/bug being fixed is that tcg_out_cmp was not applying the
right type to loading a constant, in the case it can't be implemented
directly.  Rather than recomputing the TCGType enum from the arch64 bool,
pass around the original TCGType throughout.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ppc64/tcg-target.c | 38 +++++++++++++++++++-------------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 56e70db..84c7575 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -1053,8 +1053,8 @@ static void tcg_out_st (TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
         tcg_out_ldsta (s, arg, arg1, arg2, STD, STDX);
 }
 
-static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
-                         int const_arg2, int cr, int arch64)
+static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
+                        int const_arg2, int cr, TCGType type)
 {
     int imm;
     uint32_t op;
@@ -1111,19 +1111,17 @@ static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
     default:
         tcg_abort ();
     }
-    op |= BF (cr) | (arch64 << 21);
+    op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
 
-    if (imm)
-        tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
-    else {
+    if (imm) {
+        tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
+    } else {
         if (const_arg2) {
-            tcg_out_movi (s, TCG_TYPE_I64, 0, arg2);
-            tcg_out32 (s, op | RA (arg1) | RB (0));
+            tcg_out_movi(s, type, 0, arg2);
+            arg2 = 0;
         }
-        else
-            tcg_out32 (s, op | RA (arg1) | RB (arg2));
+        tcg_out32(s, op | RA(arg1) | RB(arg2));
     }
-
 }
 
 static void tcg_out_setcond (TCGContext *s, TCGType type, TCGCond cond,
@@ -1223,7 +1221,7 @@ static void tcg_out_setcond (TCGContext *s, TCGType type, TCGCond cond,
         sh = 31;
         crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
     crtest:
-        tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, type == TCG_TYPE_I64);
+        tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, type);
         if (crop) tcg_out32 (s, crop);
         tcg_out32 (s, MFCR | RT (0));
         tcg_out_rlw(s, RLWINM, arg0, 0, sh, 31, 31);
@@ -1249,12 +1247,12 @@ static void tcg_out_bc (TCGContext *s, int bc, int label_index)
     }
 }
 
-static void tcg_out_brcond (TCGContext *s, TCGCond cond,
-                            TCGArg arg1, TCGArg arg2, int const_arg2,
-                            int label_index, int arch64)
+static void tcg_out_brcond(TCGContext *s, TCGCond cond,
+                           TCGArg arg1, TCGArg arg2, int const_arg2,
+                           int label_index, TCGType type)
 {
-    tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, arch64);
-    tcg_out_bc (s, tcg_to_bc[cond], label_index);
+    tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
+    tcg_out_bc(s, tcg_to_bc[cond], label_index);
 }
 
 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
@@ -1538,11 +1536,13 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
         break;
 
     case INDEX_op_brcond_i32:
-        tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 0);
+        tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
+                       args[3], TCG_TYPE_I32);
         break;
 
     case INDEX_op_brcond_i64:
-        tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 1);
+        tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
+                       args[3], TCG_TYPE_I64);
         break;
 
     case INDEX_op_neg_i32:
-- 
1.8.1.4

  parent reply	other threads:[~2013-04-15 18:45 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-04-15 18:40 [Qemu-devel] [PATCH v5 00/33] Modernize tcg/ppc64 Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 01/33] disas: Disassemble all ppc insns for the host Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 02/33] tcg-ppc64: Use TCGReg everywhere Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 03/33] tcg-ppc64: Introduce and use tcg_out_rlw Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 04/33] tcg-ppc64: Introduce and use tcg_out_ext32u Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 05/33] tcg-ppc64: Introduce and use tcg_out_shli64 Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 06/33] tcg-ppc64: Introduce and use tcg_out_shri64 Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 07/33] tcg-ppc64: Introduce and use TAI and SAI Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 08/33] tcg-ppc64: Fix setcond_i32 Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 09/33] tcg-ppc64: Cleanup tcg_out_movi Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 10/33] tcg-ppc64: Rearrange integer constant constraints Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 11/33] tcg-ppc64: Improve constant add and sub ops Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 12/33] tcg-ppc64: Allow constant first argument to sub Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 13/33] tcg-ppc64: Tidy or and xor patterns Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 14/33] tcg-ppc64: Improve and_i32 with constant Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 15/33] tcg-ppc64: Improve and_i64 " Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 16/33] tcg-ppc64: Use automatic implementation of ext32u_i64 Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 17/33] tcg-ppc64: Streamline qemu_ld/st insn selection Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 18/33] tcg-ppc64: Implement rotates Richard Henderson
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 19/33] tcg-ppc64: Implement bswap16 and bswap32 Richard Henderson
2013-04-15 20:04   ` Aurelien Jarno
2013-04-15 18:40 ` [Qemu-devel] [PATCH v5 20/33] tcg-ppc64: Implement bswap64 Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 21/33] tcg-ppc64: Implement compound logicals Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 22/33] tcg-ppc64: Handle constant inputs for some " Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 23/33] tcg-ppc64: Implement deposit Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 24/33] tcg-ppc64: Use I constraint for mul Richard Henderson
2013-04-15 18:41 ` Richard Henderson [this message]
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 26/33] tcg-ppc64: Cleanup i32 constants to tcg_out_cmp Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 27/33] tcg-ppc64: Use MFOCRF instead of MFCR Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 28/33] tcg-ppc64: Use ISEL for setcond Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 29/33] tcg-ppc64: Implement movcond Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 30/33] tcg-ppc64: Use getauxval for ISA detection Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 31/33] tcg-ppc64: Implement add2/sub2_i64 Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 32/33] tcg-ppc64: Implement mulu2/muls2_i64 Richard Henderson
2013-04-15 18:41 ` [Qemu-devel] [PATCH v5 33/33] tcg-ppc64: Handle deposit of zero Richard Henderson
2013-04-15 20:52 ` [Qemu-devel] [PATCH v5 00/33] Modernize tcg/ppc64 Aurelien Jarno

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