From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:43207) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoP7-0001Qm-Hx for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:45:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1URoP2-0003W5-RK for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:45:25 -0400 Received: from mail-qc0-x22c.google.com ([2607:f8b0:400d:c01::22c]:46181) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URoP2-0003W1-Nh for qemu-devel@nongnu.org; Mon, 15 Apr 2013 14:45:20 -0400 Received: by mail-qc0-f172.google.com with SMTP id b25so2359345qca.31 for ; Mon, 15 Apr 2013 11:45:20 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 15 Apr 2013 20:41:06 +0200 Message-Id: <1366051272-12979-28-git-send-email-rth@twiddle.net> In-Reply-To: <1366051272-12979-1-git-send-email-rth@twiddle.net> References: <1366051272-12979-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v5 27/33] tcg-ppc64: Use MFOCRF instead of MFCR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: av1474@comtv.ru, aurelien@aurel32.net It takes half the cycles to read one CR register instead of all 8. This is a backward compatible addition to the ISA, so chips prior to Power 2.00 spec will simply continue to read the entire CR register. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 70cbb86..c7800b0 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -382,6 +382,7 @@ static int tcg_target_const_match (tcg_target_long val, #define SRAWI XO31(824) #define NEG XO31(104) #define MFCR XO31( 19) +#define MFOCRF (MFCR | (1u << 20)) #define NOR XO31(124) #define CNTLZW XO31( 26) #define CNTLZD XO31( 58) @@ -430,6 +431,7 @@ static int tcg_target_const_match (tcg_target_long val, #define ME(e) ((e)<<1) #define BO(o) ((o)<<21) #define MB64(b) ((b)<<5) +#define FXM(b) (1 << (19 - (b))) #define LK 1 @@ -1226,10 +1228,12 @@ static void tcg_out_setcond (TCGContext *s, TCGType type, TCGCond cond, sh = 31; crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT); crtest: - tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, type); - if (crop) tcg_out32 (s, crop); - tcg_out32 (s, MFCR | RT (0)); - tcg_out_rlw(s, RLWINM, arg0, 0, sh, 31, 31); + tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); + if (crop) { + tcg_out32(s, crop); + } + tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); + tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31); break; default: -- 1.8.1.4