[Qemu-devel] [PULL 0/4] target-arm queue

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

Hi; this is a pullreq for the current target-arm queue. Some
minor tweaks and the patch which handles get/put_user() failure
in the semihosting code. Please pull.

thanks
-- PMM

The following changes since commit a8170e5e97ad17ca169c64ba87ae2f53850dab4c:

  Rename target_phys_addr_t to hwaddr (2012-10-23 08:58:25 -0500)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

for you to fetch changes up to 8b279a60dc3ca53923701dfec6e54bea9d13cfb7:

  target-arm: Remove out of date FIXME regarding saturating arithmetic (2012-10-24 13:33:29 +0100)

----------------------------------------------------------------
Peter Maydell (4):
      arm-semi.c: Handle get/put_user() failure accessing arguments
      target-arm: Use TCG operation for Neon 64 bit negation
      target-arm: Implement abs_i32 inline rather than as a helper
      target-arm: Remove out of date FIXME regarding saturating arithmetic

 target-arm/arm-semi.c    |  167 +++++++++++++++++++++++++++++-----------------
 target-arm/helper.c      |    5 --
 target-arm/helper.h      |    2 -
 target-arm/neon_helper.c |    6 --
 target-arm/op_helper.c   |    2 -
 target-arm/translate.c   |   15 ++++-
 6 files changed, 118 insertions(+), 79 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Blue Swirl]

On Wed, Oct 24, 2012 at 1:02 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> Hi; this is a pullreq for the current target-arm queue. Some
> minor tweaks and the patch which handles get/put_user() failure
> in the semihosting code. Please pull.

Thanks, pulled.

>
> thanks
> -- PMM
>
> The following changes since commit a8170e5e97ad17ca169c64ba87ae2f53850dab4c:
>
>   Rename target_phys_addr_t to hwaddr (2012-10-23 08:58:25 -0500)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
>
> for you to fetch changes up to 8b279a60dc3ca53923701dfec6e54bea9d13cfb7:
>
>   target-arm: Remove out of date FIXME regarding saturating arithmetic (2012-10-24 13:33:29 +0100)
>
> ----------------------------------------------------------------
> Peter Maydell (4):
>       arm-semi.c: Handle get/put_user() failure accessing arguments
>       target-arm: Use TCG operation for Neon 64 bit negation
>       target-arm: Implement abs_i32 inline rather than as a helper
>       target-arm: Remove out of date FIXME regarding saturating arithmetic
>
>  target-arm/arm-semi.c    |  167 +++++++++++++++++++++++++++++-----------------
>  target-arm/helper.c      |    5 --
>  target-arm/helper.h      |    2 -
>  target-arm/neon_helper.c |    6 --
>  target-arm/op_helper.c   |    2 -
>  target-arm/translate.c   |   15 ++++-
>  6 files changed, 118 insertions(+), 79 deletions(-)

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

target-arm pullreq, containing a fix for a dumb SRS bug I
introduced, and the update to migration to use vmstate
(both of which have been on the list since before freeze).
Please pull.

thanks
-- PMM

The following changes since commit 09dada400328d75daf79e3eca1e48e024fec148d:

  configure: remove duplicate test (2013-04-18 14:12:31 +0200)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.next

for you to fetch changes up to e91f229a253f489f6d12b946ad7bdcdc158c5b67:

  target-arm: Correctly restore FPSCR (2013-04-19 12:24:19 +0100)

----------------------------------------------------------------
Juan Quintela (1):
      target-arm: port ARM CPU save/load to use VMState

Peter Chubb (1):
      target-arm: Reinsert missing return statement in ARM mode SRS decode

Peter Maydell (2):
      target-arm: Add some missing CPU state fields to VMState
      target-arm: Correctly restore FPSCR

 target-arm/cpu-qom.h   |    4 +
 target-arm/cpu.c       |    1 +
 target-arm/cpu.h       |    2 -
 target-arm/machine.c   |  430 ++++++++++++++++++++++++------------------------
 target-arm/translate.c |    1 +
 5 files changed, 222 insertions(+), 216 deletions(-)

[Qemu-devel] [PATCH 1/4] target-arm: Reinsert missing return statement in ARM mode SRS decode

[Peter Maydell]

From: Peter Chubb <peter.chubb@nicta.com.au>

Since patch
   81465888c5306cd94abb9847e560796fd13d3c2f
   target-arm: factor out handling of SRS instruction
the ARM mode SRS instruction has not worked in QEMU.

The problem is a missing return directive that was removed in the
refactoring, so after decoding the instruction, qemu would fall through
to generate an UNDEF exception for an illegal instruction.

Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 35a21be..a1b7b8c 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6762,6 +6762,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
             }
             ARCH(6);
             gen_srs(s, (insn & 0x1f), (insn >> 23) & 3, insn & (1 << 21));
+            return;
         } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
             /* rfe */
             int32_t offset;
-- 
1.7.9.5

[Qemu-devel] [PATCH 2/4] target-arm: port ARM CPU save/load to use VMState

[Peter Maydell]

From: Juan Quintela <quintela@redhat.com>

Port the ARM CPU save/load code to use VMState. Some state is
saved in a slightly different order to simplify things -- for
example arrays are saved one after the other rather than 'striped',
and we always save all 32 VFP registers even if the CPU happens
to only have 16.

Use one subsection for each feature.  This means that we don't need to
bump the version field each time that a new feature gets introduced.

Signed-off-by: Juan Quintela <quintela@redhat.com>
[PMM: fixed conflicts, updated to use cpu_class_set_vmsd(),  updated
 with new/removed fields since original patch, changed to use custom
 VMStateInfo for cpsr rather than presave/postload hooks, corrected
 subsection names so vmload doesn't fail]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu-qom.h |    4 +
 target-arm/cpu.c     |    1 +
 target-arm/cpu.h     |    2 -
 target-arm/machine.c |  387 +++++++++++++++++++++++---------------------------
 4 files changed, 179 insertions(+), 215 deletions(-)

diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 2589550..12fcefe 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -111,6 +111,10 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
 
 #define ENV_OFFSET offsetof(ARMCPU, env)
 
+#ifndef CONFIG_USER_ONLY
+extern const struct VMStateDescription vmstate_arm_cpu;
+#endif
+
 void register_cp_regs_for_features(ARMCPU *cpu);
 
 void arm_cpu_do_interrupt(CPUState *cpu);
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index a1e9093..496a59f 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -814,6 +814,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
 
     cc->class_by_name = arm_cpu_class_by_name;
     cc->do_interrupt = arm_cpu_do_interrupt;
+    cpu_class_set_vmsd(cc, &vmstate_arm_cpu);
 }
 
 static void cpu_register(const ARMCPUInfo *info)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 2b97221..5438444 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -640,8 +640,6 @@ static inline CPUARMState *cpu_init(const char *cpu_model)
 #define cpu_signal_handler cpu_arm_signal_handler
 #define cpu_list arm_cpu_list
 
-#define CPU_SAVE_VERSION 9
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _user
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 68dca7f..3c41f06 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -1,237 +1,198 @@
 #include "hw/hw.h"
 #include "hw/boards.h"
 
-void cpu_save(QEMUFile *f, void *opaque)
+static bool vfp_needed(void *opaque)
 {
-    int i;
-    CPUARMState *env = (CPUARMState *)opaque;
+    ARMCPU *cpu = opaque;
+    CPUARMState *env = &cpu->env;
 
-    for (i = 0; i < 16; i++) {
-        qemu_put_be32(f, env->regs[i]);
-    }
-    qemu_put_be32(f, cpsr_read(env));
-    qemu_put_be32(f, env->spsr);
-    for (i = 0; i < 6; i++) {
-        qemu_put_be32(f, env->banked_spsr[i]);
-        qemu_put_be32(f, env->banked_r13[i]);
-        qemu_put_be32(f, env->banked_r14[i]);
-    }
-    for (i = 0; i < 5; i++) {
-        qemu_put_be32(f, env->usr_regs[i]);
-        qemu_put_be32(f, env->fiq_regs[i]);
-    }
-    qemu_put_be32(f, env->cp15.c0_cpuid);
-    qemu_put_be32(f, env->cp15.c0_cssel);
-    qemu_put_be32(f, env->cp15.c1_sys);
-    qemu_put_be32(f, env->cp15.c1_coproc);
-    qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
-    qemu_put_be32(f, env->cp15.c1_scr);
-    qemu_put_be32(f, env->cp15.c2_base0);
-    qemu_put_be32(f, env->cp15.c2_base0_hi);
-    qemu_put_be32(f, env->cp15.c2_base1);
-    qemu_put_be32(f, env->cp15.c2_base1_hi);
-    qemu_put_be32(f, env->cp15.c2_control);
-    qemu_put_be32(f, env->cp15.c2_mask);
-    qemu_put_be32(f, env->cp15.c2_base_mask);
-    qemu_put_be32(f, env->cp15.c2_data);
-    qemu_put_be32(f, env->cp15.c2_insn);
-    qemu_put_be32(f, env->cp15.c3);
-    qemu_put_be32(f, env->cp15.c5_insn);
-    qemu_put_be32(f, env->cp15.c5_data);
-    for (i = 0; i < 8; i++) {
-        qemu_put_be32(f, env->cp15.c6_region[i]);
-    }
-    qemu_put_be32(f, env->cp15.c6_insn);
-    qemu_put_be32(f, env->cp15.c6_data);
-    qemu_put_be32(f, env->cp15.c7_par);
-    qemu_put_be32(f, env->cp15.c7_par_hi);
-    qemu_put_be32(f, env->cp15.c9_insn);
-    qemu_put_be32(f, env->cp15.c9_data);
-    qemu_put_be32(f, env->cp15.c9_pmcr);
-    qemu_put_be32(f, env->cp15.c9_pmcnten);
-    qemu_put_be32(f, env->cp15.c9_pmovsr);
-    qemu_put_be32(f, env->cp15.c9_pmxevtyper);
-    qemu_put_be32(f, env->cp15.c9_pmuserenr);
-    qemu_put_be32(f, env->cp15.c9_pminten);
-    qemu_put_be32(f, env->cp15.c13_fcse);
-    qemu_put_be32(f, env->cp15.c13_context);
-    qemu_put_be32(f, env->cp15.c13_tls1);
-    qemu_put_be32(f, env->cp15.c13_tls2);
-    qemu_put_be32(f, env->cp15.c13_tls3);
-    qemu_put_be32(f, env->cp15.c15_cpar);
-    qemu_put_be32(f, env->cp15.c15_power_control);
-    qemu_put_be32(f, env->cp15.c15_diagnostic);
-    qemu_put_be32(f, env->cp15.c15_power_diagnostic);
-
-    qemu_put_be64(f, env->features);
-
-    if (arm_feature(env, ARM_FEATURE_VFP)) {
-        for (i = 0;  i < 16; i++) {
-            CPU_DoubleU u;
-            u.d = env->vfp.regs[i];
-            qemu_put_be32(f, u.l.upper);
-            qemu_put_be32(f, u.l.lower);
-        }
-        for (i = 0; i < 16; i++) {
-            qemu_put_be32(f, env->vfp.xregs[i]);
-        }
+    return arm_feature(env, ARM_FEATURE_VFP);
+}
 
+static const VMStateDescription vmstate_vfp = {
+    .name = "cpu/vfp",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 32),
+        VMSTATE_UINT32_ARRAY(env.vfp.xregs, ARMCPU, 16),
         /* TODO: Should use proper FPSCR access functions.  */
-        qemu_put_be32(f, env->vfp.vec_len);
-        qemu_put_be32(f, env->vfp.vec_stride);
-
-        if (arm_feature(env, ARM_FEATURE_VFP3)) {
-            for (i = 16;  i < 32; i++) {
-                CPU_DoubleU u;
-                u.d = env->vfp.regs[i];
-                qemu_put_be32(f, u.l.upper);
-                qemu_put_be32(f, u.l.lower);
-            }
-        }
+        VMSTATE_INT32(env.vfp.vec_len, ARMCPU),
+        VMSTATE_INT32(env.vfp.vec_stride, ARMCPU),
+        VMSTATE_END_OF_LIST()
     }
+};
 
-    if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
-        for (i = 0; i < 16; i++) {
-            qemu_put_be64(f, env->iwmmxt.regs[i]);
-        }
-        for (i = 0; i < 16; i++) {
-            qemu_put_be32(f, env->iwmmxt.cregs[i]);
-        }
-    }
+static bool iwmmxt_needed(void *opaque)
+{
+    ARMCPU *cpu = opaque;
+    CPUARMState *env = &cpu->env;
 
-    if (arm_feature(env, ARM_FEATURE_M)) {
-        qemu_put_be32(f, env->v7m.other_sp);
-        qemu_put_be32(f, env->v7m.vecbase);
-        qemu_put_be32(f, env->v7m.basepri);
-        qemu_put_be32(f, env->v7m.control);
-        qemu_put_be32(f, env->v7m.current_sp);
-        qemu_put_be32(f, env->v7m.exception);
-    }
+    return arm_feature(env, ARM_FEATURE_IWMMXT);
+}
 
-    if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
-        qemu_put_be32(f, env->teecr);
-        qemu_put_be32(f, env->teehbr);
+static const VMStateDescription vmstate_iwmmxt = {
+    .name = "cpu/iwmmxt",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
+        VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
+        VMSTATE_END_OF_LIST()
     }
+};
+
+static bool m_needed(void *opaque)
+{
+    ARMCPU *cpu = opaque;
+    CPUARMState *env = &cpu->env;
+
+    return arm_feature(env, ARM_FEATURE_M);
 }
 
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
+const VMStateDescription vmstate_m = {
+    .name = "cpu/m",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
+        VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
+        VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
+        VMSTATE_UINT32(env.v7m.control, ARMCPU),
+        VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
+        VMSTATE_INT32(env.v7m.exception, ARMCPU),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static bool thumb2ee_needed(void *opaque)
 {
-    CPUARMState *env = (CPUARMState *)opaque;
-    int i;
-    uint32_t val;
+    ARMCPU *cpu = opaque;
+    CPUARMState *env = &cpu->env;
 
-    if (version_id != CPU_SAVE_VERSION)
-        return -EINVAL;
+    return arm_feature(env, ARM_FEATURE_THUMB2EE);
+}
 
-    for (i = 0; i < 16; i++) {
-        env->regs[i] = qemu_get_be32(f);
+static const VMStateDescription vmstate_thumb2ee = {
+    .name = "cpu/thumb2ee",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(env.teecr, ARMCPU),
+        VMSTATE_UINT32(env.teehbr, ARMCPU),
+        VMSTATE_END_OF_LIST()
     }
-    val = qemu_get_be32(f);
-    /* Avoid mode switch when restoring CPSR.  */
+};
+
+static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
+{
+    ARMCPU *cpu = opaque;
+    CPUARMState *env = &cpu->env;
+    uint32_t val = qemu_get_be32(f);
+
+    /* Avoid mode switch when restoring CPSR */
     env->uncached_cpsr = val & CPSR_M;
     cpsr_write(env, val, 0xffffffff);
-    env->spsr = qemu_get_be32(f);
-    for (i = 0; i < 6; i++) {
-        env->banked_spsr[i] = qemu_get_be32(f);
-        env->banked_r13[i] = qemu_get_be32(f);
-        env->banked_r14[i] = qemu_get_be32(f);
-    }
-    for (i = 0; i < 5; i++) {
-        env->usr_regs[i] = qemu_get_be32(f);
-        env->fiq_regs[i] = qemu_get_be32(f);
-    }
-    env->cp15.c0_cpuid = qemu_get_be32(f);
-    env->cp15.c0_cssel = qemu_get_be32(f);
-    env->cp15.c1_sys = qemu_get_be32(f);
-    env->cp15.c1_coproc = qemu_get_be32(f);
-    env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
-    env->cp15.c1_scr = qemu_get_be32(f);
-    env->cp15.c2_base0 = qemu_get_be32(f);
-    env->cp15.c2_base0_hi = qemu_get_be32(f);
-    env->cp15.c2_base1 = qemu_get_be32(f);
-    env->cp15.c2_base1_hi = qemu_get_be32(f);
-    env->cp15.c2_control = qemu_get_be32(f);
-    env->cp15.c2_mask = qemu_get_be32(f);
-    env->cp15.c2_base_mask = qemu_get_be32(f);
-    env->cp15.c2_data = qemu_get_be32(f);
-    env->cp15.c2_insn = qemu_get_be32(f);
-    env->cp15.c3 = qemu_get_be32(f);
-    env->cp15.c5_insn = qemu_get_be32(f);
-    env->cp15.c5_data = qemu_get_be32(f);
-    for (i = 0; i < 8; i++) {
-        env->cp15.c6_region[i] = qemu_get_be32(f);
-    }
-    env->cp15.c6_insn = qemu_get_be32(f);
-    env->cp15.c6_data = qemu_get_be32(f);
-    env->cp15.c7_par = qemu_get_be32(f);
-    env->cp15.c7_par_hi = qemu_get_be32(f);
-    env->cp15.c9_insn = qemu_get_be32(f);
-    env->cp15.c9_data = qemu_get_be32(f);
-    env->cp15.c9_pmcr = qemu_get_be32(f);
-    env->cp15.c9_pmcnten = qemu_get_be32(f);
-    env->cp15.c9_pmovsr = qemu_get_be32(f);
-    env->cp15.c9_pmxevtyper = qemu_get_be32(f);
-    env->cp15.c9_pmuserenr = qemu_get_be32(f);
-    env->cp15.c9_pminten = qemu_get_be32(f);
-    env->cp15.c13_fcse = qemu_get_be32(f);
-    env->cp15.c13_context = qemu_get_be32(f);
-    env->cp15.c13_tls1 = qemu_get_be32(f);
-    env->cp15.c13_tls2 = qemu_get_be32(f);
-    env->cp15.c13_tls3 = qemu_get_be32(f);
-    env->cp15.c15_cpar = qemu_get_be32(f);
-    env->cp15.c15_power_control = qemu_get_be32(f);
-    env->cp15.c15_diagnostic = qemu_get_be32(f);
-    env->cp15.c15_power_diagnostic = qemu_get_be32(f);
-
-    env->features = qemu_get_be64(f);
-
-    if (arm_feature(env, ARM_FEATURE_VFP)) {
-        for (i = 0;  i < 16; i++) {
-            CPU_DoubleU u;
-            u.l.upper = qemu_get_be32(f);
-            u.l.lower = qemu_get_be32(f);
-            env->vfp.regs[i] = u.d;
-        }
-        for (i = 0; i < 16; i++) {
-            env->vfp.xregs[i] = qemu_get_be32(f);
-        }
-
-        /* TODO: Should use proper FPSCR access functions.  */
-        env->vfp.vec_len = qemu_get_be32(f);
-        env->vfp.vec_stride = qemu_get_be32(f);
-
-        if (arm_feature(env, ARM_FEATURE_VFP3)) {
-            for (i = 16;  i < 32; i++) {
-                CPU_DoubleU u;
-                u.l.upper = qemu_get_be32(f);
-                u.l.lower = qemu_get_be32(f);
-                env->vfp.regs[i] = u.d;
-            }
-        }
-    }
+    return 0;
+}
 
-    if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
-        for (i = 0; i < 16; i++) {
-            env->iwmmxt.regs[i] = qemu_get_be64(f);
-        }
-        for (i = 0; i < 16; i++) {
-            env->iwmmxt.cregs[i] = qemu_get_be32(f);
-        }
-    }
+static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
+{
+    ARMCPU *cpu = opaque;
+    CPUARMState *env = &cpu->env;
 
-    if (arm_feature(env, ARM_FEATURE_M)) {
-        env->v7m.other_sp = qemu_get_be32(f);
-        env->v7m.vecbase = qemu_get_be32(f);
-        env->v7m.basepri = qemu_get_be32(f);
-        env->v7m.control = qemu_get_be32(f);
-        env->v7m.current_sp = qemu_get_be32(f);
-        env->v7m.exception = qemu_get_be32(f);
-    }
+    qemu_put_be32(f, cpsr_read(env));
+}
 
-    if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
-        env->teecr = qemu_get_be32(f);
-        env->teehbr = qemu_get_be32(f);
+static const VMStateInfo vmstate_cpsr = {
+    .name = "cpsr",
+    .get = get_cpsr,
+    .put = put_cpsr,
+};
+
+const VMStateDescription vmstate_arm_cpu = {
+    .name = "cpu",
+    .version_id = 10,
+    .minimum_version_id = 10,
+    .minimum_version_id_old = 10,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
+        {
+            .name = "cpsr",
+            .version_id = 0,
+            .size = sizeof(uint32_t),
+            .info = &vmstate_cpsr,
+            .flags = VMS_SINGLE,
+            .offset = 0,
+        },
+        VMSTATE_UINT32(env.spsr, ARMCPU),
+        VMSTATE_UINT32_ARRAY(env.banked_spsr, ARMCPU, 6),
+        VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
+        VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
+        VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
+        VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
+        VMSTATE_UINT32(env.cp15.c0_cpuid, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c0_cssel, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c1_sys, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c1_coproc, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c1_xscaleauxcr, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c1_scr, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c2_base0, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c2_base0_hi, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c2_base1, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c2_base1_hi, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c2_control, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c2_mask, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c2_base_mask, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c2_data, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c2_insn, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c3, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c5_insn, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c5_data, ARMCPU),
+        VMSTATE_UINT32_ARRAY(env.cp15.c6_region, ARMCPU, 8),
+        VMSTATE_UINT32(env.cp15.c6_insn, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c6_data, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c7_par, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c7_par_hi, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c9_insn, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c9_data, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c9_pmcr, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c9_pmcnten, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c9_pmovsr, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c9_pmxevtyper, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c9_pmuserenr, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c9_pminten, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c13_fcse, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c13_context, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c13_tls1, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c13_tls2, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c13_tls3, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c15_cpar, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c15_power_control, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c15_diagnostic, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c15_power_diagnostic, ARMCPU),
+        VMSTATE_UINT64(env.features, ARMCPU),
+        VMSTATE_END_OF_LIST()
+    },
+    .subsections = (VMStateSubsection[]) {
+        {
+            .vmsd = &vmstate_vfp,
+            .needed = vfp_needed,
+        } , {
+            .vmsd = &vmstate_iwmmxt,
+            .needed = iwmmxt_needed,
+        } , {
+            .vmsd = &vmstate_m,
+            .needed = m_needed,
+        } , {
+            .vmsd = &vmstate_thumb2ee,
+            .needed = thumb2ee_needed,
+        } , {
+            /* empty */
+        }
     }
-
-    return 0;
-}
+};
-- 
1.7.9.5

[Qemu-devel] [PATCH 3/4] target-arm: Add some missing CPU state fields to VMState

[Peter Maydell]

A number of CPU state fields were accidentally omitted from
our migration state: some OMAP specific cp15 registers, and
some related to state for load/store exclusive insns. Add them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/machine.c |   13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/target-arm/machine.c b/target-arm/machine.c
index 3c41f06..2dd48d7 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -116,9 +116,9 @@ static const VMStateInfo vmstate_cpsr = {
 
 const VMStateDescription vmstate_arm_cpu = {
     .name = "cpu",
-    .version_id = 10,
-    .minimum_version_id = 10,
-    .minimum_version_id_old = 10,
+    .version_id = 11,
+    .minimum_version_id = 11,
+    .minimum_version_id_old = 11,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
         {
@@ -172,9 +172,16 @@ const VMStateDescription vmstate_arm_cpu = {
         VMSTATE_UINT32(env.cp15.c13_tls2, ARMCPU),
         VMSTATE_UINT32(env.cp15.c13_tls3, ARMCPU),
         VMSTATE_UINT32(env.cp15.c15_cpar, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c15_ticonfig, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c15_i_max, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c15_i_min, ARMCPU),
+        VMSTATE_UINT32(env.cp15.c15_threadid, ARMCPU),
         VMSTATE_UINT32(env.cp15.c15_power_control, ARMCPU),
         VMSTATE_UINT32(env.cp15.c15_diagnostic, ARMCPU),
         VMSTATE_UINT32(env.cp15.c15_power_diagnostic, ARMCPU),
+        VMSTATE_UINT32(env.exclusive_addr, ARMCPU),
+        VMSTATE_UINT32(env.exclusive_val, ARMCPU),
+        VMSTATE_UINT32(env.exclusive_high, ARMCPU),
         VMSTATE_UINT64(env.features, ARMCPU),
         VMSTATE_END_OF_LIST()
     },
-- 
1.7.9.5

[Qemu-devel] [PATCH 4/4] target-arm: Correctly restore FPSCR

[Peter Maydell]

Use the helper functions to save and restore the FPSCR, so that
we correctly propagate rounding mode and flushing behaviour into
the float_status fields. This also allows us to stop saving the
vector length/stride fields separately.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/machine.c |   48 +++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 41 insertions(+), 7 deletions(-)

diff --git a/target-arm/machine.c b/target-arm/machine.c
index 2dd48d7..4dd057c 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -9,17 +9,51 @@ static bool vfp_needed(void *opaque)
     return arm_feature(env, ARM_FEATURE_VFP);
 }
 
+static int get_fpscr(QEMUFile *f, void *opaque, size_t size)
+{
+    ARMCPU *cpu = opaque;
+    CPUARMState *env = &cpu->env;
+    uint32_t val = qemu_get_be32(f);
+
+    vfp_set_fpscr(env, val);
+    return 0;
+}
+
+static void put_fpscr(QEMUFile *f, void *opaque, size_t size)
+{
+    ARMCPU *cpu = opaque;
+    CPUARMState *env = &cpu->env;
+
+    qemu_put_be32(f, vfp_get_fpscr(env));
+}
+
+static const VMStateInfo vmstate_fpscr = {
+    .name = "fpscr",
+    .get = get_fpscr,
+    .put = put_fpscr,
+};
+
 static const VMStateDescription vmstate_vfp = {
     .name = "cpu/vfp",
-    .version_id = 1,
-    .minimum_version_id = 1,
-    .minimum_version_id_old = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
+    .minimum_version_id_old = 2,
     .fields = (VMStateField[]) {
         VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 32),
-        VMSTATE_UINT32_ARRAY(env.vfp.xregs, ARMCPU, 16),
-        /* TODO: Should use proper FPSCR access functions.  */
-        VMSTATE_INT32(env.vfp.vec_len, ARMCPU),
-        VMSTATE_INT32(env.vfp.vec_stride, ARMCPU),
+        /* The xregs array is a little awkward because element 1 (FPSCR)
+         * requires a specific accessor, so we have to split it up in
+         * the vmstate:
+         */
+        VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
+        VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
+        {
+            .name = "fpscr",
+            .version_id = 0,
+            .size = sizeof(uint32_t),
+            .info = &vmstate_fpscr,
+            .flags = VMS_SINGLE,
+            .offset = 0,
+        },
         VMSTATE_END_OF_LIST()
     }
 };
-- 
1.7.9.5

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Blue Swirl]

Thanks, pulled.

On Fri, Apr 19, 2013 at 3:06 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> target-arm pullreq, containing a fix for a dumb SRS bug I
> introduced, and the update to migration to use vmstate
> (both of which have been on the list since before freeze).
> Please pull.
>
> thanks
> -- PMM
>
> The following changes since commit 09dada400328d75daf79e3eca1e48e024fec148d:
>
>   configure: remove duplicate test (2013-04-18 14:12:31 +0200)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.next
>
> for you to fetch changes up to e91f229a253f489f6d12b946ad7bdcdc158c5b67:
>
>   target-arm: Correctly restore FPSCR (2013-04-19 12:24:19 +0100)
>
> ----------------------------------------------------------------
> Juan Quintela (1):
>       target-arm: port ARM CPU save/load to use VMState
>
> Peter Chubb (1):
>       target-arm: Reinsert missing return statement in ARM mode SRS decode
>
> Peter Maydell (2):
>       target-arm: Add some missing CPU state fields to VMState
>       target-arm: Correctly restore FPSCR
>
>  target-arm/cpu-qom.h   |    4 +
>  target-arm/cpu.c       |    1 +
>  target-arm/cpu.h       |    2 -
>  target-arm/machine.c   |  430 ++++++++++++++++++++++++------------------------
>  target-arm/translate.c |    1 +
>  5 files changed, 222 insertions(+), 216 deletions(-)

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

A handful of minor ARM bugfixes...

thanks
-- PMM

The following changes since commit 229c0372cf3ca201c41d2bb121627e6752e776ad:

  Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2015-11-24 10:27:19 +0000)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151124

for you to fetch changes up to e14f0eb12f920fd96b9f79d15cedd437648e8667:

  target-arm/translate-a64.c: Correct unallocated checks for ldst_excl (2015-11-24 14:12:15 +0000)

----------------------------------------------------------------
target-arm queue:
 * fix minimum RAM check warning on xlnx-ep108
 * remove unused define from aarch64-linux-user.mak config
 * don't mask out bits [47:40] in ARMv8 LPAE descriptors
 * correct unallocated instruction checks for ldst_excl

----------------------------------------------------------------
Alistair Francis (1):
      xlnx-ep108: Fix minimum RAM check

Peter Maydell (3):
      default-configs/aarch64-linux-user.mak: Remove unused define
      target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8
      target-arm/translate-a64.c: Correct unallocated checks for ldst_excl

 default-configs/aarch64-linux-user.mak |  2 --
 hw/arm/xlnx-ep108.c                    |  2 +-
 target-arm/helper.c                    | 12 +++++++++++-
 target-arm/translate-a64.c             | 15 ++-------------
 4 files changed, 14 insertions(+), 17 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

On 24 November 2015 at 14:18, Peter Maydell <peter.maydell@linaro.org> wrote:
> A handful of minor ARM bugfixes...
>
> thanks
> -- PMM
>
> The following changes since commit 229c0372cf3ca201c41d2bb121627e6752e776ad:
>
>   Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2015-11-24 10:27:19 +0000)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151124
>
> for you to fetch changes up to e14f0eb12f920fd96b9f79d15cedd437648e8667:
>
>   target-arm/translate-a64.c: Correct unallocated checks for ldst_excl (2015-11-24 14:12:15 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * fix minimum RAM check warning on xlnx-ep108
>  * remove unused define from aarch64-linux-user.mak config
>  * don't mask out bits [47:40] in ARMv8 LPAE descriptors
>  * correct unallocated instruction checks for ldst_excl
>
> ----------------------------------------------------------------
> Alistair Francis (1):
>       xlnx-ep108: Fix minimum RAM check
>
> Peter Maydell (3):
>       default-configs/aarch64-linux-user.mak: Remove unused define
>       target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8
>       target-arm/translate-a64.c: Correct unallocated checks for ldst_excl

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

Hi; here's the last target-arm pull request before I
go off on holiday -- four fairly minor bug fixes.
Hopefully it merges without problems, because I won't
be around tomorrow to do a respin :-)

thanks
-- PMM

The following changes since commit 9226682a401f34b10fd79dfe17ba334da0800747:

  Merge remote-tracking branch 'sstabellini/tags/xen-20161102-tag' into staging (2016-11-04 09:26:24 +0000)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20161107

for you to fetch changes up to 9706e0162d2405218fd7376ffdf13baed8569a4b:

  hw/i2c/bitbang_i2c: Handle NACKs from devices (2016-11-07 10:01:15 +0000)

----------------------------------------------------------------
target-arm queue:
 * bitbang_i2c: Handle NACKs from devices
 * Fix corruption of CPSR when SCTLR.EE is set
 * nvic: set pending status for not active interrupts
 * char: cadence: check baud rate generator and divider values

----------------------------------------------------------------
Julian Brown (1):
      Fix corruption of CPSR when SCTLR.EE is set

Marcin Krzeminski (1):
      nvic: set pending status for not active interrupts

Peter Maydell (1):
      hw/i2c/bitbang_i2c: Handle NACKs from devices

Prasad J Pandit (1):
      char: cadence: check baud rate generator and divider values

 hw/char/cadence_uart.c | 15 +++++++++++++++
 hw/i2c/bitbang_i2c.c   | 19 +++++++++++++++----
 hw/intc/arm_gic.c      | 22 ++++++++++++++++++++--
 target-arm/helper.c    |  2 +-
 4 files changed, 51 insertions(+), 7 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Stefan Hajnoczi]

[-- Attachment #1: Type: text/plain, Size: 1865 bytes --]

On Mon, Nov 07, 2016 at 10:47:29AM +0000, Peter Maydell wrote:
> Hi; here's the last target-arm pull request before I
> go off on holiday -- four fairly minor bug fixes.
> Hopefully it merges without problems, because I won't
> be around tomorrow to do a respin :-)
> 
> thanks
> -- PMM
> 
> The following changes since commit 9226682a401f34b10fd79dfe17ba334da0800747:
> 
>   Merge remote-tracking branch 'sstabellini/tags/xen-20161102-tag' into staging (2016-11-04 09:26:24 +0000)
> 
> are available in the git repository at:
> 
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20161107
> 
> for you to fetch changes up to 9706e0162d2405218fd7376ffdf13baed8569a4b:
> 
>   hw/i2c/bitbang_i2c: Handle NACKs from devices (2016-11-07 10:01:15 +0000)
> 
> ----------------------------------------------------------------
> target-arm queue:
>  * bitbang_i2c: Handle NACKs from devices
>  * Fix corruption of CPSR when SCTLR.EE is set
>  * nvic: set pending status for not active interrupts
>  * char: cadence: check baud rate generator and divider values
> 
> ----------------------------------------------------------------
> Julian Brown (1):
>       Fix corruption of CPSR when SCTLR.EE is set
> 
> Marcin Krzeminski (1):
>       nvic: set pending status for not active interrupts
> 
> Peter Maydell (1):
>       hw/i2c/bitbang_i2c: Handle NACKs from devices
> 
> Prasad J Pandit (1):
>       char: cadence: check baud rate generator and divider values
> 
>  hw/char/cadence_uart.c | 15 +++++++++++++++
>  hw/i2c/bitbang_i2c.c   | 19 +++++++++++++++----
>  hw/intc/arm_gic.c      | 22 ++++++++++++++++++++--
>  target-arm/helper.c    |  2 +-
>  4 files changed, 51 insertions(+), 7 deletions(-)

Thanks, applied to my staging tree:
https://github.com/stefanha/qemu/commits/staging

Stefan

[-- Attachment #2: signature.asc --]
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[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

A surprisingly short target-arm queue, but no point in holding
onto these waiting for more code to arrive :-)

thanks
-- PMM

The following changes since commit 3d0bf8dfdfebd7f2ae41b6f220444b8047d6b1ee:

  Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20170710a' into staging (2017-07-10 18:13:03 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170711

for you to fetch changes up to 792dac309c8660306557ba058b8b5a6a75ab3c1f:

  target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode (2017-07-11 11:21:26 +0100)

----------------------------------------------------------------
target-arm queue:
 * v7M: ignore writes to CONTROL.SPSEL from Thread mode
 * KVM: Enable in-kernel timers with user space gic
 * aspeed: Register all watchdogs
 * hw/misc: Add Exynos4210 Pseudo Random Number Generator

----------------------------------------------------------------
Alexander Graf (1):
      ARM: KVM: Enable in-kernel timers with user space gic

Joel Stanley (1):
      aspeed: Register all watchdogs

Krzysztof Kozlowski (1):
      hw/misc: Add Exynos4210 Pseudo Random Number Generator

Peter Maydell (1):
      target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode

 hw/misc/Makefile.objs       |   2 +-
 include/hw/arm/aspeed_soc.h |   4 +-
 include/sysemu/kvm.h        |  11 ++
 target/arm/cpu.h            |   3 +
 accel/kvm/kvm-all.c         |   5 +
 accel/stubs/kvm-stub.c      |   5 +
 hw/arm/aspeed_soc.c         |  25 ++--
 hw/arm/exynos4210.c         |   4 +
 hw/intc/arm_gic.c           |   7 ++
 hw/misc/exynos4210_rng.c    | 277 ++++++++++++++++++++++++++++++++++++++++++++
 target/arm/helper.c         |  13 ++-
 target/arm/kvm.c            |  51 ++++++++
 12 files changed, 394 insertions(+), 13 deletions(-)
 create mode 100644 hw/misc/exynos4210_rng.c

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

On 11 July 2017 at 11:29, Peter Maydell <peter.maydell@linaro.org> wrote:
> A surprisingly short target-arm queue, but no point in holding
> onto these waiting for more code to arrive :-)
>
> thanks
> -- PMM
>
> The following changes since commit 3d0bf8dfdfebd7f2ae41b6f220444b8047d6b1ee:
>
>   Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20170710a' into staging (2017-07-10 18:13:03 +0100)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170711
>
> for you to fetch changes up to 792dac309c8660306557ba058b8b5a6a75ab3c1f:
>
>   target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode (2017-07-11 11:21:26 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * v7M: ignore writes to CONTROL.SPSEL from Thread mode
>  * KVM: Enable in-kernel timers with user space gic
>  * aspeed: Register all watchdogs
>  * hw/misc: Add Exynos4210 Pseudo Random Number Generator
>

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

ARM queue, mostly bug fixes to go into rc0.
The integratorcp and fsl_imx* changes are migration
compat breakers but that's ok for these boards.

thanks
-- PMM


The following changes since commit ce1d20aac8533357650774c2c240e30de87dc122:

  Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-07-24' into staging (2017-07-24 16:20:47 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170724

for you to fetch changes up to b2d1b0507d1b80f23da12dd8aab56944fe380a09:

  integratorcp: Don't migrate flash using vmstate_register_ram_global() (2017-07-24 17:59:28 +0100)

----------------------------------------------------------------
target-arm queue:
 * fix a TCG temporary leak in aarch64 rev16
 * fsl_imx*: migrate the ROM contents
 * integratorcp: don't use vmstate_register_ram_global for flash
 * mps2: Correctly set parent bus for SCC device

----------------------------------------------------------------
Emilio G. Cota (1):
      target/arm: fix TCG temp leak in aarch64 rev16

Peter Maydell (3):
      fsl_imx*: Migrate ROM contents
      mps2: Correctly set parent bus for SCC device
      integratorcp: Don't migrate flash using vmstate_register_ram_global()

 hw/arm/fsl-imx25.c         | 4 ++--
 hw/arm/fsl-imx31.c         | 4 ++--
 hw/arm/fsl-imx6.c          | 4 ++--
 hw/arm/integratorcp.c      | 3 +--
 hw/arm/mps2.c              | 2 +-
 target/arm/translate-a64.c | 1 +
 6 files changed, 9 insertions(+), 9 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

On 24 July 2017 at 18:06, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM queue, mostly bug fixes to go into rc0.
> The integratorcp and fsl_imx* changes are migration
> compat breakers but that's ok for these boards.
>
> thanks
> -- PMM
>
>
> The following changes since commit ce1d20aac8533357650774c2c240e30de87dc122:
>
>   Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-07-24' into staging (2017-07-24 16:20:47 +0100)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170724
>
> for you to fetch changes up to b2d1b0507d1b80f23da12dd8aab56944fe380a09:
>
>   integratorcp: Don't migrate flash using vmstate_register_ram_global() (2017-07-24 17:59:28 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * fix a TCG temporary leak in aarch64 rev16
>  * fsl_imx*: migrate the ROM contents
>  * integratorcp: don't use vmstate_register_ram_global for flash
>  * mps2: Correctly set parent bus for SCC device
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

A last handful of patches before the rc0. These are all bugfixes
so they could equally well go into rc1, but since my pullreq
queue is otherwise empty I might as well push them out. The
FPSCR bugfix is definitely one I'd like in rc0; the rest are
not really user-visible I think.

thanks
-- PMM

The following changes since commit c4107e8208d0222f9b328691b519aaee4101db87:

  Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-07-08 10:26:18 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190708

for you to fetch changes up to 85795187f416326f87177cabc39fae1911f04c50:

  target/arm/vfp_helper: Call set_fpscr_to_host before updating to FPSCR (2019-07-08 14:11:31 +0100)

----------------------------------------------------------------
target-arm queue:
 * tests/migration-test: Fix read off end of aarch64_kernel array
 * Fix sve_zcr_len_for_el off-by-one error
 * hw/arm/sbsa-ref: Silence Coverity nit
 * vfp_helper: Call set_fpscr_to_host before updating to FPSCR

----------------------------------------------------------------
Peter Maydell (2):
      tests/migration-test: Fix read off end of aarch64_kernel array
      hw/arm/sbsa-ref: Remove unnecessary check for secure_sysmem == NULL

Philippe Mathieu-Daudé (1):
      target/arm/vfp_helper: Call set_fpscr_to_host before updating to FPSCR

Richard Henderson (1):
      target/arm: Fix sve_zcr_len_for_el

 hw/arm/sbsa-ref.c       |  8 ++------
 target/arm/helper.c     |  4 ++--
 target/arm/vfp_helper.c |  4 ++--
 tests/migration-test.c  | 22 +++++++---------------
 4 files changed, 13 insertions(+), 25 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

On Mon, 8 Jul 2019 at 14:22, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> A last handful of patches before the rc0. These are all bugfixes
> so they could equally well go into rc1, but since my pullreq
> queue is otherwise empty I might as well push them out. The
> FPSCR bugfix is definitely one I'd like in rc0; the rest are
> not really user-visible I think.
>
> thanks
> -- PMM
>
> The following changes since commit c4107e8208d0222f9b328691b519aaee4101db87:
>
>   Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-07-08 10:26:18 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190708
>
> for you to fetch changes up to 85795187f416326f87177cabc39fae1911f04c50:
>
>   target/arm/vfp_helper: Call set_fpscr_to_host before updating to FPSCR (2019-07-08 14:11:31 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * tests/migration-test: Fix read off end of aarch64_kernel array
>  * Fix sve_zcr_len_for_el off-by-one error
>  * hw/arm/sbsa-ref: Silence Coverity nit
>  * vfp_helper: Call set_fpscr_to_host before updating to FPSCR


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
for any user-visible changes.

-- PMM

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/20190708132237.7911-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20190708132237.7911-1-peter.maydell@linaro.org
Type: series
Subject: [Qemu-devel] [PULL 0/4] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 t [tag update]            patchew/20190708132237.7911-1-peter.maydell@linaro.org -> patchew/20190708132237.7911-1-peter.maydell@linaro.org
Switched to a new branch 'test'

=== OUTPUT BEGIN ===
checkpatch.pl: no revisions returned for revlist '1'
=== OUTPUT END ===

Test command exited with code: 255


The full log is available at
http://patchew.org/logs/20190708132237.7911-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
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