From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:53281) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UTDCb-0007Gu-06 for qemu-devel@nongnu.org; Fri, 19 Apr 2013 11:26:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UTDCY-0000XY-6A for qemu-devel@nongnu.org; Fri, 19 Apr 2013 11:26:16 -0400 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:56681 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UTDCX-0000X2-VK for qemu-devel@nongnu.org; Fri, 19 Apr 2013 11:26:14 -0400 From: Peter Maydell Date: Fri, 19 Apr 2013 16:06:57 +0100 Message-Id: <1366384020-13253-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1366384020-13253-1-git-send-email-peter.maydell@linaro.org> References: <1366384020-13253-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 1/4] target-arm: Reinsert missing return statement in ARM mode SRS decode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno , Blue Swirl Cc: Anthony Liguori , qemu-devel@nongnu.org, Paul Brook From: Peter Chubb Since patch 81465888c5306cd94abb9847e560796fd13d3c2f target-arm: factor out handling of SRS instruction the ARM mode SRS instruction has not worked in QEMU. The problem is a missing return directive that was removed in the refactoring, so after decoding the instruction, qemu would fall through to generate an UNDEF exception for an illegal instruction. Signed-off-by: Peter Chubb Signed-off-by: Peter Maydell --- target-arm/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target-arm/translate.c b/target-arm/translate.c index 35a21be..a1b7b8c 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6762,6 +6762,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) } ARCH(6); gen_srs(s, (insn & 0x1f), (insn >> 23) & 3, insn & (1 << 21)); + return; } else if ((insn & 0x0e50ffe0) == 0x08100a00) { /* rfe */ int32_t offset; -- 1.7.9.5