From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47437) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UTgbE-0000mS-Tr for qemu-devel@nongnu.org; Sat, 20 Apr 2013 18:49:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UTgbD-0005rW-Ot for qemu-devel@nongnu.org; Sat, 20 Apr 2013 18:49:40 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:50856) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UTgbD-0005oz-I6 for qemu-devel@nongnu.org; Sat, 20 Apr 2013 18:49:39 -0400 From: Aurelien Jarno Date: Sun, 21 Apr 2013 00:48:43 +0200 Message-Id: <1366498123-21182-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH] tcg: fix deposit_i64 op on 32-bit targets List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , Aurelien Jarno , "Michael S. Tsirkin" On 32-bit TCG targets, when emulating deposit_i64 with a mov_i32 + deposit_i32, care should be taken to not overwrite the low part of the second argument before the deposit when it is the same the destination. This fixes the shld instruction in qemu-system-x86_64, which in turns fixes booting "system rescue CD version 2.8.0" on this target. Reported-by: Michael S. Tsirkin Cc: Richard Henderson Cc: Paolo Bonzini Signed-off-by: Aurelien Jarno --- tcg/tcg-op.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index d70b2eb..94f6043 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2188,9 +2188,9 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, #if TCG_TARGET_REG_BITS == 32 if (ofs >= 32) { - tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_LOW(arg2), ofs - 32, len); + tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); return; } if (ofs + len <= 32) { -- 1.7.10.4