From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:48662) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUk7M-0001W5-DE for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UUk7J-0003fo-Ot for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:12 -0400 Received: from mail-wg0-x22d.google.com ([2a00:1450:400c:c00::22d]:64958) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUk7J-0003fZ-Fr for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:09 -0400 Received: by mail-wg0-f45.google.com with SMTP id l18so518750wgh.12 for ; Tue, 23 Apr 2013 13:47:08 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 23 Apr 2013 13:46:37 -0700 Message-Id: <1366750012-25015-6-git-send-email-rth@twiddle.net> In-Reply-To: <1366750012-25015-1-git-send-email-rth@twiddle.net> References: <1366750012-25015-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v6 05/20] tcg-arm: Allow constant first argument to sub List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net This allows the generation of RSB instructions. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index de8465b..6c7113b 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1625,8 +1625,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, args[0], args[1], args[2], const_args[2]); break; case INDEX_op_sub_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, - args[0], args[1], args[2], const_args[2]); + if (const_args[1]) { + if (const_args[2]) { + tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); + } else { + tcg_out_dat_rI(s, COND_AL, ARITH_RSB, + args[0], args[2], args[1], 1); + } + } else { + tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, + args[0], args[1], args[2], const_args[2]); + } break; case INDEX_op_and_i32: tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, @@ -1819,7 +1828,7 @@ static const TCGTargetOpDef arm_op_defs[] = { /* TODO: "r", "r", "ri" */ { INDEX_op_add_i32, { "r", "r", "rIN" } }, - { INDEX_op_sub_i32, { "r", "r", "rIN" } }, + { INDEX_op_sub_i32, { "r", "rI", "rIN" } }, { INDEX_op_mul_i32, { "r", "r", "r" } }, { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, { INDEX_op_muls2_i32, { "r", "r", "r", "r" } }, -- 1.8.1.4