From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:57749) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUxvk-0006Oz-UL for qemu-devel@nongnu.org; Wed, 24 Apr 2013 07:32:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UUxvj-0005uV-Hx for qemu-devel@nongnu.org; Wed, 24 Apr 2013 07:32:08 -0400 Received: from mail-ee0-f42.google.com ([74.125.83.42]:64383) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUxvj-0005uN-Ay for qemu-devel@nongnu.org; Wed, 24 Apr 2013 07:32:07 -0400 Received: by mail-ee0-f42.google.com with SMTP id c41so378403eek.15 for ; Wed, 24 Apr 2013 04:32:06 -0700 (PDT) From: edgar.iglesias@gmail.com Date: Wed, 24 Apr 2013 13:31:34 +0200 Message-Id: <1366803094-11619-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v2] microblaze: Add internal base vectors reg List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.crosthwaite@xilinx.com, afaerber@suse.de From: "Edgar E. Iglesias" Configurable at CPU synthesis/instantiation. Signed-off-by: Edgar E. Iglesias --- Peter Crosthwaite commented off-list that it would be a good idea to make this a device property. I agree but am a bit unsure of how it should look. Any comments on this attempt? v2: Make base_vectors a CPU/device property. target-microblaze/cpu-qom.h | 1 + target-microblaze/cpu.c | 8 ++++++++ target-microblaze/helper.c | 8 ++++---- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index aa51cf6..ce92a4e 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -56,6 +56,7 @@ typedef struct MicroBlazeCPUClass { typedef struct MicroBlazeCPU { /*< private >*/ CPUState parent_obj; + uint32_t base_vectors; /*< public >*/ CPUMBState env; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 0f4293d..404f82c 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "qemu-common.h" +#include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -119,6 +120,11 @@ static const VMStateDescription vmstate_mb_cpu = { .unmigratable = 1, }; +static Property mb_properties[] = { + DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void mb_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -133,6 +139,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->do_interrupt = mb_cpu_do_interrupt; dc->vmsd = &vmstate_mb_cpu; + + dc->props = mb_properties; } static const TypeInfo mb_cpu_type_info = { diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index a0416d0..0dd669d 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -152,7 +152,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, env, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = 0x20; + env->sregs[SR_PC] = cpu->base_vectors + 0x20; break; case EXCP_MMU: @@ -192,7 +192,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, env, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = 0x20; + env->sregs[SR_PC] = cpu->base_vectors + 0x20; break; case EXCP_IRQ: @@ -233,7 +233,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_MSR] |= t; env->regs[14] = env->sregs[SR_PC]; - env->sregs[SR_PC] = 0x10; + env->sregs[SR_PC] = cpu->base_vectors + 0x10; //log_cpu_state_mask(CPU_LOG_INT, env, 0); break; @@ -252,7 +252,7 @@ void mb_cpu_do_interrupt(CPUState *cs) if (env->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->sregs[SR_PC]; env->sregs[SR_MSR] |= MSR_BIP; - env->sregs[SR_PC] = 0x18; + env->sregs[SR_PC] = cpu->base_vectors + 0x18; } else env->sregs[SR_PC] = env->btarget; break; -- 1.7.10.4