From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:42459) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UVq5F-0004rC-7g for qemu-devel@nongnu.org; Fri, 26 Apr 2013 17:21:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UVq5E-0004cm-5f for qemu-devel@nongnu.org; Fri, 26 Apr 2013 17:21:33 -0400 Message-ID: <1367011280.17497.24.camel@pasglop> From: Benjamin Herrenschmidt Date: Sat, 27 Apr 2013 07:21:20 +1000 Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH] ppc/spapr: Fix cache related properties List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: qemu-ppc List , qemu-devel , David Gibson The properties in the CPU nodes for expressing the cache block size are spelled {d,i}-cache... not {d,i}cache... Also add the "line" variants in addition to the "block" variants for completeness (some OSes might require them). Signed-off-by: Benjamin Herrenschmidt --- diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 7a42501..7582a05 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -333,9 +333,13 @@ static void *spapr_create_fdt_skel(const char *cpu_model, _FDT((fdt_property_string(fdt, "device_type", "cpu"))); _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); - _FDT((fdt_property_cell(fdt, "dcache-block-size", + _FDT((fdt_property_cell(fdt, "d-cache-block-size", env->dcache_line_size))); - _FDT((fdt_property_cell(fdt, "icache-block-size", + _FDT((fdt_property_cell(fdt, "i-cache-block-size", + env->icache_line_size))); + _FDT((fdt_property_cell(fdt, "d-cache-line-size", + env->dcache_line_size))); + _FDT((fdt_property_cell(fdt, "i-cache-line-size", env->icache_line_size))); _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));