From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:58140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UWrTz-00039F-4T for qemu-devel@nongnu.org; Mon, 29 Apr 2013 13:03:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UWrTl-0004gd-8q for qemu-devel@nongnu.org; Mon, 29 Apr 2013 13:03:19 -0400 Received: from mx1.redhat.com ([209.132.183.28]:31689) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UWrTk-0004fz-TP for qemu-devel@nongnu.org; Mon, 29 Apr 2013 13:03:05 -0400 From: Igor Mammedov Date: Mon, 29 Apr 2013 19:03:01 +0200 Message-Id: <1367254981-29385-1-git-send-email-imammedo@redhat.com> In-Reply-To: <1367247776-7695-4-git-send-email-imammedo@redhat.com> References: <1367247776-7695-4-git-send-email-imammedo@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 3/7 v8] target-i386: Move APIC to ICC bus List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@us.ibm.com, afaerber@suse.de, ehabkost@redhat.com It allows APIC to be hotplugged. * map APIC's mmio at board level if it is present * do not register mmio region for each APIC, since only one is used/mapped Signed-off-by: Igor Mammedov Signed-off-by: Andreas F=C3=A4rber --- v3: - fix compile error caused by mismerged hunk v2: - use icc-bridge from args instead of resolving it --- hw/cpu/icc_bus.c | 10 ++++++++++ hw/i386/pc.c | 13 +++++++++++-- hw/intc/apic_common.c | 18 ++++++++++++------ include/hw/cpu/icc_bus.h | 3 +++ include/hw/i386/apic_internal.h | 6 +++--- target-i386/cpu.c | 16 +++------------- 6 files changed, 42 insertions(+), 24 deletions(-) diff --git a/hw/cpu/icc_bus.c b/hw/cpu/icc_bus.c index 3ac8eeb..73a1dc9 100644 --- a/hw/cpu/icc_bus.c +++ b/hw/cpu/icc_bus.c @@ -80,6 +80,7 @@ typedef struct ICCBridgeState { /*< public >*/ =20 ICCBus icc_bus; + MemoryRegion apic_container; } ICCBridgeState; =20 #define ICC_BRIGDE(obj) OBJECT_CHECK(ICCBridgeState, (obj), TYPE_ICC_BRI= DGE) @@ -87,8 +88,17 @@ typedef struct ICCBridgeState { static void icc_bridge_init(Object *obj) { ICCBridgeState *s =3D ICC_BRIGDE(obj); + SysBusDevice *sb =3D SYS_BUS_DEVICE(obj); =20 qbus_create_inplace(&s->icc_bus, TYPE_ICC_BUS, DEVICE(s), "icc"); + + /* Do not change order of registering regions, + * APIC must be first registered region, board maps it by 0 index + */ + memory_region_init(&s->apic_container, "icc-apic-container", + APIC_SPACE_SIZE); + sysbus_init_mmio(sb, &s->apic_container); + s->icc_bus.apic_address_space =3D &s->apic_container; } =20 static const TypeInfo icc_bridge_info =3D { diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 658ff6c..6b3faac 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -53,6 +53,7 @@ #include "qemu/bitmap.h" #include "qemu/config-file.h" #include "hw/acpi/acpi.h" +#include "hw/cpu/icc_bus.h" =20 /* debug PC/ISA interrupts */ //#define DEBUG_IRQ @@ -917,6 +918,7 @@ static X86CPU *pc_new_cpu(const char *cpu_model, int6= 4_t apic_id, void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) { int i; + X86CPU *cpu =3D NULL; Error *error =3D NULL; =20 /* init CPUs */ @@ -929,14 +931,21 @@ void pc_cpus_init(const char *cpu_model, DeviceStat= e *icc_bridge) } =20 for (i =3D 0; i < smp_cpus; i++) { - pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), - icc_bridge, &error); + cpu =3D pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), + icc_bridge, &error); if (error) { fprintf(stderr, "%s\n", error_get_pretty(error)); error_free(error); exit(1); } } + + /* map APIC MMIO area if CPU has APIC */ + if (cpu && cpu->env.apic_state) { + /* XXX: what if the base changes? */ + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, + APIC_DEFAULT_ADDRESS, 0x1000); + } } =20 void pc_acpi_init(const char *default_dsdt) diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index e0ae07a..b03e904 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -21,6 +21,8 @@ #include "hw/i386/apic_internal.h" #include "trace.h" #include "sysemu/kvm.h" +#include "hw/qdev.h" +#include "hw/sysbus.h" =20 static int apic_irq_delivered; bool apic_report_tpr_access; @@ -282,12 +284,13 @@ static int apic_load_old(QEMUFile *f, void *opaque,= int version_id) return 0; } =20 -static int apic_init_common(SysBusDevice *dev) +static int apic_init_common(ICCDevice *dev) { APICCommonState *s =3D APIC_COMMON(dev); APICCommonClass *info; static DeviceState *vapic; static int apic_no; + static bool mmio_registered; =20 if (apic_no >=3D MAX_APICS) { return -1; @@ -296,8 +299,11 @@ static int apic_init_common(SysBusDevice *dev) =20 info =3D APIC_COMMON_GET_CLASS(s); info->init(s); - - sysbus_init_mmio(dev, &s->io_memory); + if (!mmio_registered) { + ICCBus *b =3D ICC_BUS(qdev_get_parent_bus(DEVICE(dev))); + memory_region_add_subregion(b->apic_address_space, 0, &s->io_mem= ory); + mmio_registered =3D true; + } =20 /* Note: We need at least 1M to map the VAPIC option ROM */ if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && @@ -375,19 +381,19 @@ static Property apic_properties_common[] =3D { =20 static void apic_common_class_init(ObjectClass *klass, void *data) { - SysBusDeviceClass *sc =3D SYS_BUS_DEVICE_CLASS(klass); + ICCDeviceClass *idc =3D ICC_DEVICE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->vmsd =3D &vmstate_apic_common; dc->reset =3D apic_reset_common; dc->no_user =3D 1; dc->props =3D apic_properties_common; - sc->init =3D apic_init_common; + idc->init =3D apic_init_common; } =20 static const TypeInfo apic_common_type =3D { .name =3D TYPE_APIC_COMMON, - .parent =3D TYPE_SYS_BUS_DEVICE, + .parent =3D TYPE_ICC_DEVICE, .instance_size =3D sizeof(APICCommonState), .class_size =3D sizeof(APICCommonClass), .class_init =3D apic_common_class_init, diff --git a/include/hw/cpu/icc_bus.h b/include/hw/cpu/icc_bus.h index d728a7d..b550070 100644 --- a/include/hw/cpu/icc_bus.h +++ b/include/hw/cpu/icc_bus.h @@ -22,6 +22,7 @@ #ifndef ICC_BUS_H #define ICC_BUS_H =20 +#include "exec/memory.h" #include "hw/qdev-core.h" =20 #define TYPE_ICC_BUS "icc-bus" @@ -37,6 +38,8 @@ typedef struct ICCBus { /*< private >*/ BusState parent_obj; /*< public >*/ + + MemoryRegion *apic_address_space; } ICCBus; =20 #define ICC_BUS(obj) OBJECT_CHECK(ICCBus, (obj), TYPE_ICC_BUS) diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_inter= nal.h index aac6290..1b0a7fb 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -21,7 +21,7 @@ #define QEMU_APIC_INTERNAL_H =20 #include "exec/memory.h" -#include "hw/sysbus.h" +#include "hw/cpu/icc_bus.h" #include "qemu/timer.h" =20 /* APIC Local Vector Table */ @@ -78,7 +78,7 @@ typedef struct APICCommonState APICCommonState; =20 typedef struct APICCommonClass { - SysBusDeviceClass parent_class; + ICCDeviceClass parent_class; =20 void (*init)(APICCommonState *s); void (*set_base)(APICCommonState *s, uint64_t val); @@ -92,7 +92,7 @@ typedef struct APICCommonClass } APICCommonClass; =20 struct APICCommonState { - SysBusDevice busdev; + ICCDevice busdev; =20 MemoryRegion io_memory; X86CPU *cpu; diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 4fe4325..dc92b97 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -41,10 +41,10 @@ #endif =20 #include "sysemu/sysemu.h" +#include "hw/qdev-properties.h" #include "hw/cpu/icc_bus.h" #ifndef CONFIG_USER_ONLY #include "hw/xen/xen.h" -#include "hw/sysbus.h" #include "hw/i386/apic_internal.h" #endif =20 @@ -2131,6 +2131,7 @@ static void mce_init(X86CPU *cpu) static void x86_cpu_apic_create(X86CPU *cpu, Error **errp) { CPUX86State *env =3D &cpu->env; + DeviceState *dev =3D DEVICE(cpu); APICCommonState *apic; const char *apic_type =3D "apic"; =20 @@ -2140,7 +2141,7 @@ static void x86_cpu_apic_create(X86CPU *cpu, Error = **errp) apic_type =3D "xen-apic"; } =20 - env->apic_state =3D qdev_try_create(NULL, apic_type); + env->apic_state =3D qdev_try_create(qdev_get_parent_bus(dev), apic_t= ype); if (env->apic_state =3D=3D NULL) { error_setg(errp, "APIC device '%s' could not be created", apic_t= ype); return; @@ -2157,7 +2158,6 @@ static void x86_cpu_apic_create(X86CPU *cpu, Error = **errp) static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) { CPUX86State *env =3D &cpu->env; - static int apic_mapped; =20 if (env->apic_state =3D=3D NULL) { return; @@ -2168,16 +2168,6 @@ static void x86_cpu_apic_realize(X86CPU *cpu, Erro= r **errp) object_get_typename(OBJECT(env->apic_state))); return; } - - /* XXX: mapping more APICs at the same memory location */ - if (apic_mapped =3D=3D 0) { - /* NOTE: the APIC is directly connected to the CPU - it is not - on the global memory bus. */ - /* XXX: what if the base changes? */ - sysbus_mmio_map_overlap(SYS_BUS_DEVICE(env->apic_state), 0, - APIC_DEFAULT_ADDRESS, 0x1000); - apic_mapped =3D 1; - } } #else static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) --=20 1.8.2.1