From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:45933) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UXfY6-0005r3-0W for qemu-devel@nongnu.org; Wed, 01 May 2013 18:30:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UXfY4-0000oV-MG for qemu-devel@nongnu.org; Wed, 01 May 2013 18:30:53 -0400 From: Alexander Graf Date: Thu, 2 May 2013 00:30:44 +0200 Message-Id: <1367447444-17563-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH] PPC: Add MMU type for 2.06 with AMR but no TB pages List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org When running -cpu on a POWER7 system with PR KVM, we mask out the 1TB MMU capability from the MMU type mask, but not the AMR bit. This leads to us having a new MMU type that we don't check for in our MMU management functions. Add the new type, so that we don't have to worry about breakage there. We're not going to use the TCG MMU management in that case anyway. The long term fix for this will be to move all these MMU management functions to class callbacks. Signed-off-by: Alexander Graf --- target-ppc/cpu.h | 3 +++ target-ppc/mmu_helper.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 7cacb56..aa1d013 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -119,6 +119,9 @@ enum powerpc_mmu_t { /* Architecture 2.06 variant */ POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_AMR | 0x00000003, + /* Architecture 2.06 "degraded" (no 1T segments) */ + POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR + | 0x00000003, /* Architecture 2.06 "degraded" (no 1T segments or AMR) */ POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003, #endif /* defined(TARGET_PPC64) */ diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index acf0133..68d5415 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1188,6 +1188,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) #if defined(TARGET_PPC64) case POWERPC_MMU_64B: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_06d: dump_slb(f, cpu_fprintf, env); break; @@ -1324,6 +1325,7 @@ hwaddr cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr) #if defined(TARGET_PPC64) case POWERPC_MMU_64B: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_06d: return ppc_hash64_get_phys_page_debug(env, addr); #endif @@ -1815,6 +1817,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) #if defined(TARGET_PPC64) case POWERPC_MMU_64B: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_06d: #endif /* defined(TARGET_PPC64) */ tlb_flush(env, 1); @@ -1884,6 +1887,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) #if defined(TARGET_PPC64) case POWERPC_MMU_64B: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_06d: /* tlbie invalidate TLBs for all segments */ /* XXX: given the fact that there are too many segments to invalidate, -- 1.8.1.4