From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:56233) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ua5hC-0007Di-8d for qemu-devel@nongnu.org; Wed, 08 May 2013 10:50:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ua5hA-00055l-GL for qemu-devel@nongnu.org; Wed, 08 May 2013 10:50:18 -0400 Received: from mx1.redhat.com ([209.132.183.28]:1613) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ua5Mp-0005MO-8W for qemu-devel@nongnu.org; Wed, 08 May 2013 10:29:15 -0400 From: Kevin Wolf Date: Wed, 8 May 2013 16:28:57 +0200 Message-Id: <1368023344-29731-4-git-send-email-kwolf@redhat.com> In-Reply-To: <1368023344-29731-1-git-send-email-kwolf@redhat.com> References: <1368023344-29731-1-git-send-email-kwolf@redhat.com> Subject: [Qemu-devel] [PATCH 03/10] ide: Reset BMIDEA bit when the bus master is stopped List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: anthony@codemonkey.ws Cc: kwolf@redhat.com, qemu-devel@nongnu.org The device is supposed to reset the Bus Master IDE Active bit in the status register when 0 is written to the Start/Stop Bus Master bit in the command register. In the common cases this happens automatically because bdrv_drain_all() flushes the requests, but with a large PRDT it could remain set. Signed-off-by: Kevin Wolf --- hw/ide/pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ide/pci.c b/hw/ide/pci.c index a310975..635a364 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -312,6 +312,7 @@ void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val) bdrv_drain_all(); assert(bm->bus->dma->aiocb == NULL); } + bm->status &= ~BM_STATUS_DMAING; } else { bm->cur_addr = bm->addr; if (!(bm->status & BM_STATUS_DMAING)) { -- 1.8.1.4