From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:58403) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uc6ve-0007Fg-II for qemu-devel@nongnu.org; Tue, 14 May 2013 00:33:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Uc6vZ-0008EB-Ue for qemu-devel@nongnu.org; Tue, 14 May 2013 00:33:34 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:65450) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uc6vZ-0008Cv-PB for qemu-devel@nongnu.org; Tue, 14 May 2013 00:33:29 -0400 Received: by mail-pa0-f41.google.com with SMTP id rl6so156972pac.28 for ; Mon, 13 May 2013 21:33:29 -0700 (PDT) From: John Rigby Date: Mon, 13 May 2013 22:32:49 -0600 Message-Id: <1368505980-17151-2-git-send-email-john.rigby@linaro.org> In-Reply-To: <1368505980-17151-1-git-send-email-john.rigby@linaro.org> References: <1368505980-17151-1-git-send-email-john.rigby@linaro.org> Subject: [Qemu-devel] [PATCH v4 01/12] ARM: Extract the disas struct to a header file List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: 'Peter Maydell , John Rigby , 'Alexander Graf , Paul Brook From: Alexander Graf We will need to share the disassembly status struct between AArch32 and AArch64 modes. So put it into a header file that both sides can use. Signed-off-by: Alexander Graf Signed-off-by: John Rigby --- target-arm/translate.c | 24 +----------------------- target-arm/translate.h | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 23 deletions(-) create mode 100644 target-arm/translate.h diff --git a/target-arm/translate.c b/target-arm/translate.c index a1b7b8c..675773a 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -45,29 +45,7 @@ #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0) -/* internal defines */ -typedef struct DisasContext { - target_ulong pc; - int is_jmp; - /* Nonzero if this instruction has been conditionally skipped. */ - int condjmp; - /* The label that will be jumped to when the instruction is skipped. */ - int condlabel; - /* Thumb-2 conditional execution bits. */ - int condexec_mask; - int condexec_cond; - struct TranslationBlock *tb; - int singlestep_enabled; - int thumb; - int bswap_code; -#if !defined(CONFIG_USER_ONLY) - int user; -#endif - int vfp_enabled; - int vec_len; - int vec_stride; -} DisasContext; - +#include "translate.h" static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE]; #if defined(CONFIG_USER_ONLY) diff --git a/target-arm/translate.h b/target-arm/translate.h new file mode 100644 index 0000000..e727bc6 --- /dev/null +++ b/target-arm/translate.h @@ -0,0 +1,27 @@ +#ifndef TARGET_ARM_TRANSLATE_H +#define TARGET_ARM_TRANSLATE_H + +/* internal defines */ +typedef struct DisasContext { + target_ulong pc; + int is_jmp; + /* Nonzero if this instruction has been conditionally skipped. */ + int condjmp; + /* The label that will be jumped to when the instruction is skipped. */ + int condlabel; + /* Thumb-2 conditional execution bits. */ + int condexec_mask; + int condexec_cond; + struct TranslationBlock *tb; + int singlestep_enabled; + int thumb; + int bswap_code; +#if !defined(CONFIG_USER_ONLY) + int user; +#endif + int vfp_enabled; + int vec_len; + int vec_stride; +} DisasContext; + +#endif /* TARGET_ARM_TRANSLATE_H */ -- 1.8.2.2