From: John Rigby <john.rigby@linaro.org>
To: qemu-devel@nongnu.org
Cc: 'Peter Maydell <peter.maydell@linaro.org>,
John Rigby <john.rigby@linaro.org>,
'Alexander Graf <agraf@suse.de>
Subject: [Qemu-devel] [PATCH v4 05/12] AArch64: Add gdb stub
Date: Mon, 13 May 2013 22:32:53 -0600 [thread overview]
Message-ID: <1368505980-17151-6-git-send-email-john.rigby@linaro.org> (raw)
In-Reply-To: <1368505980-17151-1-git-send-email-john.rigby@linaro.org>
From: Alexander Graf <agraf@suse.de>
We want to be able to debug AArch64 guests. So let's add the respective gdb
stub functions and xml descriptions that allow us to do so.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
---
Changes in v3:
- fix checkpatch.pl issues
Changes in v4:
- env->sp --> env->xregs[31]
gdb-xml/aarch64-core.xml | 46 ++++++++++++++++++++++++++
gdb-xml/aarch64-fpu.xml | 86 ++++++++++++++++++++++++++++++++++++++++++++++++
gdbstub.c | 53 +++++++++++++++++++++++++++++
3 files changed, 185 insertions(+)
create mode 100644 gdb-xml/aarch64-core.xml
create mode 100644 gdb-xml/aarch64-fpu.xml
diff --git a/gdb-xml/aarch64-core.xml b/gdb-xml/aarch64-core.xml
new file mode 100644
index 0000000..e1e9dc3
--- /dev/null
+++ b/gdb-xml/aarch64-core.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2009-2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.aarch64.core">
+ <reg name="x0" bitsize="64"/>
+ <reg name="x1" bitsize="64"/>
+ <reg name="x2" bitsize="64"/>
+ <reg name="x3" bitsize="64"/>
+ <reg name="x4" bitsize="64"/>
+ <reg name="x5" bitsize="64"/>
+ <reg name="x6" bitsize="64"/>
+ <reg name="x7" bitsize="64"/>
+ <reg name="x8" bitsize="64"/>
+ <reg name="x9" bitsize="64"/>
+ <reg name="x10" bitsize="64"/>
+ <reg name="x11" bitsize="64"/>
+ <reg name="x12" bitsize="64"/>
+ <reg name="x13" bitsize="64"/>
+ <reg name="x14" bitsize="64"/>
+ <reg name="x15" bitsize="64"/>
+ <reg name="x16" bitsize="64"/>
+ <reg name="x17" bitsize="64"/>
+ <reg name="x18" bitsize="64"/>
+ <reg name="x19" bitsize="64"/>
+ <reg name="x20" bitsize="64"/>
+ <reg name="x21" bitsize="64"/>
+ <reg name="x22" bitsize="64"/>
+ <reg name="x23" bitsize="64"/>
+ <reg name="x24" bitsize="64"/>
+ <reg name="x25" bitsize="64"/>
+ <reg name="x26" bitsize="64"/>
+ <reg name="x27" bitsize="64"/>
+ <reg name="x28" bitsize="64"/>
+ <reg name="x29" bitsize="64"/>
+ <reg name="x30" bitsize="64"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+ <reg name="cpsr" bitsize="32"/>
+</feature>
diff --git a/gdb-xml/aarch64-fpu.xml b/gdb-xml/aarch64-fpu.xml
new file mode 100644
index 0000000..997197e
--- /dev/null
+++ b/gdb-xml/aarch64-fpu.xml
@@ -0,0 +1,86 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2009-2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.aarch64.fpu">
+ <vector id="v2d" type="ieee_double" count="2"/>
+ <vector id="v2u" type="uint64" count="2"/>
+ <vector id="v2i" type="int64" count="2"/>
+ <vector id="v4f" type="ieee_single" count="4"/>
+ <vector id="v4u" type="uint32" count="4"/>
+ <vector id="v4i" type="int32" count="4"/>
+ <vector id="v8u" type="uint16" count="8"/>
+ <vector id="v8i" type="int16" count="8"/>
+ <vector id="v16u" type="uint8" count="16"/>
+ <vector id="v16i" type="int8" count="16"/>
+ <vector id="v1u" type="uint128" count="1"/>
+ <vector id="v1i" type="int128" count="1"/>
+ <union id="vnd">
+ <field name="f" type="v2d"/>
+ <field name="u" type="v2u"/>
+ <field name="s" type="v2i"/>
+ </union>
+ <union id="vns">
+ <field name="f" type="v4f"/>
+ <field name="u" type="v4u"/>
+ <field name="s" type="v4i"/>
+ </union>
+ <union id="vnh">
+ <field name="u" type="v8u"/>
+ <field name="s" type="v8i"/>
+ </union>
+ <union id="vnb">
+ <field name="u" type="v16u"/>
+ <field name="s" type="v16i"/>
+ </union>
+ <union id="vnq">
+ <field name="u" type="v1u"/>
+ <field name="s" type="v1i"/>
+ </union>
+ <union id="aarch64v">
+ <field name="d" type="vnd"/>
+ <field name="s" type="vns"/>
+ <field name="h" type="vnh"/>
+ <field name="b" type="vnb"/>
+ <field name="q" type="vnq"/>
+ </union>
+ <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/>
+ <reg name="v1" bitsize="128" type="aarch64v" />
+ <reg name="v2" bitsize="128" type="aarch64v" />
+ <reg name="v3" bitsize="128" type="aarch64v" />
+ <reg name="v4" bitsize="128" type="aarch64v" />
+ <reg name="v5" bitsize="128" type="aarch64v" />
+ <reg name="v6" bitsize="128" type="aarch64v" />
+ <reg name="v7" bitsize="128" type="aarch64v" />
+ <reg name="v8" bitsize="128" type="aarch64v" />
+ <reg name="v9" bitsize="128" type="aarch64v" />
+ <reg name="v10" bitsize="128" type="aarch64v"/>
+ <reg name="v11" bitsize="128" type="aarch64v"/>
+ <reg name="v12" bitsize="128" type="aarch64v"/>
+ <reg name="v13" bitsize="128" type="aarch64v"/>
+ <reg name="v14" bitsize="128" type="aarch64v"/>
+ <reg name="v15" bitsize="128" type="aarch64v"/>
+ <reg name="v16" bitsize="128" type="aarch64v"/>
+ <reg name="v17" bitsize="128" type="aarch64v"/>
+ <reg name="v18" bitsize="128" type="aarch64v"/>
+ <reg name="v19" bitsize="128" type="aarch64v"/>
+ <reg name="v20" bitsize="128" type="aarch64v"/>
+ <reg name="v21" bitsize="128" type="aarch64v"/>
+ <reg name="v22" bitsize="128" type="aarch64v"/>
+ <reg name="v23" bitsize="128" type="aarch64v"/>
+ <reg name="v24" bitsize="128" type="aarch64v"/>
+ <reg name="v25" bitsize="128" type="aarch64v"/>
+ <reg name="v26" bitsize="128" type="aarch64v"/>
+ <reg name="v27" bitsize="128" type="aarch64v"/>
+ <reg name="v28" bitsize="128" type="aarch64v"/>
+ <reg name="v29" bitsize="128" type="aarch64v"/>
+ <reg name="v30" bitsize="128" type="aarch64v"/>
+ <reg name="v31" bitsize="128" type="aarch64v"/>
+ <reg name="fpsr" bitsize="32"/>
+ <reg name="fpcr" bitsize="32"/>
+</feature>
diff --git a/gdbstub.c b/gdbstub.c
index e80e1d3..e85f34a 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -935,6 +935,59 @@ static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
return 8;
#endif
}
+#elif defined(TARGET_AARCH64)
+
+#define NUM_CORE_REGS 34
+#define GDB_CORE_XML "aarch64-core.xml"
+
+static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 31) {
+ /* Core integer register. */
+ GET_REG64(env->xregs[n]);
+ }
+ switch (n) {
+ case 31:
+ GET_REG64(env->xregs[31]);
+ break;
+ case 32:
+ GET_REG64(env->pc);
+ break;
+ case 33:
+ GET_REG32(env->pstate);
+ break;
+ }
+ /* Unknown register. */
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
+{
+ uint64_t tmp;
+
+ tmp = ldq_p(mem_buf);
+
+ if (n < 31) {
+ /* Core integer register. */
+ env->xregs[n] = tmp;
+ return 8;
+ }
+ switch (n) {
+ case 31:
+ env->xregs[31] = tmp;
+ return 8;
+ case 32:
+ env->pc = tmp;
+ return 8;
+ case 33:
+ /* CPSR */
+ env->pstate = tmp;
+ return 4;
+ }
+ /* Unknown register. */
+ return 0;
+}
+
#elif defined (TARGET_ARM)
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
--
1.8.2.2
next prev parent reply other threads:[~2013-05-14 4:33 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-14 4:32 [Qemu-devel] [PATCH v4 00/12] AArch64 preparation patch set John Rigby
2013-05-14 4:32 ` [Qemu-devel] [PATCH v4 01/12] ARM: Extract the disas struct to a header file John Rigby
2013-05-14 4:32 ` [Qemu-devel] [PATCH v4 02/12] ARM: Export cpu_env John Rigby
2013-05-14 4:32 ` [Qemu-devel] [PATCH v4 03/12] ARM: Prepare translation for AArch64 code John Rigby
2013-05-14 4:32 ` [Qemu-devel] [PATCH v4 04/12] ARM: Add AArch64 translation stub John Rigby
2013-05-20 12:57 ` Peter Maydell
2013-06-16 20:06 ` Andreas Färber
2013-06-16 20:24 ` Peter Maydell
2013-05-14 4:32 ` John Rigby [this message]
2013-05-14 4:32 ` [Qemu-devel] [PATCH v4 06/12] linux-user: Don't treat aarch64 cpu names specially John Rigby
2013-05-14 4:32 ` [Qemu-devel] [PATCH v4 07/12] linux-user: Add syscall handling for AArch64 John Rigby
2013-05-14 4:32 ` [Qemu-devel] [PATCH v4 08/12] linux-user: Fix up AArch64 syscall handlers John Rigby
2013-05-14 4:32 ` [Qemu-devel] [PATCH v4 09/12] linux-user: Add signal handling for AArch64 John Rigby
2013-05-14 16:31 ` Richard Henderson
2013-05-14 18:51 ` John Rigby
2013-05-14 4:32 ` [Qemu-devel] [PATCH v4 10/12] linux-user: Add AArch64 support John Rigby
2013-05-14 4:32 ` [Qemu-devel] [PATCH v4 11/12] ARM: Add aarch64 target to configure John Rigby
2013-05-14 4:33 ` [Qemu-devel] [PATCH v4 12/12] linux-user: AArch64 requires at least 3.8.0 John Rigby
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1368505980-17151-6-git-send-email-john.rigby@linaro.org \
--to=john.rigby@linaro.org \
--cc=agraf@suse.de \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).