From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:60628) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UdSZH-0007Dh-3k for qemu-devel@nongnu.org; Fri, 17 May 2013 17:52:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UdSZ7-00024A-Ug for qemu-devel@nongnu.org; Fri, 17 May 2013 17:52:02 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:33443) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UdSZ7-00023y-P4 for qemu-devel@nongnu.org; Fri, 17 May 2013 17:51:53 -0400 From: Kwok Cheung Yeung Date: Fri, 17 May 2013 14:51:19 -0700 Message-ID: <1368827481-20434-1-git-send-email-kcy@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 0/2] linux-user: Fix MIPS16/microMIPS signal handling List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Kwok Cheung Yeung , peter.maydell@linaro.org, riku.voipio@iki.fi, aurelien@aurel32.net These patches fix various issues related to signal handling in user mode emulation for the MIPS architecture. - When a MIPS16/microMIPS signal handler is called, the program segfaults because the PC is set to an invalid address. - When returning from a signal handler, the ISA mode is not set to that of the resume instruction. - When the faulting instruction is in a branch delay slot, the resume address is set to that of the instruction rather than the branch, resulting in incorrect behaviour. The flag indicating that the instruction is in a delay slot is also not cleared. v1 -> v2: - Add fixes for signal return and delay slot instructions - Refactor code Kwok Cheung Yeung (2): linux-user: Fix MIPS ISA transitions during signal handling linux-user: Save the correct resume address for MIPS signal handling linux-user/signal.c | 16 +++++++++++++++- target-mips/cpu.h | 1 + target-mips/helper.c | 4 ++-- 3 files changed, 18 insertions(+), 3 deletions(-) -- 1.8.1.2