From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:60631) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UdSZH-0007Di-7D for qemu-devel@nongnu.org; Fri, 17 May 2013 17:52:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UdSZ8-00024O-QC for qemu-devel@nongnu.org; Fri, 17 May 2013 17:52:03 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:33452) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UdSZ8-00024K-Km for qemu-devel@nongnu.org; Fri, 17 May 2013 17:51:54 -0400 From: Kwok Cheung Yeung Date: Fri, 17 May 2013 14:51:21 -0700 Message-ID: <1368827481-20434-3-git-send-email-kcy@codesourcery.com> In-Reply-To: <1368827481-20434-1-git-send-email-kcy@codesourcery.com> References: <1368827481-20434-1-git-send-email-kcy@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 2/2] linux-user: Save the correct resume address for MIPS signal handling List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Kwok Cheung Yeung , peter.maydell@linaro.org, riku.voipio@iki.fi, aurelien@aurel32.net The current ISA mode needs to be saved in bit 0 of the resume address. If the current instruction happens to be in a branch delay slot, then the address of the preceding jump instruction should be stored instead. exception_resume_pc already does both of these tasks, so it is made available and reused. MIPS_HFLAG_BMASK in hflags is cleared, otherwise QEMU may treat the first instruction of the signal handler as a delay slot instruction. Signed-off-by: Kwok Cheung Yeung --- linux-user/signal.c | 3 ++- target-mips/cpu.h | 1 + target-mips/helper.c | 4 ++-- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/linux-user/signal.c b/linux-user/signal.c index dc34ae7..5da8452 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -2528,7 +2528,8 @@ setup_sigcontext(CPUMIPSState *regs, struct target_sigcontext *sc) int err = 0; int i; - err |= __put_user(regs->active_tc.PC, &sc->sc_pc); + err |= __put_user(exception_resume_pc(regs), &sc->sc_pc); + regs->hflags &= ~MIPS_HFLAG_BMASK; __put_user(0, &sc->sc_regs[0]); for (i = 1; i < 32; ++i) { diff --git a/target-mips/cpu.h b/target-mips/cpu.h index cedf03d..6e761e0 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -668,6 +668,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, int rw); #endif +target_ulong exception_resume_pc (CPUMIPSState *env); static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, target_ulong *cs_base, int *flags) diff --git a/target-mips/helper.c b/target-mips/helper.c index 3a54acf..36929dd 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -366,8 +366,7 @@ static const char * const excp_names[EXCP_LAST + 1] = { [EXCP_CACHE] = "cache error", }; -#if !defined(CONFIG_USER_ONLY) -static target_ulong exception_resume_pc (CPUMIPSState *env) +target_ulong exception_resume_pc (CPUMIPSState *env) { target_ulong bad_pc; target_ulong isa_mode; @@ -383,6 +382,7 @@ static target_ulong exception_resume_pc (CPUMIPSState *env) return bad_pc; } +#if !defined(CONFIG_USER_ONLY) static void set_hflags_for_handler (CPUMIPSState *env) { /* Exception handlers are entered in 32-bit mode. */ -- 1.8.1.2