[Qemu-devel] [PATCH 00/10] target-arm: fix TCGv usage (AArch64 prep)

[Peter Maydell <peter.maydell@linaro.org>]

This patch series is preparatory cleanup for the impending
AArch64 support.

Patch 1 replaces all the uses of TCGv, tcg_temp_new(), etc in the
current 32 bit ARM decoder with the specifically-TCGv_i32 versions. 
This is necessary for supporting a 64-bit core, which will have
TARGET_LONG_BITS==64 (and so TCGv == TCGv_i64) but still wants 32 bit
vaddrs, register sizes, etc in the A32/T32/T16 instruction sets.  The
mechanical conversion is correct for everything except the arguments
to tcg_gen_qemu_{ld,st}*, which we handle separately later.

Patches 2-9 remove the gen_ld* and gen_st* helper functions in favour
of open-coding the creation/deletion of the TCG temp.  I think this
makes the code easier to understand because the temp creation and
deletion is all at the same level of the code and it reduces the
current confusing situation where some gen_ functions will destroy a
temp they're passed and some will not.  I think it also brings it
closer into line with other targets.  That said, if there's pushback
that this part of the patchset is going in the wrong direction I can
drop it.  (Conversely, if people like it then there are other
functions like load_reg() and store_reg() which could also be changed
not to create/destroy temporaries.)

Patch 10 fixes the load/store bits that patch 1 did not, by
abstracting out "AArch32 load/store" into gen functions which
extend/truncate the 32 bit values to 64 bits as necessary.  NB that
the TARGET_LONG_BITS==64 parts are only compile-tested.  I include it
in this series because it completes the work that patch 1 starts,
and as motivation/indication of direction.

Peter Maydell (10):
  target-arm: Don't use TCGv when we mean TCGv_i32
  target-arm: Remove gen_ld64() and gen_st64()
  target-arm: Remove uses of gen_{ld,st}* from iWMMXt code
  target-arm: Remove uses of gen_{ld,st}* from Neon code
  target-arm: Remove use of gen_{ld,st}* from ldrex/strex
  target-arm: Remove gen_{ld,st}* from basic ARM insns
  target-arm: Remove gen_{ld,st}* from Thumb insns
  target-arm: Remove gen_{ld,st}* from thumb2 decoder
  target-arm: Remove gen_{ld,st}* definitions
  target-arm: Abstract out load/store from a vaddr in AArch32

 target-arm/translate.c |  862 +++++++++++++++++++++++++++---------------------
 1 file changed, 490 insertions(+), 372 deletions(-)

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1.7.9.5