From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "John Rigby" <john.rigby@linaro.org>,
patches@linaro.org, "Blue Swirl" <blauwirbel@gmail.com>,
"Andreas Färber" <afaerber@suse.de>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH 07/10] target-arm: Remove gen_{ld, st}* from Thumb insns
Date: Thu, 23 May 2013 13:00:01 +0100 [thread overview]
Message-ID: <1369310404-5285-8-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1369310404-5285-1-git-send-email-peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/translate.c | 71 +++++++++++++++++++++++++++++++-----------------
1 file changed, 46 insertions(+), 25 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e5a2e4c..953c5fb 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9217,7 +9217,8 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
val &= ~(uint32_t)2;
addr = tcg_temp_new_i32();
tcg_gen_movi_i32(addr, val);
- tmp = gen_ld32(addr, IS_USER(s));
+ tmp = tcg_temp_new_i32();
+ tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
tcg_temp_free_i32(addr);
store_reg(s, rd, tmp);
break;
@@ -9412,37 +9413,43 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
tcg_gen_add_i32(addr, addr, tmp);
tcg_temp_free_i32(tmp);
- if (op < 3) /* store */
+ if (op < 3) { /* store */
tmp = load_reg(s, rd);
+ } else {
+ tmp = tcg_temp_new_i32();
+ }
switch (op) {
case 0: /* str */
- gen_st32(tmp, addr, IS_USER(s));
+ tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
break;
case 1: /* strh */
- gen_st16(tmp, addr, IS_USER(s));
+ tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
break;
case 2: /* strb */
- gen_st8(tmp, addr, IS_USER(s));
+ tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
break;
case 3: /* ldrsb */
- tmp = gen_ld8s(addr, IS_USER(s));
+ tcg_gen_qemu_ld8s(tmp, addr, IS_USER(s));
break;
case 4: /* ldr */
- tmp = gen_ld32(addr, IS_USER(s));
+ tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
break;
case 5: /* ldrh */
- tmp = gen_ld16u(addr, IS_USER(s));
+ tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
break;
case 6: /* ldrb */
- tmp = gen_ld8u(addr, IS_USER(s));
+ tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
break;
case 7: /* ldrsh */
- tmp = gen_ld16s(addr, IS_USER(s));
+ tcg_gen_qemu_ld16s(tmp, addr, IS_USER(s));
break;
}
- if (op >= 3) /* load */
+ if (op >= 3) { /* load */
store_reg(s, rd, tmp);
+ } else {
+ tcg_temp_free_i32(tmp);
+ }
tcg_temp_free_i32(addr);
break;
@@ -9456,12 +9463,14 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << 11)) {
/* load */
- tmp = gen_ld32(addr, IS_USER(s));
+ tmp = tcg_temp_new_i32();
+ tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
store_reg(s, rd, tmp);
} else {
/* store */
tmp = load_reg(s, rd);
- gen_st32(tmp, addr, IS_USER(s));
+ tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ tcg_temp_free_i32(tmp);
}
tcg_temp_free_i32(addr);
break;
@@ -9476,12 +9485,14 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << 11)) {
/* load */
- tmp = gen_ld8u(addr, IS_USER(s));
+ tmp = tcg_temp_new_i32();
+ tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
store_reg(s, rd, tmp);
} else {
/* store */
tmp = load_reg(s, rd);
- gen_st8(tmp, addr, IS_USER(s));
+ tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
+ tcg_temp_free_i32(tmp);
}
tcg_temp_free_i32(addr);
break;
@@ -9496,12 +9507,14 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << 11)) {
/* load */
- tmp = gen_ld16u(addr, IS_USER(s));
+ tmp = tcg_temp_new_i32();
+ tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
store_reg(s, rd, tmp);
} else {
/* store */
tmp = load_reg(s, rd);
- gen_st16(tmp, addr, IS_USER(s));
+ tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
+ tcg_temp_free_i32(tmp);
}
tcg_temp_free_i32(addr);
break;
@@ -9515,12 +9528,14 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << 11)) {
/* load */
- tmp = gen_ld32(addr, IS_USER(s));
+ tmp = tcg_temp_new_i32();
+ tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
store_reg(s, rd, tmp);
} else {
/* store */
tmp = load_reg(s, rd);
- gen_st32(tmp, addr, IS_USER(s));
+ tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ tcg_temp_free_i32(tmp);
}
tcg_temp_free_i32(addr);
break;
@@ -9586,12 +9601,14 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << i)) {
if (insn & (1 << 11)) {
/* pop */
- tmp = gen_ld32(addr, IS_USER(s));
+ tmp = tcg_temp_new_i32();
+ tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
store_reg(s, i, tmp);
} else {
/* push */
tmp = load_reg(s, i);
- gen_st32(tmp, addr, IS_USER(s));
+ tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ tcg_temp_free_i32(tmp);
}
/* advance to the next address. */
tcg_gen_addi_i32(addr, addr, 4);
@@ -9601,13 +9618,15 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << 8)) {
if (insn & (1 << 11)) {
/* pop pc */
- tmp = gen_ld32(addr, IS_USER(s));
+ tmp = tcg_temp_new_i32();
+ tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
/* don't set the pc until the rest of the instruction
has completed */
} else {
/* push lr */
tmp = load_reg(s, 14);
- gen_st32(tmp, addr, IS_USER(s));
+ tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ tcg_temp_free_i32(tmp);
}
tcg_gen_addi_i32(addr, addr, 4);
}
@@ -9730,7 +9749,8 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << i)) {
if (insn & (1 << 11)) {
/* load */
- tmp = gen_ld32(addr, IS_USER(s));
+ tmp = tcg_temp_new_i32();
+ tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
if (i == rn) {
loaded_var = tmp;
} else {
@@ -9739,7 +9759,8 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
} else {
/* store */
tmp = load_reg(s, i);
- gen_st32(tmp, addr, IS_USER(s));
+ tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ tcg_temp_free_i32(tmp);
}
/* advance to the next address */
tcg_gen_addi_i32(addr, addr, 4);
--
1.7.9.5
next prev parent reply other threads:[~2013-05-23 12:25 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-23 11:59 [Qemu-devel] [PATCH 00/10] target-arm: fix TCGv usage (AArch64 prep) Peter Maydell
2013-05-23 11:59 ` [Qemu-devel] [PATCH 01/10] target-arm: Don't use TCGv when we mean TCGv_i32 Peter Maydell
2013-05-23 16:43 ` Richard Henderson
2013-05-23 11:59 ` [Qemu-devel] [PATCH 02/10] target-arm: Remove gen_ld64() and gen_st64() Peter Maydell
2013-05-23 16:44 ` Richard Henderson
2013-05-23 11:59 ` [Qemu-devel] [PATCH 03/10] target-arm: Remove uses of gen_{ld, st}* from iWMMXt code Peter Maydell
2013-05-23 16:46 ` Richard Henderson
2013-05-23 11:59 ` [Qemu-devel] [PATCH 04/10] target-arm: Remove uses of gen_{ld, st}* from Neon code Peter Maydell
2013-05-23 11:59 ` [Qemu-devel] [PATCH 05/10] target-arm: Remove use of gen_{ld, st}* from ldrex/strex Peter Maydell
2013-05-23 12:00 ` [Qemu-devel] [PATCH 06/10] target-arm: Remove gen_{ld, st}* from basic ARM insns Peter Maydell
2013-05-23 12:00 ` Peter Maydell [this message]
2013-05-23 12:00 ` [Qemu-devel] [PATCH 08/10] target-arm: Remove gen_{ld, st}* from thumb2 decoder Peter Maydell
2013-05-23 12:00 ` [Qemu-devel] [PATCH 09/10] target-arm: Remove gen_{ld, st}* definitions Peter Maydell
2013-05-23 12:00 ` [Qemu-devel] [PATCH 10/10] target-arm: Abstract out load/store from a vaddr in AArch32 Peter Maydell
2013-05-23 16:53 ` Richard Henderson
2013-05-24 15:54 ` Peter Maydell
2013-05-26 17:03 ` [Qemu-devel] [PATCH 00/10] target-arm: fix TCGv usage (AArch64 prep) Blue Swirl
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