From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:33518) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UfUav-0003oQ-6M for qemu-devel@nongnu.org; Thu, 23 May 2013 08:26:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UfUao-0005rN-Jw for qemu-devel@nongnu.org; Thu, 23 May 2013 08:26:09 -0400 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:57366 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UfUao-0005qf-CA for qemu-devel@nongnu.org; Thu, 23 May 2013 08:26:02 -0400 From: Peter Maydell Date: Thu, 23 May 2013 13:00:02 +0100 Message-Id: <1369310404-5285-9-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1369310404-5285-1-git-send-email-peter.maydell@linaro.org> References: <1369310404-5285-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 08/10] target-arm: Remove gen_{ld, st}* from thumb2 decoder List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: John Rigby , patches@linaro.org, Blue Swirl , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Richard Henderson Signed-off-by: Peter Maydell --- target-arm/translate.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 953c5fb..0ca68fe 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -8134,18 +8134,22 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw } if (insn & (1 << 20)) { /* ldrd */ - tmp = gen_ld32(addr, IS_USER(s)); + tmp = tcg_temp_new_i32(); + tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); store_reg(s, rs, tmp); tcg_gen_addi_i32(addr, addr, 4); - tmp = gen_ld32(addr, IS_USER(s)); + tmp = tcg_temp_new_i32(); + tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); store_reg(s, rd, tmp); } else { /* strd */ tmp = load_reg(s, rs); - gen_st32(tmp, addr, IS_USER(s)); + tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = load_reg(s, rd); - gen_st32(tmp, addr, IS_USER(s)); + tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + tcg_temp_free_i32(tmp); } if (insn & (1 << 21)) { /* Base writeback. */ @@ -8181,10 +8185,12 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw /* tbh */ tcg_gen_add_i32(addr, addr, tmp); tcg_temp_free_i32(tmp); - tmp = gen_ld16u(addr, IS_USER(s)); + tmp = tcg_temp_new_i32(); + tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s)); } else { /* tbb */ tcg_temp_free_i32(tmp); - tmp = gen_ld8u(addr, IS_USER(s)); + tmp = tcg_temp_new_i32(); + tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s)); } tcg_temp_free_i32(addr); tcg_gen_shli_i32(tmp, tmp, 1); @@ -8219,9 +8225,11 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw if ((insn & (1 << 24)) == 0) tcg_gen_addi_i32(addr, addr, -8); /* Load PC into tmp and CPSR into tmp2. */ - tmp = gen_ld32(addr, 0); + tmp = tcg_temp_new_i32(); + tcg_gen_qemu_ld32u(tmp, addr, 0); tcg_gen_addi_i32(addr, addr, 4); - tmp2 = gen_ld32(addr, 0); + tmp2 = tcg_temp_new_i32(); + tcg_gen_qemu_ld32u(tmp2, addr, 0); if (insn & (1 << 21)) { /* Base writeback. */ if (insn & (1 << 24)) { @@ -8259,7 +8267,8 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw continue; if (insn & (1 << 20)) { /* Load. */ - tmp = gen_ld32(addr, IS_USER(s)); + tmp = tcg_temp_new_i32(); + tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); if (i == 15) { gen_bx(s, tmp); } else if (i == rn) { @@ -8271,7 +8280,8 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw } else { /* Store. */ tmp = load_reg(s, i); - gen_st32(tmp, addr, IS_USER(s)); + tcg_gen_qemu_st32(tmp, addr, IS_USER(s)); + tcg_temp_free_i32(tmp); } tcg_gen_addi_i32(addr, addr, 4); } -- 1.7.9.5