From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47494) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UkDVW-0006Tm-OJ for qemu-devel@nongnu.org; Wed, 05 Jun 2013 09:12:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UkDVU-0006iZ-8L for qemu-devel@nongnu.org; Wed, 05 Jun 2013 09:12:06 -0400 Received: from mail-qe0-f42.google.com ([209.85.128.42]:44798) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UkDJr-0001qf-GO for qemu-devel@nongnu.org; Wed, 05 Jun 2013 09:00:03 -0400 Received: by mail-qe0-f42.google.com with SMTP id s14so1007598qeb.29 for ; Wed, 05 Jun 2013 06:00:03 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 5 Jun 2013 05:59:26 -0700 Message-Id: <1370437167-11278-2-git-send-email-rth@twiddle.net> In-Reply-To: <1370437167-11278-1-git-send-email-rth@twiddle.net> References: <1370437167-11278-1-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 1/2] tcg: Use QEMU_BUILD_BUG_ON for CPU_TLB_ENTRY_BITS List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@us.ibm.com Rather than a hand-coded version of the same thing. Reviewed-by: Andreas Färber Reviewed-by: liguang Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index d8c64e9..2e5a9ba 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -99,7 +99,7 @@ typedef struct CPUTLBEntry { sizeof(uintptr_t))]; } CPUTLBEntry; -extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BITS) ? 1 : -1]; +QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); #define CPU_COMMON_TLB \ /* The meaning of the MMU modes is defined in the target code. */ \ -- 1.8.1.4