From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34566) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UkeZc-0001f6-Q6 for qemu-devel@nongnu.org; Thu, 06 Jun 2013 14:06:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UkeZY-0000yn-8c for qemu-devel@nongnu.org; Thu, 06 Jun 2013 14:06:08 -0400 Received: from mail-pd0-f174.google.com ([209.85.192.174]:33304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UkeZY-0000yf-1e for qemu-devel@nongnu.org; Thu, 06 Jun 2013 14:06:04 -0400 Received: by mail-pd0-f174.google.com with SMTP id 10so2690779pdc.5 for ; Thu, 06 Jun 2013 11:06:03 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 6 Jun 2013 11:05:45 -0700 Message-Id: <1370541947-909-4-git-send-email-rth@twiddle.net> In-Reply-To: <1370541947-909-1-git-send-email-rth@twiddle.net> References: <1370541947-909-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 3/5] tcg-arm: Make use of conditional availability of opcodes for divide List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net We can now detect and use divide instructions at runtime, rather than having to restrict their availability to compile-time. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 16 ++++++++++++++-- tcg/arm/tcg-target.h | 14 ++++++++------ 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 3d43412..f6bc165 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -67,6 +67,13 @@ static const int use_armv7_instructions = 0; #endif #undef USE_ARMV7_INSTRUCTIONS +#ifndef use_idiv_instructions +bool use_idiv_instructions; +#endif +#ifdef CONFIG_GETAUXVAL +# include +#endif + #ifndef NDEBUG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { "%r0", @@ -2041,18 +2048,23 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, -#if TCG_TARGET_HAS_div_i32 { INDEX_op_div_i32, { "r", "r", "r" } }, { INDEX_op_rem_i32, { "r", "r", "r" } }, { INDEX_op_divu_i32, { "r", "r", "r" } }, { INDEX_op_remu_i32, { "r", "r", "r" } }, -#endif { -1 }, }; static void tcg_target_init(TCGContext *s) { +#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions) + { + unsigned long hwcap = getauxval(AT_HWCAP); + use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT); + } +#endif + #if !defined(CONFIG_USER_ONLY) /* fail safe */ if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 3be41cc..4e1a88f 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -49,6 +49,13 @@ typedef enum { #define TCG_TARGET_NB_REGS 16 +#ifdef __ARM_ARCH_EXT_IDIV__ +#define use_idiv_instructions 1 +#else +extern bool use_idiv_instructions; +#endif + + /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_R13 #define TCG_TARGET_STACK_ALIGN 8 @@ -73,12 +80,7 @@ typedef enum { #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 1 - -#ifdef __ARM_ARCH_EXT_IDIV__ -#define TCG_TARGET_HAS_div_i32 1 -#else -#define TCG_TARGET_HAS_div_i32 0 -#endif +#define TCG_TARGET_HAS_div_i32 use_idiv_instructions extern bool tcg_target_deposit_valid(int ofs, int len); #define TCG_TARGET_deposit_i32_valid tcg_target_deposit_valid -- 1.8.1.4