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* [Qemu-devel] [PATCH 0/5] tcg-arm: Runtime detection of architecture
@ 2013-06-06 18:05 Richard Henderson
  2013-06-06 18:05 ` [Qemu-devel] [PATCH 1/5] tcg: Allow non-constant control macros Richard Henderson
                   ` (5 more replies)
  0 siblings, 6 replies; 10+ messages in thread
From: Richard Henderson @ 2013-06-06 18:05 UTC (permalink / raw)
  To: qemu-devel; +Cc: aurelien

Two prepatory generic tcg patches, to allow non-constant values for
the various TCG_TARGET_HAS_foo macros.

When in patch 3 this gets used, the code inlined in the translators
will be able to check the relevant variable and emit either division
opcode or the call to the division subroutine.

Perhaps more valuable is being able to generate armv7 insns when
running on e.g. an cortex-a15, even when the OS distribution is
built for a more generic armv5.

Tested on an a15, and with various hacks to force each of the unused
code paths to be used.


r~


Richard Henderson (5):
  tcg: Allow non-constant control macros
  tcg: Simplify logic using TCG_OPF_NOT_PRESENT
  tcg-arm: Make use of conditional availability of opcodes for divide
  tcg-arm: Simplify logic in detecting the ARM ISA in use
  tcg-arm: Use AT_PLATFORM to detect the host ISA

 tcg/arm/tcg-target.c | 82 +++++++++++++++++++++++++++-------------------------
 tcg/arm/tcg-target.h | 14 +++++----
 tcg/tcg-opc.h        | 28 ++++++++++--------
 tcg/tcg.c            |  4 +--
 tcg/tcg.h            |  3 +-
 5 files changed, 69 insertions(+), 62 deletions(-)

-- 
1.8.1.4

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 3/5] tcg-arm: Make use of conditional availability of opcodes for divide
@ 2013-06-26 14:00 Claudio Fontana
  0 siblings, 0 replies; 10+ messages in thread
From: Claudio Fontana @ 2013-06-26 14:00 UTC (permalink / raw)
  To: Richard Henderson; +Cc: qemu-devel@nongnu.org

Richard wrote (eons ago):
> We can now detect and use divide instructions at runtime, rather than
> having to restrict their availability to compile-time.
> 
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  tcg/arm/tcg-target.c | 16 ++++++++++++++--
>  tcg/arm/tcg-target.h | 14 ++++++++------
>  2 files changed, 22 insertions(+), 8 deletions(-)
> 
> diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
> index 3d43412..f6bc165 100644
> --- a/tcg/arm/tcg-target.c
> +++ b/tcg/arm/tcg-target.c
> @@ -67,6 +67,13 @@ static const int use_armv7_instructions = 0;
>  #endif
>  #undef USE_ARMV7_INSTRUCTIONS
>  
> +#ifndef use_idiv_instructions
> +bool use_idiv_instructions;
> +#endif
> +#ifdef CONFIG_GETAUXVAL
> +# include <sys/auxv.h>
> +#endif
> +
>  #ifndef NDEBUG
>  static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
>      "%r0",
> @@ -2041,18 +2048,23 @@ static const TCGTargetOpDef arm_op_defs[] = {
>  
>      { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
>  
> -#if TCG_TARGET_HAS_div_i32
>      { INDEX_op_div_i32, { "r", "r", "r" } },
>      { INDEX_op_rem_i32, { "r", "r", "r" } },
>      { INDEX_op_divu_i32, { "r", "r", "r" } },
>      { INDEX_op_remu_i32, { "r", "r", "r" } },
> -#endif
>  
>      { -1 },
>  };
>  
>  static void tcg_target_init(TCGContext *s)
>  {
> +#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
> +    {
> +        unsigned long hwcap = getauxval(AT_HWCAP);
> +        use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);
> +    }
> +#endif
> +
>  #if !defined(CONFIG_USER_ONLY)
>      /* fail safe */
>      if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
> index 3be41cc..4e1a88f 100644
> --- a/tcg/arm/tcg-target.h
> +++ b/tcg/arm/tcg-target.h
> @@ -49,6 +49,13 @@ typedef enum {
>  
>  #define TCG_TARGET_NB_REGS 16
>  
> +#ifdef __ARM_ARCH_EXT_IDIV__
> +#define use_idiv_instructions  1
> +#else
> +extern bool use_idiv_instructions;
> +#endif
> +
> +
>  /* used for function call generation */
>  #define TCG_REG_CALL_STACK             TCG_REG_R13
>  #define TCG_TARGET_STACK_ALIGN         8
> @@ -73,12 +80,7 @@ typedef enum {
>  #define TCG_TARGET_HAS_deposit_i32      1
>  #define TCG_TARGET_HAS_movcond_i32      1
>  #define TCG_TARGET_HAS_muls2_i32        1
> -
> -#ifdef __ARM_ARCH_EXT_IDIV__
> -#define TCG_TARGET_HAS_div_i32          1
> -#else
> -#define TCG_TARGET_HAS_div_i32          0
> -#endif
> +#define TCG_TARGET_HAS_div_i32          use_idiv_instructions
>  
>  extern bool tcg_target_deposit_valid(int ofs, int len);
>  #define TCG_TARGET_deposit_i32_valid  tcg_target_deposit_valid
> -- 
> 1.8.1.4

this should probably be rebased on latest git imo, because it fails to apply at the moment due to the removal of the assertions on (1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry) etc.

Claudio

^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2013-06-26 14:01 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-06-06 18:05 [Qemu-devel] [PATCH 0/5] tcg-arm: Runtime detection of architecture Richard Henderson
2013-06-06 18:05 ` [Qemu-devel] [PATCH 1/5] tcg: Allow non-constant control macros Richard Henderson
2013-06-06 18:05 ` [Qemu-devel] [PATCH 2/5] tcg: Simplify logic using TCG_OPF_NOT_PRESENT Richard Henderson
2013-06-06 18:05 ` [Qemu-devel] [PATCH 3/5] tcg-arm: Make use of conditional availability of opcodes for divide Richard Henderson
2013-06-06 18:05 ` [Qemu-devel] [PATCH 4/5] tcg-arm: Simplify logic in detecting the ARM ISA in use Richard Henderson
2013-06-06 18:05 ` [Qemu-devel] [PATCH 5/5] tcg-arm: Use AT_PLATFORM to detect the host ISA Richard Henderson
2013-06-10 18:42 ` [Qemu-devel] [PATCH 0/5] tcg-arm: Runtime detection of architecture Richard Henderson
2013-06-17 15:56   ` Richard Henderson
2013-06-25  3:44     ` Richard Henderson
  -- strict thread matches above, loose matches on Subject: below --
2013-06-26 14:00 [Qemu-devel] [PATCH 3/5] tcg-arm: Make use of conditional availability of opcodes for divide Claudio Fontana

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