From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34587) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UkeZg-0001kW-16 for qemu-devel@nongnu.org; Thu, 06 Jun 2013 14:06:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UkeZd-00010e-9S for qemu-devel@nongnu.org; Thu, 06 Jun 2013 14:06:11 -0400 Received: from mail-pb0-x22d.google.com ([2607:f8b0:400e:c01::22d]:51446) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UkeZd-00010O-1G for qemu-devel@nongnu.org; Thu, 06 Jun 2013 14:06:09 -0400 Received: by mail-pb0-f45.google.com with SMTP id mc8so3592808pbc.32 for ; Thu, 06 Jun 2013 11:06:08 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 6 Jun 2013 11:05:47 -0700 Message-Id: <1370541947-909-6-git-send-email-rth@twiddle.net> In-Reply-To: <1370541947-909-1-git-send-email-rth@twiddle.net> References: <1370541947-909-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 5/5] tcg-arm: Use AT_PLATFORM to detect the host ISA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net With this we can generate armv7 insns even when the OS compiles for a lower common denominator. The macros are arranged so that when we do compile for a given ISA, all of the runtime checks for that ISA are optimized away. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 202f1fc..243dedd 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -41,9 +41,11 @@ # endif #endif -#define use_armv5_instructions (__ARM_ARCH >= 5) -#define use_armv6_instructions (__ARM_ARCH >= 6) -#define use_armv7_instructions (__ARM_ARCH >= 7) +static int arm_arch = __ARM_ARCH; + +#define use_armv5_instructions (__ARM_ARCH >= 5 || arm_arch >= 5) +#define use_armv6_instructions (__ARM_ARCH >= 6 || arm_arch >= 6) +#define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7) #ifndef use_idiv_instructions bool use_idiv_instructions; @@ -2036,12 +2038,22 @@ static const TCGTargetOpDef arm_op_defs[] = { static void tcg_target_init(TCGContext *s) { -#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions) +#if defined(CONFIG_GETAUXVAL) + /* Only probe for the platform and capabilities if we havn't already + determined maximum values at compile time. */ +# if !defined(use_idiv_instructions) { unsigned long hwcap = getauxval(AT_HWCAP); use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT); } -#endif +# endif + if (__ARM_ARCH < 7) { + const char *pl = (const char *)getauxval(AT_PLATFORM); + if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { + arm_arch = pl[1] - '0'; + } + } +#endif /* GETAUXVAL */ #if !defined(CONFIG_USER_ONLY) /* fail safe */ -- 1.8.1.4