From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59017) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ull4K-0000Sr-MS for qemu-devel@nongnu.org; Sun, 09 Jun 2013 15:14:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ull4H-0000hs-Em for qemu-devel@nongnu.org; Sun, 09 Jun 2013 15:14:24 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 9 Jun 2013 21:12:55 +0200 Message-Id: <1370805206-26574-29-git-send-email-afaerber@suse.de> In-Reply-To: <1370805206-26574-1-git-send-email-afaerber@suse.de> References: <1370805206-26574-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH qom-cpu 28/59] cpu: Replace cpu_single_env with CPUState cpu_single_cpu List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Anthony Liguori , Alexander Graf , Blue Swirl , =?UTF-8?q?Andreas=20F=C3=A4rber?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Paul Brook , Scott Wood , "open list:mpc8544ds" , Guan Xuetao , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Richard Henderson Fiddle with include order to ensure CPUState is defined before cpu_single_cpu. Signed-off-by: Andreas F=C3=A4rber --- cpu-exec.c | 13 +++++++------ cpus.c | 29 ++++++++++++++--------------- exec.c | 12 +++++++----- hw/alpha/typhoon.c | 16 ++++------------ hw/arm/pxa2xx.c | 3 +-- hw/i386/kvmvapic.c | 6 ++++-- hw/i386/pc.c | 11 ++++++----- hw/intc/arm_gic.c | 3 +-- hw/intc/armv7m_nvic.c | 11 ++++++++--- hw/intc/openpic.c | 5 +---- hw/mips/mips_fulong2e.c | 6 +++--- hw/mips/mips_jazz.c | 6 +++--- hw/mips/mips_malta.c | 6 +++--- hw/misc/vmport.c | 26 ++++++++++++++++---------- hw/ppc/mpc8544_guts.c | 3 ++- hw/ppc/prep.c | 6 +++--- hw/sparc/sun4m.c | 5 ++--- hw/timer/arm_mptimer.c | 2 -- include/exec/cpu-all.h | 4 ++-- memory.c | 6 ++---- target-alpha/cpu.h | 2 +- target-s390x/cpu.h | 3 +-- target-unicore32/cpu.h | 2 +- translate-all.c | 20 ++++++++++++-------- user-exec.c | 6 +++--- 25 files changed, 107 insertions(+), 105 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 31c089d..5d5362d 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -213,12 +213,12 @@ int cpu_exec(CPUArchState *env) cpu->halted =3D 0; } =20 - cpu_single_env =3D env; + cpu_single_cpu =3D cpu; =20 - /* As long as cpu_single_env is null, up to the assignment just abov= e, + /* As long as cpu_single_cpu is null, up to the assignment just abov= e, * requests by other threads to exit the execution loop are expected= to * be issued using the exit_request global. We must make sure that o= ur - * evaluation of the global value is performed past the cpu_single_e= nv + * evaluation of the global value is performed past the cpu_single_c= pu * value transition point, which requires a memory barrier as well a= s * an instruction scheduling constraint on modern architectures. */ smp_mb(); @@ -673,7 +673,8 @@ int cpu_exec(CPUArchState *env) } else { /* Reload env after longjmp - the compiler may have smashed = all * local variables as longjmp is marked 'noreturn'. */ - env =3D cpu_single_env; + cpu =3D cpu_single_cpu; + env =3D cpu->env_ptr; } } /* for(;;) */ =20 @@ -707,7 +708,7 @@ int cpu_exec(CPUArchState *env) #error unsupported target CPU #endif =20 - /* fail safe : never use cpu_single_env outside cpu_exec() */ - cpu_single_env =3D NULL; + /* fail safe : never use cpu_single_cpu outside cpu_exec() */ + cpu_single_cpu =3D NULL; return ret; } diff --git a/cpus.c b/cpus.c index 1453c11..7428389 100644 --- a/cpus.c +++ b/cpus.c @@ -118,10 +118,11 @@ TimersState timers_state; int64_t cpu_get_icount(void) { int64_t icount; - CPUArchState *env =3D cpu_single_env; + CPUState *cpu =3D cpu_single_cpu; =20 icount =3D qemu_icount; - if (env) { + if (cpu) { + CPUArchState *env =3D cpu->env_ptr; if (!can_do_io(env)) { fprintf(stderr, "Bad clock read\n"); } @@ -472,8 +473,8 @@ static void cpu_handle_guest_debug(CPUState *cpu) =20 static void cpu_signal(int sig) { - if (cpu_single_env) { - cpu_exit(ENV_GET_CPU(cpu_single_env)); + if (cpu_single_cpu) { + cpu_exit(cpu_single_cpu); } exit_request =3D 1; } @@ -664,10 +665,10 @@ void run_on_cpu(CPUState *cpu, void (*func)(void *d= ata), void *data) =20 qemu_cpu_kick(cpu); while (!wi.done) { - CPUArchState *self_env =3D cpu_single_env; + CPUState *self_cpu =3D cpu_single_cpu; =20 qemu_cond_wait(&qemu_work_cond, &qemu_global_mutex); - cpu_single_env =3D self_env; + cpu_single_cpu =3D self_cpu; } } =20 @@ -738,7 +739,7 @@ static void *qemu_kvm_cpu_thread_fn(void *arg) qemu_mutex_lock(&qemu_global_mutex); qemu_thread_get_self(cpu->thread); cpu->thread_id =3D qemu_get_thread_id(); - cpu_single_env =3D cpu->env_ptr; + cpu_single_cpu =3D cpu; =20 r =3D kvm_init_vcpu(cpu); if (r < 0) { @@ -786,9 +787,9 @@ static void *qemu_dummy_cpu_thread_fn(void *arg) cpu->created =3D true; qemu_cond_signal(&qemu_cpu_cond); =20 - cpu_single_env =3D cpu->env_ptr; + cpu_single_cpu =3D cpu; while (1) { - cpu_single_env =3D NULL; + cpu_single_cpu =3D NULL; qemu_mutex_unlock_iothread(); do { int sig; @@ -799,7 +800,7 @@ static void *qemu_dummy_cpu_thread_fn(void *arg) exit(1); } qemu_mutex_lock_iothread(); - cpu_single_env =3D cpu->env_ptr; + cpu_single_cpu =3D cpu; qemu_wait_io_event_common(cpu); } =20 @@ -896,8 +897,7 @@ void qemu_cpu_kick(CPUState *cpu) void qemu_cpu_kick_self(void) { #ifndef _WIN32 - assert(cpu_single_env); - CPUState *cpu_single_cpu =3D ENV_GET_CPU(cpu_single_env); + assert(cpu_single_cpu); =20 if (!cpu_single_cpu->thread_kicked) { qemu_cpu_kick_thread(cpu_single_cpu); @@ -915,7 +915,7 @@ bool qemu_cpu_is_self(CPUState *cpu) =20 static bool qemu_in_vcpu_thread(void) { - return cpu_single_env && qemu_cpu_is_self(ENV_GET_CPU(cpu_single_env= )); + return cpu_single_cpu && qemu_cpu_is_self(cpu_single_cpu); } =20 void qemu_mutex_lock_iothread(void) @@ -1070,8 +1070,7 @@ void qemu_init_vcpu(CPUState *cpu) =20 void cpu_stop_current(void) { - if (cpu_single_env) { - CPUState *cpu_single_cpu =3D ENV_GET_CPU(cpu_single_env); + if (cpu_single_cpu) { cpu_single_cpu->stop =3D false; cpu_single_cpu->stopped =3D true; cpu_exit(cpu_single_cpu); diff --git a/exec.c b/exec.c index 2b99bb9..e14a815 100644 --- a/exec.c +++ b/exec.c @@ -73,7 +73,7 @@ static MemoryRegion io_mem_unassigned, io_mem_subpage_r= am; CPUArchState *first_cpu; /* current CPU in the current thread. It is only valid inside cpu_exec() */ -DEFINE_TLS(CPUArchState *,cpu_single_env); +DEFINE_TLS(CPUState *,cpu_single_cpu); /* 0 =3D Do not count executed instructions. 1 =3D Precise instruction counting. 2 =3D Adaptive rate instruction counting. */ @@ -1420,8 +1420,10 @@ static void notdirty_mem_write(void *opaque, hwadd= r ram_addr, cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); /* we remove the notdirty callback only if the code has been flushed */ - if (dirty_flags =3D=3D 0xff) - tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); + if (dirty_flags =3D=3D 0xff) { + CPUArchState *env =3D cpu_single_cpu->env_ptr; + tlb_set_dirty(env, env->mem_io_vaddr); + } } =20 static bool notdirty_mem_accepts(void *opaque, hwaddr addr, @@ -1439,7 +1441,7 @@ static const MemoryRegionOps notdirty_mem_ops =3D { /* Generate a debug exception if a watchpoint has been hit. */ static void check_watchpoint(int offset, int len_mask, int flags) { - CPUArchState *env =3D cpu_single_env; + CPUArchState *env =3D cpu_single_cpu->env_ptr; target_ulong pc, cs_base; target_ulong vaddr; CPUWatchpoint *wp; @@ -1912,7 +1914,7 @@ bool address_space_rw(AddressSpace *as, hwaddr addr= , uint8_t *buf, if (is_write) { if (!memory_access_is_direct(section->mr, is_write)) { l =3D memory_access_size(l, addr1); - /* XXX: could force cpu_single_env to NULL to avoid + /* XXX: could force cpu_single_cpu to NULL to avoid potential bugs */ if (l =3D=3D 4) { /* 32 bit write access */ diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 207dcad..f0b1f6f 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -72,9 +72,8 @@ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) =20 static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) { - CPUAlphaState *env =3D cpu_single_env; + CPUState *cpu =3D cpu_single_cpu; TyphoonState *s =3D opaque; - CPUState *cpu; uint64_t ret =3D 0; =20 if (addr & 4) { @@ -95,7 +94,6 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, u= nsigned size) =20 case 0x0080: /* MISC: Miscellaneous Register. */ - cpu =3D ENV_GET_CPU(env); ret =3D s->cchip.misc | (cpu->cpu_index & 3); break; =20 @@ -197,8 +195,7 @@ static uint64_t cchip_read(void *opaque, hwaddr addr,= unsigned size) break; =20 default: - cpu =3D CPU(alpha_env_get_cpu(cpu_single_env)); - cpu_unassigned_access(cpu, addr, false, false, 0, size); + cpu_unassigned_access(cpu_single_cpu, addr, false, false, 0, siz= e); return -1; } =20 @@ -215,7 +212,6 @@ static uint64_t dchip_read(void *opaque, hwaddr addr,= unsigned size) static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) { TyphoonState *s =3D opaque; - CPUState *cs; uint64_t ret =3D 0; =20 if (addr & 4) { @@ -302,8 +298,7 @@ static uint64_t pchip_read(void *opaque, hwaddr addr,= unsigned size) break; =20 default: - cs =3D CPU(alpha_env_get_cpu(cpu_single_env)); - cpu_unassigned_access(cs, addr, false, false, 0, size); + cpu_unassigned_access(cpu_single_cpu, addr, false, false, 0, siz= e); return -1; } =20 @@ -315,7 +310,6 @@ static void cchip_write(void *opaque, hwaddr addr, uint64_t v32, unsigned size) { TyphoonState *s =3D opaque; - CPUState *cpu_single_cpu =3D CPU(alpha_env_get_cpu(cpu_single_env)); uint64_t val, oldval, newval; =20 if (addr & 4) { @@ -480,7 +474,6 @@ static void pchip_write(void *opaque, hwaddr addr, uint64_t v32, unsigned size) { TyphoonState *s =3D opaque; - CPUState *cs; uint64_t val, oldval; =20 if (addr & 4) { @@ -582,8 +575,7 @@ static void pchip_write(void *opaque, hwaddr addr, break; =20 default: - cs =3D CPU(alpha_env_get_cpu(cpu_single_env)); - cpu_unassigned_access(cs, addr, true, false, 0, size); + cpu_unassigned_access(cpu_single_cpu, addr, true, false, 0, size= ); return; } } diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 24b03a0..d023167 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -301,8 +301,7 @@ static int pxa2xx_pwrmode_write(CPUARMState *env, con= st ARMCPRegInfo *ri, #endif =20 /* Suspend */ - cpu_interrupt(CPU(arm_env_get_cpu(cpu_single_env)), - CPU_INTERRUPT_HALT); + cpu_interrupt(cpu_single_cpu, CPU_INTERRUPT_HALT); =20 goto message; =20 diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index f93629f..9aac9de 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -623,11 +623,13 @@ static int vapic_prepare(VAPICROMState *s) static void vapic_write(void *opaque, hwaddr addr, uint64_t data, unsigned int size) { - CPUX86State *env =3D cpu_single_env; + CPUState *cs =3D cpu_single_cpu; + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; hwaddr rom_paddr; VAPICROMState *s =3D opaque; =20 - cpu_synchronize_state(CPU(x86_env_get_cpu(env))); + cpu_synchronize_state(cs); =20 /* * The VAPIC supports two PIO-based hypercalls, both via port 0x7E. diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 145efce..71d9019 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -880,8 +880,9 @@ void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) =20 DeviceState *cpu_get_current_apic(void) { - if (cpu_single_env) { - return cpu_single_env->apic_state; + if (cpu_single_cpu) { + X86CPU *cpu =3D X86_CPU(cpu_single_cpu); + return cpu->env.apic_state; } else { return NULL; } @@ -1100,10 +1101,10 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus = *pci_bus) =20 static void cpu_request_exit(void *opaque, int irq, int level) { - CPUX86State *env =3D cpu_single_env; + CPUState *cpu =3D cpu_single_cpu; =20 - if (env && level) { - cpu_exit(CPU(x86_env_get_cpu(env))); + if (cpu && level) { + cpu_exit(cpu); } } =20 diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index bae6572..79fd4a9 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -39,8 +39,7 @@ static const uint8_t gic_id[] =3D { static inline int gic_get_current_cpu(GICState *s) { if (s->num_cpu > 1) { - CPUState *cpu =3D ENV_GET_CPU(cpu_single_env); - return cpu->cpu_index; + return cpu_single_cpu->cpu_index; } return 0; } diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 25fa43c..53576c8 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -140,6 +140,7 @@ void armv7m_nvic_complete_irq(void *opaque, int irq) =20 static uint32_t nvic_readl(nvic_state *s, uint32_t offset) { + ARMCPU *cpu; uint32_t val; int irq; =20 @@ -171,7 +172,8 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t of= fset) case 0x1c: /* SysTick Calibration Value. */ return 10000; case 0xd00: /* CPUID Base. */ - return cpu_single_env->cp15.c0_cpuid; + cpu =3D ARM_CPU(cpu_single_cpu); + return cpu->env.cp15.c0_cpuid; case 0xd04: /* Interrupt Control State. */ /* VECTACTIVE */ val =3D s->gic.running_irq[0]; @@ -206,7 +208,8 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t of= fset) val |=3D (1 << 31); return val; case 0xd08: /* Vector Table Offset. */ - return cpu_single_env->v7m.vecbase; + cpu =3D ARM_CPU(cpu_single_cpu); + return cpu->env.v7m.vecbase; case 0xd0c: /* Application Interrupt/Reset Control. */ return 0xfa05000; case 0xd10: /* System Control. */ @@ -279,6 +282,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t of= fset) =20 static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) { + ARMCPU *cpu; uint32_t oldval; switch (offset) { case 0x10: /* SysTick Control and Status. */ @@ -331,7 +335,8 @@ static void nvic_writel(nvic_state *s, uint32_t offse= t, uint32_t value) } break; case 0xd08: /* Vector Table Offset. */ - cpu_single_env->v7m.vecbase =3D value & 0xffffff80; + cpu =3D ARM_CPU(cpu_single_cpu); + cpu->env.v7m.vecbase =3D value & 0xffffff80; break; case 0xd0c: /* Application Interrupt/Reset Control. */ if ((value >> 16) =3D=3D 0x05fa) { diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index c788714..6f152e0 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -184,13 +184,10 @@ static int output_to_inttgt(int output) =20 static int get_current_cpu(void) { - CPUState *cpu_single_cpu; - - if (!cpu_single_env) { + if (!cpu_single_cpu) { return -1; } =20 - cpu_single_cpu =3D ENV_GET_CPU(cpu_single_env); return cpu_single_cpu->cpu_index; } =20 diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index 00c9071..59ee1b4 100644 --- a/hw/mips/mips_fulong2e.c +++ b/hw/mips/mips_fulong2e.c @@ -250,10 +250,10 @@ static void network_init (void) =20 static void cpu_request_exit(void *opaque, int irq, int level) { - CPUMIPSState *env =3D cpu_single_env; + CPUState *cpu =3D cpu_single_cpu; =20 - if (env && level) { - cpu_exit(CPU(mips_env_get_cpu(env))); + if (cpu && level) { + cpu_exit(cpu); } } =20 diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 2ad0c0b..2ffae59 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -99,10 +99,10 @@ static const MemoryRegionOps dma_dummy_ops =3D { =20 static void cpu_request_exit(void *opaque, int irq, int level) { - CPUMIPSState *env =3D cpu_single_env; + CPUState *cpu =3D cpu_single_cpu; =20 - if (env && level) { - cpu_exit(CPU(mips_env_get_cpu(env))); + if (cpu && level) { + cpu_exit(cpu); } } =20 diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 8a4459d..4fc611c 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -770,10 +770,10 @@ static void main_cpu_reset(void *opaque) =20 static void cpu_request_exit(void *opaque, int irq, int level) { - CPUMIPSState *env =3D cpu_single_env; + CPUState *cpu =3D cpu_single_cpu; =20 - if (env && level) { - cpu_exit(CPU(mips_env_get_cpu(env))); + if (cpu && level) { + cpu_exit(cpu); } } =20 diff --git a/hw/misc/vmport.c b/hw/misc/vmport.c index 7026481..f8b16b6 100644 --- a/hw/misc/vmport.c +++ b/hw/misc/vmport.c @@ -62,11 +62,13 @@ static uint64_t vmport_ioport_read(void *opaque, hwad= dr addr, unsigned size) { VMPortState *s =3D opaque; - CPUX86State *env =3D cpu_single_env; + CPUState *cs =3D cpu_single_cpu; + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; unsigned char command; uint32_t eax; =20 - cpu_synchronize_state(CPU(x86_env_get_cpu(env))); + cpu_synchronize_state(cs); =20 eax =3D env->regs[R_EAX]; if (eax !=3D VMPORT_MAGIC) @@ -89,29 +91,32 @@ static uint64_t vmport_ioport_read(void *opaque, hwad= dr addr, static void vmport_ioport_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - CPUX86State *env =3D cpu_single_env; + X86CPU *cpu =3D X86_CPU(cpu_single_cpu); =20 - env->regs[R_EAX] =3D vmport_ioport_read(opaque, addr, 4); + cpu->env.regs[R_EAX] =3D vmport_ioport_read(opaque, addr, 4); } =20 static uint32_t vmport_cmd_get_version(void *opaque, uint32_t addr) { - CPUX86State *env =3D cpu_single_env; - env->regs[R_EBX] =3D VMPORT_MAGIC; + X86CPU *cpu =3D X86_CPU(cpu_single_cpu); + + cpu->env.regs[R_EBX] =3D VMPORT_MAGIC; return 6; } =20 static uint32_t vmport_cmd_ram_size(void *opaque, uint32_t addr) { - CPUX86State *env =3D cpu_single_env; - env->regs[R_EBX] =3D 0x1177; + X86CPU *cpu =3D X86_CPU(cpu_single_cpu); + + cpu->env.regs[R_EBX] =3D 0x1177; return ram_size; } =20 /* vmmouse helpers */ void vmmouse_get_data(uint32_t *data) { - CPUX86State *env =3D cpu_single_env; + X86CPU *cpu =3D X86_CPU(cpu_single_cpu); + CPUX86State *env =3D &cpu->env; =20 data[0] =3D env->regs[R_EAX]; data[1] =3D env->regs[R_EBX]; data[2] =3D env->regs[R_ECX]; data[3] =3D env->regs[R_EDX]; @@ -120,7 +125,8 @@ void vmmouse_get_data(uint32_t *data) =20 void vmmouse_set_data(const uint32_t *data) { - CPUX86State *env =3D cpu_single_env; + X86CPU *cpu =3D X86_CPU(cpu_single_cpu); + CPUX86State *env =3D &cpu->env; =20 env->regs[R_EAX] =3D data[0]; env->regs[R_EBX] =3D data[1]; env->regs[R_ECX] =3D data[2]; env->regs[R_EDX] =3D data[3]; diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c index 193beab..89f950f 100644 --- a/hw/ppc/mpc8544_guts.c +++ b/hw/ppc/mpc8544_guts.c @@ -62,7 +62,8 @@ static uint64_t mpc8544_guts_read(void *opaque, hwaddr = addr, unsigned size) { uint32_t value =3D 0; - CPUPPCState *env =3D cpu_single_env; + PowerPCCPU *cpu =3D POWERPC_CPU(cpu_single_cpu); + CPUPPCState *env =3D &cpu->env; =20 addr &=3D MPC8544_GUTS_MMIO_SIZE - 1; switch (addr) { diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 4dbb36e..83ceb7b 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -417,10 +417,10 @@ static const MemoryRegionOps PPC_prep_io_ops =3D { =20 static void cpu_request_exit(void *opaque, int irq, int level) { - CPUPPCState *env =3D cpu_single_env; + CPUState *cpu =3D cpu_single_cpu; =20 - if (env && level) { - cpu_exit(CPU(ppc_env_get_cpu(env))); + if (cpu && level) { + cpu_exit(cpu); } } =20 diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 0e86ca7..1273533 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -264,9 +264,8 @@ static void secondary_cpu_reset(void *opaque) =20 static void cpu_halt_signal(void *opaque, int irq, int level) { - if (level && cpu_single_env) { - cpu_interrupt(CPU(sparc_env_get_cpu(cpu_single_env)), - CPU_INTERRUPT_HALT); + if (level && cpu_single_cpu) { + cpu_interrupt(cpu_single_cpu, CPU_INTERRUPT_HALT); } } =20 diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 317f5e4..1aa300b 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -49,8 +49,6 @@ typedef struct { =20 static inline int get_current_cpu(ARMMPTimerState *s) { - CPUState *cpu_single_cpu =3D ENV_GET_CPU(cpu_single_env); - if (cpu_single_cpu->cpu_index >=3D s->num_cpu) { hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n", s->num_cpu, cpu_single_cpu->cpu_index); diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index e19acf2..a0ca585 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -357,8 +357,8 @@ CPUArchState *cpu_copy(CPUArchState *env); void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) GCC_FMT_ATTR(2, 3); extern CPUArchState *first_cpu; -DECLARE_TLS(CPUArchState *,cpu_single_env); -#define cpu_single_env tls_var(cpu_single_env) +DECLARE_TLS(CPUState *,cpu_single_cpu); +#define cpu_single_cpu tls_var(cpu_single_cpu) =20 /* Flags for use in ENV->INTERRUPT_PENDING. =20 diff --git a/memory.c b/memory.c index 74daf03..3810030 100644 --- a/memory.c +++ b/memory.c @@ -857,8 +857,7 @@ static uint64_t unassigned_mem_read(void *opaque, hwa= ddr addr, #ifdef DEBUG_UNASSIGNED printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); #endif - cpu_unassigned_access(ENV_GET_CPU(cpu_single_env), addr, false, fals= e, 0, - size); + cpu_unassigned_access(cpu_single_cpu, addr, false, false, 0, size); return 0; } =20 @@ -868,8 +867,7 @@ static void unassigned_mem_write(void *opaque, hwaddr= addr, #ifdef DEBUG_UNASSIGNED printf("Unassigned mem write " TARGET_FMT_plx " =3D 0x%"PRIx64"\n", = addr, val); #endif - cpu_unassigned_access(ENV_GET_CPU(cpu_single_env), addr, true, false= , 0, - size); + cpu_unassigned_access(cpu_single_cpu, addr, true, false, 0, size); } =20 static bool unassigned_mem_accepts(void *opaque, hwaddr addr, diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 01f4ebb..78f3c73 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -294,8 +294,8 @@ struct CPUAlphaState { #define cpu_gen_code cpu_alpha_gen_code #define cpu_signal_handler cpu_alpha_signal_handler =20 -#include "exec/cpu-all.h" #include "cpu-qom.h" +#include "exec/cpu-all.h" =20 enum { FEATURE_ASN =3D 0x00000001, diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index 6304c4d..dab862a 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -40,8 +40,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 62 #define TARGET_VIRT_ADDR_SPACE_BITS 64 =20 -#include "exec/cpu-all.h" - #include "fpu/softfloat.h" =20 #define NB_MMU_MODES 3 @@ -151,6 +149,7 @@ typedef struct CPUS390XState { } CPUS390XState; =20 #include "cpu-qom.h" +#include "exec/cpu-all.h" =20 #if defined(CONFIG_USER_ONLY) static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp= ) diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index 5b2b9d1..ba77cb0 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -155,8 +155,8 @@ static inline void cpu_set_tls(CPUUniCore32State *env= , target_ulong newtls) env->regs[16] =3D newtls; } =20 -#include "exec/cpu-all.h" #include "cpu-qom.h" +#include "exec/cpu-all.h" #include "exec/exec-all.h" =20 static inline void cpu_pc_from_tb(CPUUniCore32State *env, TranslationBlo= ck *tb) diff --git a/translate-all.c b/translate-all.c index 40b8f3d..c399a28 100644 --- a/translate-all.c +++ b/translate-all.c @@ -997,8 +997,10 @@ void tb_invalidate_phys_page_range(tb_page_addr_t st= art, tb_page_addr_t end, int is_cpu_write_access) { TranslationBlock *tb, *tb_next, *saved_tb; - CPUArchState *env =3D cpu_single_env; - CPUState *cpu =3D NULL; + CPUState *cpu =3D cpu_single_cpu; +#if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY) + CPUArchState *env =3D NULL; +#endif tb_page_addr_t tb_start, tb_end; PageDesc *p; int n; @@ -1021,9 +1023,11 @@ void tb_invalidate_phys_page_range(tb_page_addr_t = start, tb_page_addr_t end, /* build code bitmap */ build_page_bitmap(p); } - if (env !=3D NULL) { - cpu =3D ENV_GET_CPU(env); +#if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY) + if (cpu !=3D NULL) { + env =3D cpu->env_ptr; } +#endif =20 /* we remove all the TBs in the range [start, end[ */ /* XXX: see if in some cases it could be faster to invalidate all @@ -1145,8 +1149,8 @@ static void tb_invalidate_phys_page(tb_page_addr_t = addr, int n; #ifdef TARGET_HAS_PRECISE_SMC TranslationBlock *current_tb =3D NULL; - CPUArchState *env =3D cpu_single_env; - CPUState *cpu =3D NULL; + CPUState *cpu =3D cpu_single_cpu; + CPUArchState *env =3D NULL; int current_tb_modified =3D 0; target_ulong current_pc =3D 0; target_ulong current_cs_base =3D 0; @@ -1163,8 +1167,8 @@ static void tb_invalidate_phys_page(tb_page_addr_t = addr, if (tb && pc !=3D 0) { current_tb =3D tb_find_pc(pc); } - if (env !=3D NULL) { - cpu =3D ENV_GET_CPU(env); + if (cpu !=3D NULL) { + env =3D cpu->env_ptr; } #endif while (tb !=3D NULL) { diff --git a/user-exec.c b/user-exec.c index 71bd6c5..c512cef 100644 --- a/user-exec.c +++ b/user-exec.c @@ -94,7 +94,7 @@ static inline int handle_cpu_signal(uintptr_t pc, unsig= ned long address, } =20 /* see if it is an MMU fault */ - ret =3D cpu_handle_mmu_fault(cpu_single_env, address, is_write, + ret =3D cpu_handle_mmu_fault(cpu_single_cpu->env_ptr, address, is_wr= ite, MMU_USER_IDX); if (ret < 0) { return 0; /* not an MMU fault */ @@ -103,12 +103,12 @@ static inline int handle_cpu_signal(uintptr_t pc, u= nsigned long address, return 1; /* the MMU fault was handled without causing real CPU = fault */ } /* now we have a real cpu fault */ - cpu_restore_state(cpu_single_env, pc); + cpu_restore_state(cpu_single_cpu->env_ptr, pc); =20 /* we restore the process signal mask as the sigreturn should do it (XXX: use sigsetjmp) */ sigprocmask(SIG_SETMASK, old_set, NULL); - exception_action(cpu_single_env); + exception_action(cpu_single_cpu->env_ptr); =20 /* never comes here */ return 1; --=20 1.8.1.4